Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: The invention includes an adjustable offset differential amplifier. The adjustable offset differential amplifier includes a first differential transistor receiving a first differential input, and a second differential transistor receiving a second differential input. A differential amplifier output includes an amplitude proportional to a difference between the first differential input and the second differential input. The first differential transistor includes a plurality of sub first differential transistors. Each sub first differential transistor includes an adjustable back gate bias. Control circuitry can be connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

Abstract: MRAM noise stabilizing and reducing apparatus and methods for MRAM sensing operations injects noise generated by activation of a word line (80, 82, 84, 86) into a sense line (128) and a reference line (130). Sense strings (20, 22, 24, 26) addressed by the word line (80, 82, 84, 86) are alternately coupled to the sense line (128) and the reference line (130). Cross coupling reduces the noise injected on the sense lines (128, 130). Cross coupling also balances the noise created by activation of the word line (80, 82, 84, 86) between the sense line (128) and reference line (130). A sense string (20, 22, 24, 26) not addressed by the word line (80, 82, 84, 86) provides a reference signal. A differential amplifier (132) includes circuitry to compare and store a difference between the sense line (128) and the reference line (130). The stored value can be further compared to a second value obtained by reversing the current on the word line (80, 82, 84, 86).

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.

Abstract: Exemplar embodiments are disclosed which allow errors in a magnetoresistive solid-state storage device, such as a magnetic random access memory (MRAM) device, to be minimized. An illustrative method includes the steps of identifying cells in the device which have a failure mode characterized by a propensity to remain in a particular orientation of magnetization, mapping the location of the identified cells, and compensating for the failure mode of a cell at a mapped location. Systems and computer readable media are also provided.

Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

Abstract: A sensing circuit for determining the logic state of each memory cell in a resistive memory array, wherein each memory cell in the resistive memory array has current control isolation and the logic state of each memory cell can be determined relative to a reference cell having a pre-selected logic state. The sensing circuit comprises a memory cell sensing circuit to determine a bias voltage of a memory cell, a reference cell sensing circuit to determine a bias voltage of a reference cell, an isolation circuit to apply an isolation voltage to turn off a current control element associated with each unselected memory cell, an adjusting circuit to make the bias voltage on the memory cell approximately equal to the bias voltage on the reference cell, and a state determining circuit for determining the logic state of the memory cell.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: Capacitors are provided for changing the voltage level of data lines, respectively, in a data reading operation. A signal line electrically coupled to capacitors is provided. Capacitors charge data lines in accordance with the voltage level of signal line by capacitive coupling. Thus, data lines can be charged quickly to achieve a fast data reading operation.

Abstract: The invention includes a memory cell sensor. The memory cell sensor includes an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment of the invention includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: A magnetic memory includes memory cells configured to store first data bits. Compare logic is configured to compare the first data bits to second data bits and provide an indication for each first data bit that has a same logic state as a corresponding second data bit.

Abstract: A reference cell circuit for a magnetic tunnel junction MRAM includes a first magnetic tunnel junction device set to a low resistance state and a second magnetic tunnel junction device set to a high resistance state. A reference cell series unit includes the first magnetic tunnel junction device electrically coupled in series with the second magnetic tunnel junction device. The reference cell series unit further has a first end and a second end with the first end being electrically coupled to a first current source and the second end being electrically coupled to a current sink and a second current source.

Abstract: An information storage device is disclosed. In one embodiment, the information storage device includes first and second memory cells which store complementary first and second logic states. An error detection system coupled to the first and second memory cells is configured to indicate an error if a difference between a first current flowing through the first memory cell and a second current flowing through the second memory cell is less than a predefined value.

Abstract: An adjustable current mode differential sense amplifier is provided. The amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier.

Abstract: A semiconductor memory device has a memory cell array which includes memory cells arranged in a matrix form, word lines, bit lines, a decoding circuit and sense unit. The decoding circuit is supplied with an address signal and a first control signal and drives a selected word line which is the word line specified by the address signal or an adjacent word line which is the word line adjacent to the selected word line on the basis of the first control signal. The sense unit is connected to the bit line and reads data stored in the memory cell which is connected to the word line driven by the decoding circuit.

Abstract: A memory system that generates a reference voltage unaffected by supply voltage variations and is suitable for performing burn-in test is attainable by employing the following configuration. For example, in an MRAM containing a TMR element (Rij) and an N channel MOS transistor (Mij), as memory element, there is disposed a switching circuit (SW1) capable of switching between the state of applying a reference voltage (VrefN) to a memory element and the state of applying a reference voltage (VrefB) for burn-in test having a larger value than the reference voltage (VrefN) to the memory element. At the time of burn-in test, instead of the reference voltage (VrefN) for normal read operation, the reference voltage (VrefB) for burn-in test can be applied via a sense circuit (SC) to the memory element, by applying mode change signals (MODE1 to MODEn) from the exterior and operating the switching circuit (SW1) via a decode circuit (TD).

Abstract: A resistive memory device (40) and method of manufacturing thereof including magnetic memory cells (14) having a second magnetic layer (20) including at least a first and second material (24/26). The Curie temperature of the second material (26) is lower than the Curie temperature of the first material (24). A plurality of non-continuous second conductive lines (22) are disposed over the magnetic memory cells (14). A current (28) may be run through the second conductive lines (22) to increase the temperature of the second material (26) to a temperature greater than the second material (26) Curie temperature, causing the second material (26) to lose its ferromagnetic properties, providing increased write selectivity to the memory array (40).

Abstract: A reference cell circuit for a magnetic tunnel junction MRAM includes two magnetic tunnel junctions where one is always set to a low resistance state and the other is always set to a high resistance state. The two magnetic tunnel junctions are connected between two segments of a bit line. The reference cell also includes a digit line that crosses both of the bit line segments.

Abstract: A method and apparatus for sensing a resistive state of a resistive memory element includes producing a first current related to a resistance of a memory cell. The first current is added to a second current during a first sensing time and subtracted from a third current during a second sensing time. The first, second and third currents are integrated over time using a capacitor, and a resulting voltage signal on the capacitor is timed using a clocked counter. A time average value of a digital output of the clocked counter is then related to the resistance of the memory cell, and hence to the resistive state of the resistive memory element.

Abstract: A magnetic memory includes memory cells configured to store first data bits. Compare logic is configured to compare the first data bits to second data bits and provide an indication for each first data bit that has a same logic state as a corresponding second data bit.

Abstract: Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.

Abstract: An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier.

Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

Abstract: Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: A system and method for determining the logic state of a memory cell in a magnetic tunnel junction (MTJ) memory device based on the ratio of the current through the cell at different bias points are disclosed. A memory cell in an MJT memory device is sequentially subjected to at least two different bias voltages. The current through the cell at each of the bias voltages is measured, and a ratio of the different currents is determined. The ratio is then compared with a predetermined value to determine the logic state of the cell. The predetermined value can be a known value. Alternatively, the predetermined value can be determined by application of the system and method to a reference cell having a known logic state.

Abstract: A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and electrically conductive hard mask material on the memory element. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.

Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

Abstract: A magnetic memory element is written to by heating the memory element and applying at least one magnetic field to the memory element. The memory element is heated via heating lines which can be formed in a single path or plurality of paths. Each path has one end tied to a reference potential, and the other end coupled to a current source via a transistor.

Abstract: In data read operation, a data line receives a data read current from a data read current supply circuit, and is electrically coupled to a selected memory cell. A switch circuit sequentially connects first to third nodes to the data line one by one. Read data indicating storage data of the selected memory cell is produced based on comparison between the respective voltages on the first to third nodes held by first to third voltage holding capacitors. The switch circuit transmits a data line voltage corresponding to the storage data of the selected memory cell to the first node, a data line voltage corresponding to data “1” stored in the selected memory cell to the second node, and a data line voltage corresponding to data “0” stored in the selected memory cell to the third node.

Abstract: An information recording and reproducing method for a magnetic memory including a variable resistor having a first magnetic layer for storing information on a basis of a direction of magnetization, a non-magnetic layer, and a second magnetic layer having a coercive force that is smaller than a coercive force of the first magnetic layer, the variable resistor exhibiting different resistances according to magnetization directions of the first magnetic layer and the second magnetic layer, the information recording and reproducing method including the steps of: initializing the second magnetic layer in a first magnetization direction; detecting a resistance value of the variable resistor and holding the detected resistance value as a first resistance value; detecting a second resistance value by reversing magnetization of the second magnetization layer in a second magnetization direction and comparing the first resistance value with the second resistance value; and reproducing information according to a result of

Abstract: Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

Abstract: A dummy cell circuit, used in semiconductor memory capable of high-speed operation without inviting enlargement of the chip size even when using a paraelectric capacitor, includes at least one paraelectric capacitor and have a specific relation between potentials applied to its terminals. For example, in a standby mode, a first terminal of the paraelectric capacitor is precharged to a first potential higher than ground potential whereas a second terminal of the paraelectric capacitor is pre-charged to ground potential. In an active mode, the first terminal is connected to one of paired bit lines, which is a reference bit line to which data is not read-out from memory cell, and the second terminal is raised from ground potential to a second potential higher than ground potential.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

Abstract: A resistive cross point memory (RXPtM) cell array device, one example of which is a magnetic random access memory (MRAM) device, includes a chip on which is formed an array of RXPtM cells, an array of sense amplifiers used in sensing resistance values of the RXPtM cells, and an input/output (I/O) controller. The I/O controller includes a calibration controller, which tests the combination of a particularly selected memory cell and a particular associated one of the array of sense amplifiers in view of then existing environmental conditions, to assure that the sense amplifier has an acceptable calibration. Data integrity of the RXPtM cell array device is assured by a method in which each operation to sense data from the device includes a calibration test, which if not passed results in the sense amplifiers being recalibrated. When proper calibration of the sense amplifies is indicated, then sensing of the data value proceeds.

Abstract: A sense amplifier is provided for reading data in a multiple-state memory cell of a resistive memory array in response to a read voltage applied across the sensed memory cell, including a differential amplifier having first and second input nodes. A sense circuit determines the current in the memory cell with the read voltage applied thereto and applies a sense current representative of the memory cell current to the first input node of the differential amplifier. A reference circuit has first and second resistive elements for applying a reference current to the second input node of the differential amplifier to provide a reference value against which to compare the sense current to determine the state of the memory cell. The first resistive element has a resistance representative of a first state of the memory cell, and the second resistive element has a resistance representative of a second state of the memory cell.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2)(1+Rmin/Rmax), where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell. A reference voltage generator is disclosed which generates the reference voltage and includes an operational amplifier and two MTJ memory cells connected to provide an output signal equal to (Vbias1/2)(1+Rmin/Rmax).

Abstract: The fabrication process of a conventional MRAM using a magnetoresistive effect element as a memory device is difficult, and the device structure makes it difficult to decrease the cell area and increase the degree of integration. It is an object of this invention to realize an MRAM which can achieve a high integration degree. A memory device is characterized by including a magnetoresistive element, a bit line formed above this magnetoresistive element, and a write line. The magnetoresistive element is formed immediately above the drain region of a field-effect transistor.

Abstract: An MRAM memory array has nonlinear word lines and linear bit lines. The word lines cross the bit lines at memory cell locations, and are substantially coextensive with the bit lines at the crossing points. When a current is passed through the word and bit lines, the magnetic fields generated by the word line and the bit line at a coextensive portion are substantially aligned. The magnitude of the resultant field is therefore greater than in conventional, orthogonally oriented fields. Because the addition of the fields generated by the word and bit lines is enhanced, smaller word and bit line currents can be utilized, which reduces the size required for the memory array. The memory array can also utilize memory cells having a magnetic layer for producing a transverse magnetic field. The transverse field is orthogonally oriented to the magnetic field generated by the word and bit lines, and increases the reproducibility of switching of the memory cell.

Abstract: The invention described herein defines a system and a method for selectively controlling the sensitivity of a region of a magnetoresistive element to an incident magnetic field, by applying an external magnetic field to the magnetoresistive element. A number of applications to non-volatile data storage are described, as is a magnetic sweep element based on a FET structure. Finally, the storage media and recording modes (in-plane vs. perpendicular) best suited to the proposed applications are analyzed, and the desired or optimal characteristics of the proposed devices are discussed.

Abstract: A magnetic memory unit includes at least one magnetic resistor, whose magnetized direction represent bit information stored in the magnetic memory unit, at least one read line, a current source for providing the magnetic resistor a bias current to produce an output voltage, and a sensing circuit for sensing the output voltage. The sensing circuit includes several components and has a symmetrical structure, so as to avoid defects while sensing the bit information stored in the magnetic memory unit.

Abstract: A magnetic memory unit includes at least one magnetic resistor, whose magnetized direction represent bit information stored in the magnetic memory unit, at least one read line, a current source for providing the magnetic resistor a bias current to produce an output voltage, and a sensing circuit for sensing the output voltage. The sensing circuit includes several components and has a symmetrical structure, so as to avoid defects while sensing the bit information stored in the magnetic memory unit.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2) (1+Rmin/Rmax) where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell.

Abstract: A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

Abstract: A method for nondestructively reading memory cells of an MRAM memory, which includes steps of: determining a standard resistance of a memory cell at a voltage at which a resistance of the memory cell is independent of a stored content of the memory cell; determining an actual resistance or of the memory cell at a voltage at which the resistance of the memory cell is dependent on the stored content of the memory cell; obtaining a normalized actual resistance of the memory cell by to dividing the actual resistance or by the standard resistance; obtaining a comparison result by comparing the normalized actual resistance with a reference value; and detecting the stored content of the memory cell dependent on the comparison result.

Abstract: An equal potential may be applied to a selected bit line and unselected bit lines during a read operation on a memory cell in a resistive cross point array. In the alternative, an equal potential may be applied to the selected bit line and unselected word lines.