Abstract: Resistance of a memory cell element in a resistive cross point memory cell array is sensed by a read circuit including a differential amplifier, a first direct injection preamplifier and a second direct injection preamplifier. During a read operation, the first direct injection preamplifier is coupled to a first input node of the differential amplifier, and the second direct injection preamplifier is coupled to a second input node of the differential amplifier.

Abstract: A current conveyor for readout of a magnetic tunneling junction memory cell is coupled to a data readout line connected to at least one MTJ memory cell. The current conveyor includes a FET with a source terminal coupled to a current source and a drain terminal coupled to the data readout line. The gate terminal of the FET is connected to an output terminal of an operational amplifier connected to receive negative feedback from the data readout line and to receive a bias voltage on a second input terminal. The current conveyor has very low input impedance so that minimum data readout line swing is achieved.

Abstract: A current sensing amplifier for detecting a small current difference between a pair of variable resistance loads comprises a first amplifier and a second amplifier. The first amplifier comprises a voltage clamp including first and second outputs, the voltage clamp being coupled to the pair of variable resistance loads and substantially fixing a predetermined voltage across the variable resistance loads, the voltage clamp transferring the measured current difference to the first and second outputs. The first amplifier further includes a differential current source coupled to the first and second outputs. The second amplifier includes first and second inputs and an output, the first and second inputs being coupled to the first and second outputs, respectively, of the first amplifier.

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a differential amplifier, a first current mode preamplifier coupled to a sense node of the differential amplifier, and a second current mode preamplifier coupled to a reference node of the differential amplifier. During a read operation, the first preamplifier applies a regulated voltage to the selected memory cell, and the second preamplifier applies a regulated voltage to a reference cell. A sense current flows through the selected memory cell and to the sense node of the differential amplifier, while a reference current flows through the reference cell and to the reference node of the differential amplifier. Resulting is a differential voltage across sense and reference nodes. The differential voltage indicates whether a logic value of ‘0’ or ‘1’ is stored in the selected memory cell.

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory ("MRAM") device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and an analog sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier generates an input signal having a transition that is time-delayed according to the voltage on the integrator capacitor; generates a reference signal having a time-fixed transition; and compares a relative occurrence of transitions in the input and reference signals. The relative occurrence indicates whether a logic value of `0` or `1` is stored in the selected memory cell.

Abstract: A new and improved magnetic device is provided for memories and sensors. A magnetic random access memory (MRAM) device (20) includes a storage element (21) for magnetically storing states and an amplifier (25) for sensing the states stored in the storage element. A circuit (27) for dissipating electrical charges are coupled to inputs (23,24) of the amplifier (25) to discharge electrical charges applied to the inputs (23,24) of the amplifier (25). The charge dissipating circuit (27) includes junctions (271-274) which are typically connected in series between power (255) and common (257) lines. Electric charges applied to the inputs (23,24) of the amplifier (25) is discharged through the junctions (271-274).

Abstract: A composition of materials having ferromagnetic, piezoelectric, and electro-optical properties is disclosed. In the preferred embodiment, the composition of materials comprises a first layer of Pb(.sub.1-x-y) Cd.sub.x Si.sub.y, a second layer of Se.sub.(1-z) S.sub.z, and a third layer of Fe.sub.(1-w) Cr.sub.w , where x, y, z and w are values within the ranges of 0.09.ltoreq.x.ltoreq.0.11, 0.09.ltoreq.y.ltoreq.0.11, 0.09.ltoreq.x.ltoreq.0.11 and 0.18.ltoreq.w.ltoreq.0.30. Additionally, each of the layers contain at least one of the elements of Ag, Bi, O, and N. A random-accessible, non-volatile memory built using the invented composition of materials is also disclosed. This memory provides for storing two independent bits of binary information in a single memory cell.

Abstract: A housing for integrated circuit structures containing magnetic thin film which has permeable protective layers parallel thereto.

Abstract: A small, very low cost, wide margin core memory couples a return current drive scheme with a crossover-free sense winding extending parallel to the Y drive conductors to eliminate the assembly time and wasted substrate space associated with sense winding crossovers. The return currents generate small noise signals which cancel with partial select noise signals to provide noise signals comparable to a 3 wire, 3D bow tie sense winding.

Abstract: A highly efficient core memory drive system passes currents down a selected X and Y conductor and divides the currents for return through the unselected drive wires in the same X or Y dimension. The drive conductors are coupled to drive and sink switches at a drive end and the X conductors are connected together at an opposite common end and the Y conductors are connected together at an opposite common end. Resistors provide a current path between the drive end of each X conductor and an X resistor bus and between the drive end of each Y conductor and a Y resistor bus. A pair of switching transistors including a sink transistor and a drive transistor is connected to a drive end of each conductor to generate a drive current therein. The drive current divides equally among the unselected conductors at the common end to return through the unselected conductors and through the resistors to the resistor bus.

Abstract: A core memory system includes a plurality of word lines strung through a core memory array and a plurality of field effect transistors coupling respective ones of the word select lines to an address decoding circuit. In one embodiment of the invention, the field effect transistors are utilized in conjunction with a transformer selection system. In the transformer selection system, the drain electrodes of each field effect transistor are connected in series with respective ones of a plurality of secondary windings of a transformer. The system includes a plurality of such transformers, the primary windings of the various transformers being selected in response to a first decoder. The gates of the respective field effect transistors are selected in response to a second decoder.

Abstract: A core memory utilizes an auxiliary core that is driven concurrently with selected data cores to increase tolerances by automatically tracking the peaking time and the output magnitude. Wide variations in both the magnitude and duration of core output switching signals are compensated by use of the auxiliary core to control the sensing strobe time during a read part cycle and drive current duration during both read and write part cycles. Subtracting half of the auxiliary core output switching signal from a selected data core output switching signal normalizes the difference about zero volts with a one being indicated by the presence of a positive voltage and a zero by a negative voltage. With the reference threshold at zero there is no precise adjustment. Since the peak of the auxiliary core output tracks the peak of the selected data core output, substantial changes in the peaking and switching times do not interfere with accurate determinations of data core data states.

Abstract: Organizations are disclosed for driving bit lines of a two-line 21/2D coincident current magnetic core memory in which a bit line not used for reading a bit out of a core is placed physically in parallel with the bit line driven by half select current to approximate in the unused line the capacitive and inductive coupling of the driven line with the word drive line. That coupling produces in the unused line the same noise (crosstalk) produced in the driven bit line by the word drive pulse. The crosstalk signal in the unused line is subtracted from the signal in the driven bit line before amplification and detection. The unused line may be a separate dummy line, or simply another bit line not being used for the bit being read out. In the case of paired bit lines used for common mode rejection of the bit drive signal, a second pair of unused bit lines is arranged in parallel for crosstalk cancellation.

Abstract: An impedance is connected by a switching circuit, to sense/inhibit windings of a core memory at the end of each memory cycle. The result is an effectively decreased time constant for the core windings which permits faster memory operation. The circuit further reverse biases diodes connected to the input terminals of a sense amplifier during a read cycle thereby increasing the isolation of this amplifier from the effects of inhibit current pulses occurring during a memory read cycle.

Abstract: A circuit arrangement is disclosed for sensing a presence or absence of a low-level output signal which may be used for detecting a change of resistance in a magnetic bubble detector. The circuit operates in a D.C. coupling mode whereby the low-level signals are directly coupled into a sense amplifier, which is preceded by the circuit above-mentioned. The circuit, which comprises a modified current mirror, is used as a resistance transducer which converts a change of resistance (.DELTA.R) into a direct change of voltage (.DELTA.E). The change of voltage provides an indication of the presence of, for example, a magnetic bubble.

Abstract: A core memory system includes an array of toroidal ferrite cores, and also includes two hundred fifty-six X lines extending through a plurality of the cores, one hundred twenty-eight Y lines extending through a plurality of the cores, and eighteen sense-inhibit lines, each extending through a respective plurality of the cores. The X lines are organized as 16 groups, the first ends of all X lines in each respective group being electrically connected together at a common junction. The common junction is connected to a first lead of a first winding of a Balun transformer. The Balun transformer includes 17 identical windings about a toroidal core. The second end of the first winding is connected to the output of an address driver/receiver circuit. The second ends of each of the 16 X lines are connected to the second leads of respective ones of the remaining 16 windings of the Balun transformer. The second leads of each of the 16 windings are connected to respective address driver/receiver circuits.

Abstract: Data can be stored in a 1,2, or 3-dimensional memory by lining up the permanent dipole of small particles using a superposition of ultrasonic pulses and applied fields. Signals due to dipole orientation changes in particles with lower coercive fields than the design coercive field may lead to a large "noise" signal which disturbs the readout. This "noise" signal can be eliminated by applying a field with or without stress to the sample which lines up all dipoles with too low coercive fields. Afterwards the standard procedure to "read" the memory is used, which is undisturbed by the "noise" due to flipping of dipoles with too low coercive fields, if the field applied during "reading" is parallel to the field used to flip particles with too low critical fields.

Abstract: In a magnetic bubble memory device, positive signal lines interconnecting a magnetic bubble memory chip located at substantially the center of an insulating substrate and lead pins at the end of the substrate are surrounded by a plurality of grounded conductors for shielding the positive signal lines so as to decrease noise induced therein by a voltage drop across coils for producing the rotating magnetic field.