Abstract: A method of operating a static random access memory (SRAM) having a column clear function by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using a column clear operation. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared. A subset of columns of a plurality of rows may be cleared by asserting a plurality of column clear signals corresponding to the subset of columns and a plurality of work lines corresponding to the plurality of rows.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: A semiconductor memory device includes a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: An electrically erasable programmable read-only memory cell array has a plurality of memory cells supplied with a supply voltage and a ground voltage. Each memory cell has a storage transistor with a floating gate. For each of selected memory cells, a first voltage higher than both the supply voltage and the ground voltage is applied to the control gate of the storage transistor and a second voltage lower than both the supply voltage and the ground voltage is applied to one of the source/drain electrodes of the storage transistor to thereby erase data in all of the selected memory cells.

Abstract: A nonvolatile multibank memory on a die with multiple read, write, and erase circuits, allowing more than one bank to be read, written, erased, or tested independently. Such a multibank memory arrangement is used advantageously in a monolithic three dimensional memory formed above a substrate, leaving unused substrate area available in which the additional circuitry and related cache memory can be formed.

Abstract: In protecting Flash memory data, a flexible system and method provides for different levels of protection. It offers the ability to dynamically lock a sector of memory using a dynamic protection bit in volatile memory. It offers persistent locking of a sector using a non-volatile bit in memory and locking this status using a lock bit in volatile memory. It offers yet further protection by including a password mode which requires a password to clear the lock bit. The password is located in an unreadable, one time programmable area of the memory. The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner.

Abstract: At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: A semiconductor memory device has a ready/busy pin for detecting a current state of the device. The memory device includes a voltage level detector, a ready/busy driver controller, and a ready/busy driver. The voltage level detector checks if the internal voltage level has reached a predetermined level, and then generates a power-up signal. The ready/busy driver controller generates a busy enable signal in response to the power-up signal. The ready/busy driver provides the busy enable signal to a ready/busy pin by which it is informed that the memory device is in a busy state.

Abstract: The present invention relates to a method for controlling the access, in a computer, of a memory having an erasure frequently limited by blocks. This memory contains utility memory blocks (NB0, NB1) which are available for a user's access by an address conversion occurring through a pointer panel (AZTO). An erasure utility category (LN0, LN1023) is maintained in the form of a table in association with each address pointer maintained in the form of a table in association with each address pointer (AP0 AP1023). This erasure utility category is increased every time a predetermined erasure-state criteria is reached. The other pointing positions of the erasure utility categories (LN0 LN1023) are further explored in the pointer panel (AZTO) until a lower erasure utility category is found. The corresponding address pointer (AP0 AP1023) is then permuted with the one located at the output with the one located at the output pointer position (AP1).

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

Abstract: Method and apparatus for the erase of non-volatile memory in which holes trapped in the tunnel oxide are reduced.

Abstract: A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

Abstract: A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. A random or pseudo-random number generator outputs a new number in response to individual occurrences of the event, and updates the compressed count when an output of the random number generator matches a predetermined number. The probability of the predetermined number being generated by the random number generator in response to a single event may be varied as the function of some other factor, such as the value of the compressed count, when that provides more useful tracking of the number of events. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems.

Abstract: In a flash memory, error management units which store information on a physical occurrence position of an error which occurred during data reading are prepared by as much as the number of bits which can be corrected by an error correction code, in a redundant portion of a physical page. If the number of positions on which the error have occurred in a same physical page exceeds the number of the prepared error management units, then it is judged that the defect is uncorrectable.

Abstract: Erase operations are performed on a flash memory device by monitoring the entropic nature of the flash memory device. In one implementation, flash abstraction logic, tracks how many physical sectors are free to receive data; track how many physical sectors contain data that is dirty, and compare whether the physical sectors that are free to receive data outnumber the physical sectors that contain data that is dirty. A compactor performs an erase operation of one or more blocks when the physical sectors that contain data that is dirty outnumber the physical sectors that are free to receive data. In another implementation, the flash abstraction logic tracks how many physical sector addresses are free to receive data, and track when the physical sector addresses that are free to receive data are insufficient in quantity to receive write requests from a file system.

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased.

Abstract: In a semiconductor memory device the potential of a semiconductor substrate and that of all of a plurality of word lines are increased to an erase voltage by means of a boosting circuit, and subsequently the potential of the word line selected by a word line selection circuit is decreased, when data of a memory cell is erased.

Abstract: A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.

Abstract: In a semiconductor memory device for performing a memory operation by controlling an internal voltage and a memory operation voltage, a cycle of an internal clock signal is varied in accordance with operation time characteristics of the memory operation.

Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: A state machine and an associated method for achieving a faster response time for an interruption of an erase operation in a flash memory are disclosed. In particular, a state machine having a plurality of interconnected execution cycles is disclosed. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles. The plurality of suspend cycles interrupt the erase operation in response to a suspend command by adjusting one shot timing circuits, timer counters, and timing circuits included in the state machine. The state machine may include a plurality of interconnected groups, each having a plurality of execution cycles.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

Abstract: This method has a step of performing a write-before-erase operation (S21, S22) and a step of performing an erase operation (S23, S24) for a memory cell. A voltage application condition upon the write-before-erase operation is relaxed in comparison with a voltage application condition upon a usual write operation so that a threshold voltage distribution of memory cells after the write-before-erase operation is substantially different from a threshold voltage distribution of memory cells after the usual write operation. According to this data erase method for a nonvolatile semiconductor memory device, stress applied to each memory cell by the write-before-erase operation can be reduced, and hence reliability of a memory cell can be improved.

Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

Abstract: The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

Abstract: In a flash memory, error management units which store information on a physical occurrence position of an error which occurred during data reading are prepared by as much as the number of bits which can be corrected by an error correction code, in a redundant portion of a physical page. If the number of positions on which the error have occurred in a same physical page exceeds the number of the prepared error management units, then it is judged that the defect is uncorrectable.

Abstract: A method of erasing a non-volatile memory. The non-volatile memory is positioned on a substrate of a semiconductor wafer and has a memory array region. The memory array region has memory cells, word lines and a substrate line electrically connected to the substrate of each memory cell in the memory array region. The erasing method is to control a potential difference between a word line not to be erased and the substrate to within a specific range, then supply a predetermined first potential to a word line to be erased, thereafter float the word line not to be erased, and finally supply the substrate line with a predetermined second potential. The potential difference between the first and the second potential drive the charges stored in the floating gate of the memory cell electrically connected to the word line to be erased to move into the channel through the tunneling oxide layer to complete the erasing.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.

Abstract: A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

Abstract: The present invention is in the field of charging a capacitance of a memory cell. Embodiments of the present invention program a memory cell by determining programming pulses to be used to program the memory cell based on a target state and the memory cell's response to previous program pulses.

Abstract: There is provided a boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory including at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity. The boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or a subset of the plurality of asymmetrical blocks.

Abstract: A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information.

Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

Abstract: A system and method for testing a flash memory device having uniform sectors and smaller, “boot” sectors includes determining uniform and boot test limits based on average erase and APDE time periods of the uniform and boot sectors, respectively. In this way, the erase test results for each sector type is compared against test limits that are based only on that sector type, thereby avoiding excessive false rejects.

Abstract: A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD. The I/O is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the I/O and selectively coupling the local wordlines to the VDD node.

Abstract: A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.

Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.

Abstract: A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.

Abstract: A microcomputer is capable of having a CPU calculate a suitable bit rate with respect to a host computer and of setting accordingly an appropriate erasure time forestalling excess erasure of an internally furnished flash memory regardless of the operating frequency of the microcomputer. The microcomputer includes a central processing unit, a non-volatile semiconductor memory, and a terminal which is supplied with a mode set signal. The non-volatile semiconductor memory includes a first block storing a control program and a second block storing data. When the terminal is supplied with a mode set signal for indicating a predetermined mode, if data has previously been written into the second block, such data is erased by the central processing unit. On the other hand, if no data is found in the second block, it is determined that an erase operation is unnecessary and therefore is not performed.