Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.

Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased, after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.

Abstract: The present invention provides an information update count managing method, including: a write step of writing pieces of information in a predetermined order in an information storage area including at least one WORD of a non-volatile memory, wherein information can be written to the non-volatile memory in a unit of WORDs, each WORD including a plurality of bits, and information can be erased from the non-volatile memory in a unit of sectors, each sector including a plurality of WORDS; and a read step of reading out the last piece of information which has been written in the information storage area within a predetermined permitted update count.

Abstract: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.

Abstract: A memory unit and memory module using the same. The memory module at least has a first memory region with a plurality of memory units. In each memory unit, first and access transistors each have a first terminal coupled to one bit line pair respectively. A latch node is coupled between second terminals of the first and second access transistor to latch data. An OR gate has a first input terminal coupled to a word line, an output terminal coupled to gates of the first and second access transistor, and a second input terminal. The second input terminals of the OR gates in all memory units are coupled to a flush line. Invalidation information is written to the latch nodes in the memory units from the bit line pair when the flush line is activated during a flush operation.

Abstract: Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.

Abstract: An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.

Abstract: Flash memory devices having control circuitry to decrease the magnitude of a source voltage of a first polarity during an erase period to increase the magnitude of a control gate voltage of a second polarity applied during the erase period.

Abstract: A removable memory card detachably mounted to a host device. The memory card includes a non-volatile semiconductor memory in which data recorded in the memory is erased as a block of a predetermined data volume. An interface for inputting/outputting data between the data storage device and said host device, and a controller for controlling file management in the semiconductor memory in response to a command from said host device over said interface is also used. Parameters for recording file management data are stored in a system information storage unit. The controller records the file management data in the semiconductor memory when supplied with an initialization command from said host device.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A storage device is provided. The storage device includes a number of storage cells arranged and each having a storage element and an active element including a MOS transistor that controls access to the storage element, and in which applying a voltage to the storage element the resistance value of the storage element changes and information is recorded wherein the resistance value of a storage element after information has been written is prevented from becoming lower than necessary and in which information writing can be easily performed.

Abstract: A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Abstract: A semiconductor memory device comprises a memory array in which memory cells having variable resistive elements (R11 to Rij) whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released and selection transistors (T11 to Tij) comprising N type MOSFETs are arranged with a matrix; programming means for applying the electrical stress to the variable resistive elements (R11 to Rij) to program data into the memory cell; programming state detection means for detecting the variation in the electrical resistance at the time of the programming operation; and programming control means for stopping the application of the electrical stress when the electrical resistance is varied to a predetermined reference value. With this structure, it is possible to constitute the semiconductor memory device in which the time required for programming data is shortened and the programming precision is high.

Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.

Abstract: A nonvolatile semiconductor memory device includes a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate, a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line and the bit line connected to the memory cell, and a pulse voltage applying circuit.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: A system for clearing and programming the memory of an FPGA IC, when the IC is comprised of a plurality of cores. The system clears the memory of the of cores. The system then sequentially verifies completion of clearing memory of each core. The system then provides a programming ready signal to all cores when the memory of a last core has has been cleared. The system then sends the bitstream data to a first core. After the first core is programmed, the balance of the bitstream data is sent to a next core. This process is repeated until all of the cores are programmed.

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in response to detecting an incorrect datum. Various solutions implement column, row and sector redundancy, both in case of erasing and programming.

Abstract: Reducing writes to non-volatile storage in a system for tracking sequence numbers in a communications protocol. In a system which tracks sequence numbers, a sequence number base is kept in non-volatile storage. During normal operation, the value in non-volatile storage is not rewritten until it exceeds the base value in non-volatile storage plus a predetermined update constant. On startup, the sequence number is set to the value in non-volatile storage plus the predetermined update constant.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

Abstract: The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.

Abstract: An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

Abstract: A potential of ?3V is applied to a control gate electrode, a potential of 5V is applied to a pair of impurity regions and a potential of 3V is applied to a semiconductor substrate in a non-volatile semiconductor memory device. Accordingly, electrons existing on one impurity region side in a silicon nitride film move toward that impurity region, and electrons existing on the other impurity region side move toward that impurity region. Furthermore, electrons existing in that part (middle part) of the silicon nitride film which is positioned immediately above a region approximately at the middle point between one impurity region and the other impurity region move toward the semiconductor substrate. Therefore, MPE (Miss Placed Electron) is no longer caused in the non-volatile semiconductor memory device.

Abstract: An object of the invention is to provide a nonvolatile semiconductor memory device and an erase method for a memory cell array that have high degree of freedom and that are capable of quickly and securely implementing data erase and reprogramming. In a memory cell array, memory cells each configured of a variable resistor element for storing information through variations in electric resistance and a selected transistor are arranged in a matrix, and word lines (WL1, . . . , WLm) and bit lines (BL1, . . . , BLn) are arranged to select a predetermined memory cell. For the memory cell array, erase means is provided that sets the electric resistance of the variable resistor element to a predetermined erased state by applying voltage under a predetermined application condition to the word line (WL), bit line (BL), and source line (SL). The erase means switches between a batch-erase mode and an individual-erase mode.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

Abstract: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Abstract: The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

Abstract: In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.

Abstract: Methods and apparatus for storing erase counts in a non-volatile memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a data structure in a non-volatile memory includes a first indicator that provides an indication of a number of times a first block of a plurality of blocks in a non-volatile memory has been erased. The data structure also includes a header that is arranged to contain information relating to the blocks in the non-volatile memory.

Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

Abstract: At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.

Abstract: The disclosure is a semiconductor memory device operable with a multi-sector erase mode for a multiplicity of memory chips, including a cell array, a register circuit containing information for a sector to be erased, an address clock driving circuit for contemporaneously generating an address clock signal from each memory chips, a counter for generating address signals in sequence, a core driver for executing an erase operation for the sector, and a control circuit thereof.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: Method and apparatus for the erase of non-volatile memory in which holes trapped in the tunnel oxide are reduced.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: A recording apparatus for facilitating data erasure operations involving data recorded on a recording medium. Each piece of data recorded on the recording medium may be examined to determine whether it is rerecordable by determining whether the data is already stored in another storage medium. When data erasure is requested, erasure processing may be controlled in accordance with the result of the determination. For example, original data based on data captured by a microphone or a camera (namely, non-rerecordable data) may not be erased (without specific approval by the user). Conversely, rerecordable data copied from another recording medium such as a CD may be erased.

Abstract: A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.