Abstract: A memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

Abstract: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.

Abstract: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal.

Abstract: Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outside of a chip.

Abstract: Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for simultaneously driving a plurality of source lines. The apparatus may include a plurality of source lines coupled to a single source line driver. The apparatus may also include a plurality of dynamic random access memory cells arranged in an array of rows and columns, each dynamic random access memory cell including one or more memory transistors. Each of the one or more memory transistors may include a first region coupled to a first source line of the plurality of source lines, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.

Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.

Abstract: When a free physical block where data is to be written is searched for, a search process for searching for a pair of free physical blocks is first executed using a free physical block search table. Detection of a free non-pair good block is executed only when a pair of free physical block is not detected in the search process using the free physical block search table. When there is a free physical block, two-plane write is executed. When there is no pair of free physical blocks, data is written in an adequately combined non-pair good blocks.

Abstract: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.

Abstract: In a nonvolatile memory system, first raw data is obtained from stored data using a first set of reading parameters. Subsequently, the first raw data is transferred to an ECC circuit where it is decoded. While the first raw data is being transferred and decoded, second raw data is obtained from the same stored data using a second set of reading parameters.

Abstract: A method of scanning over a substrate includes implementing a write mode of the substrate by scanning a probe across a substrate, the probe having a spring cantilever probe mechanically fixed to a probe holding structure, a tip with a nanoscale apex, and an actuator for lateral positioning of the tip; the actuator comprising a thermally switchable element and a heating element for heating the thermally switchable element; and heating the heating element to a given temperature so as to locally soften a portion of the substrate and applying a force to the softened portion of the substrate through the tip so as to create one or more indentation marks in the softened portion of the substrate.

Abstract: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

Abstract: A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.

Abstract: When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.

Abstract: A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports perform a serial I/O data transmission. The banks perform a parallel I/O data transmission with the ports. The global data buses are employed for transmitting data between the ports and the banks. The first I/O controller controls a serial data transmission between the ports and external devices. The second I/O controller controls a parallel data transmission between the ports and the global buses. The test I/O controller generates test commands based on a test command/address (C/A) inputted from the external devices and transmits a test I/O data with the global data bus during a test operation mode.

Abstract: An image memory is composed of a memory cell array, first and second area selecting circuits, and a write circuit. The memory cell array includes memory elements arrayed in rows and columns, each of the memory elements being adapted to store pixel data. The first area selecting circuit is adapted to select a plurality of row addresses at the same time, and the second area selecting circuit is adapted to select a plurality of column addresses at the same time. The write circuit is adapted to write same pixel data into selected memory elements out of the memory elements, the selected memory elements being associated with the selected row addresses and column addresses.

Abstract: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, is provided. The coupling device may include a serial data interface configured to receive data, a parallel data interface configured to transmit data, and a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface.

Abstract: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.

Abstract: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented.

Abstract: A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.

Abstract: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.

Abstract: A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.

Abstract: A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories through serial ports regardless of a physical location and an order of the serial ports. The memory controller also transmits and receives memory data in a serial mode through the serial link connection.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.

Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.

Abstract: A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.

Abstract: Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits. Each memory device is additionally configured to drive zero, one or more data strobes associated with the subset M, and tri-state the remaining data strobes. A memory controller may simultaneously read status information from two or more memory devices in parallel, with each memory device driving a separate subset M of the N-bit bus. Each memory device may serialize the status information, and drive it on the subset M of the bus in burst form. Each memory device may include a configuration register initialized by a memory controller to define its subset M.

Abstract: A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal parallel-interfaced with the external device into the global data bus, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus.

Abstract: A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays, synchronously with the internal clock. In testing the semiconductor memory device according to the present invention, one data is written during a period when an external clock having a cycle of an integer times cycle of the internal clock is fixed to a high level or a low level. With this arrangement, continuous data can be assigned to mutually different mini arrays.

Abstract: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

Abstract: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

Abstract: When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.

Abstract: According to some embodiments, an apparatus is provided comprising a plurality of transmit storage structures each being associated with a storage width, a write block, and a read block. The write block is to receive information having a first width via an interface associated with a configurable width, and the read block is to read the information from the storage structures and is to transmit information to a network line.

Abstract: A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.