Abstract: The purpose of the present invention is to provide a semiconductor memory device which is capable of suppressing an increase in chip surface area and in power consumption resulting from peripheral circuitry even when the capacity thereof becomes large, and which, moreover, does not experience discrepancies in clock skew and the like between I/Os, and which is capable of high speed operation. 4-bit parallel data comprising a 0th through 3rd bit are exchanged simultaneously between memory cell arrays with respect to each I/O pin in DQ0-DQ7. Data of the 0th bit through 3rd bit are inputted and outputted with the exterior in that order via input/output interface circuit 5-1. At data load signal LOAD, flip flop groups 12-0 through 12-3 incorporate the 0th through 3rd bit data corresponding to 8 I/O pins. It is necessary to initially read out the 0th bit parallel data to the exterior, so that flip flop group 12-0 is disposed in closest proximity to the input/output interface circuit 5-1.

Abstract: An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area.

Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

Abstract: A non-volatile memory cell is provided. The non-volatile memory cell includes a first conductivity type semiconductor substrate, second conductivity type source/drain regions longitudinally arranged in a direction to be parallel to each other and separated from each other by a predetermined distance in the semiconductor substrate, such that the second conductive source/drain regions define a channel region therebetween. A tunnel oxide layer is formed on the semiconductor substrate. First conductive layer patterns are formed on the tunnel oxide layer on the channel formation region in the form of islands. Buried oxide layers fill spaces between the adjacent first conductive layer patterns. Second conductive layer patterns are formed on the upper surfaces and the upper side surfaces of the first conductive layer patterns and arranged so that their edges are extended to some surfaces of the buried oxide layers.

Abstract: A digital computer performs read-modify-write (RMW) processing on each bit of a row of memory in parallel, in one operation cycle, comprising: (a) addressing a memory, (b) reading each bit of a row of data from the memory in parallel, (c) performing the same computational operation on each bit of the data in parallel, using an arithmetic logic unit (ALU) in a dedicated processing element, and (d) writing the result of the operation back into the original memory location for each bit in the row.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A test circuit for functionally testing memory devices. The test circuit loads a plurality of data bits into the memory device under test. The test circuit subsequently reads the data bits stored in the memory cells, and detects if the logic level of the data bits read is the complement of the logic level written: The logic level is detected over a duration during which at least two data bits are read.

Abstract: A FIFO circuit with a reduced number of buffers connected to output ports and thereby lowering parasitic capacitance. The FIFO circuit includes an input register for storing data therein supplied from a plurality of input ports. A shifter rearranges the data supplied from the input register and a shift register stores therein and shifts the data supplied from the shifter. A selector circuit selects either the data from the input register or the data from the shift register such that valid data fill places from a least significant side of the output ports. A control circuit controls the input register, the shift register, the shifter, and the selector circuit.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.

Abstract: A high performance random access memory integrated circuit is disclosed in several embodiments, along with various embodiments of associated supporting circuitry, which offers significant power savings in read operations. The integrated circuit is capable of retrieving data words from a memory array either one data word in a single clock cycle or more than one data word in a single clock cycle. For random memory reads, retrieving one data word from the memory array in a clock cycle where the memory array is accessed in response to each read request saves power over retrieving more than one data word from the memory array in the clock cycle. Conversely, if read requests are burst requests (i.e., a first read request immediately followed by advance requests), power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed.

Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: In a data rate converter, input data received in series synchronously with an input clock signal is converted into parallel data so as to be written into a memory, and the written parallel data is read from the memory and converted into serial data synchronously with an output clock signal so as to be outputted. Clock pulses of the input clock signal are counted to obtain an input count value. A ready signal is produced based on the input count value for allowing the start of reading the parallel data from the memory. The ready signal has a pulse width greater than two periods of the output clock signal. A trigger signal is produced upon detection of the second leading or trailing edge of the output clock signal within the pulse width of the ready signal. In response to the trigger signal, clock pulses of the output clock signal are counted to obtain an output count value. A read signal is produced based on the output count value for reading the parallel data from the memory.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the multiple memory blocks, and a burst counter unit. The output registers alternately receive data transferred from the memory cell array. In accordance with the result of counting by the burst counter unit, the data retained in the output registers is output alternately in bursts, whereby the speed of data read operation in the memory is boosted regardless of the operating speed of the memory cell array therein.

Abstract: An integrated circuit first-in, first-out (“FIFO”) memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory (“DRAM”) array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory (“SRAM”) row, or register, interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

Abstract: A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentiall

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations.

Abstract: Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: Registers are arranged along at least opposite two sides of the four sides of a dynamic random access memory cell array. The registers are interconnected via an internal data bus line used for internal data transfer for the memory cell array. At least one register of the registers arranged along the opposite two sides is coupled with an external data bus, and the other register is coupled with an internal circuit via an internal data bus. An external controller which controls an operation in response to an external control signal is provided for the register coupled with an external circuit. An internal controller which controls an operation according to a control signal from the internal circuit is provided for the register coupled with the internal circuit. The external and internal circuits are permitted to simultaneously access the memory cell array only when the external and internal circuits read the data of a memory cell located at the same address of the memory cell array.

Abstract: The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

Abstract: A semiconductor memory apparatus with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array. In an alternative embodiment, the FIFO memory device includes a "Retransmit" feature which allows data to be read from the device multiple times as well as the Read Pointer to be selectively placed under user control.

Abstract: A method and apparatus for selectively enabling individual sets of registers in a row of a register array. One embodiment of the present invention is a register array that has a number of registers arranged in a number of rows and columns. Each row of registers includes N sets of registers, where N is an integer greater than 1. The register array also includes a said selector and N said-selecting enable lines for each row of registers. Each enable line of the N set-selecting enable lines couple the set selector to one set of registers of the N sets of registers in each row. In other words, the set selector enables a particular set of registers (i.e., causes a particular set of registers to output their contents on their output bit lines) by providing an enable signal to the particular set of registers on the enable line that couples the set selector to the particular set of registers.

Abstract: Preferred integrated circuit memory devices have the capability of connecting a sense amplifier to multiple arrays of memory one-at-a-time or simultaneously, in response to first and second control signals, respectively. These memory devices include first and second memory arrays which have first and second pairs of differential input/output lines electrically coupled thereto, respectively. A sense amplifier is also provided having first and second pairs of differential input/output lines. To provide independent or simultaneous access to the first and second memory arrays by the sense amplifier, preferred isolation and equalization circuits are provided.

Abstract: A memory having a SRAM, a DRAM and two external IO ports is provided. The SRAM has three IO ports for enabling the external IO ports and the DRAM to access each and every memory cell in the DRAM. Each SRAM cell is provided with two IO ports coupled to the external IO ports, and with an IO port for transferring data to and from the DRAM. The triple-port SRAM cell comprises three input data lines coupled to a latching circuit for writing data supplied from the external IO ports and the DRAM, and three output data lines coupled to the latching system for reading stored data to the external IO ports and the DRAM. Three write address lines and three read address lines provide addressing of the SRAM cell for data writing and reading operations performed by the external IO ports and the DRAM. Each SRAM cell may be read concurrently via all three ports to make the most current data stored in the SRAM accessible from any port at any time.

Abstract: A method and system of utilizing a memory array device contained within an integrated circuit within the printer device is provided in which data bits are written in a row format, thereby filling an N.times.M memory array device and then read in a column format. An N.times.M memory array device is employed such as a 32.times.32 bit memory array. During the reading phase, data from a computer is read by the memory device in a parallel fashion so that data is written sequentially a row of memory cells, such as B0W0, B1W0, B2W0 . . . etc. Once the memory array is loaded up, the writing phase is accomplished by performing a parallel dump wherein all of the memory cells of the first column are read together such that a column of memory cells, such as B0W0 to B0W31 is read first, a column of memory cells, such as B1W0 to B1W31 is read second, a column of memory cells B2W0 to B2W31 is read third etc. The N.times.M memory array device is read in a column format instead of the standard row format.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: The synchronous memory device includes a data transfer control circuit including a pipeline control circuit which, when serial access is started in a cycle corresponding to two cycles of a clock BCK, does not separate all of the first to third pipeline stages from each other and brings the first pipeline stage and the second pipeline stage into a through state. When serial access is started in a cycle departing from the two cycles of the clock BCK, the pipeline control circuit separates all of the first to third pipeline stages from each other.

Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

Abstract: In a memory device for storing data according to the FIFO principle, an input counter is provided having a value which is modified when data are written into a memory, and having a comparison unit that outputs a status signal concerning presence of data in the memory dependent on a comparison of the counter states. A scanning unit is arranged at the connection between the comparison unit and the input counter. The scanning unit scans the state of the input counter according to a clock signal and outputs the scan result to the comparison unit.

Abstract: A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A method and apparatus for implementing a prefetch scheme in which a plurality of data are simultaneously read from memory cells of sequential addresses synchronized to an external signal and serially transferred from the memory cells to a temporary latch circuit which has a number of bits corresponding to the member of bits in the prefetch scheme. The bits in the temporary latch circuit are multiplexed and sequentially driven out of the memory device. The memory device includes a plurality of memory cells which are connected to an input/output line pair through a plurality of column select gates, each of which is controlled by an independent chip select line. A sense amplifier is connected to the input/output line pair for sensing and amplifying data from the input/output lines and to transmit data to the input/output lines. A data output buffer transfers the data from the sense amplifier to the outside of chip.

Abstract: The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

Abstract: When stored data of a plurality of memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23, MC30 to MC33) arranged in a matrix are sequentially read out, a reading access control circuit (101) outputs a row address and a column address to a row decoder (102) and a reading bit-line selector (103), respectively, for an access to the memory cells. The reading access control circuit (101) outputs the row address and the column address so that an n-type memory cell may be first selected by the reading bit-line selector (103) after activation of the selected reading word line every time one of the reading word lines (RWL0 to RWL3) is selected by the row decoder (102). With this configuration, data can be sequentially read out at higher speed from a plurality of memory cells arranged in a matrix.

Abstract: A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area required for a buffer memory of any given size that is fabricated on integrated circuit. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage call be fabricated using much less chip area per bit than the first and third memory stages.

Abstract: A semiconductor memory device is disclosed which can read a plurality of bit units and which can suppress an increase in current consumption and in chip size even if the number of bits serving as a unit of reading is increased. The semiconductor memory device includes a memory cell array having memory cells arranged in a matrix form such that a plurality of columns are divided into a plurality of sections, a plurality of column selection circuits for selecting each of the columns of the memory cell array, a sense amplifier for sense-amplifying data transferred through the data lines, and a column selection control circuit for controlling the plurality of column selection circuits to select one of the plurality of sections of the memory cell array and one of the columns of the sections and to read bit data from the selected column, sequentially.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is desclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof as permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: The invention once stores PCM data to a memory and after a predetermined time is elapsed, reading in again and making to output whereby makes to delay the PCM data. The invention comprises a memory for once storing a PCM data converted to parallel, a delay time setting circuit for setting a delay time of PCM data, and a comparator and control circuit for comparing a setting value from the delay time setting circuit and a high order 10 bits writing address of the memory and thereby providing an address and control signal for either initiating a high order 10 bits reading address of the memory or else for writing or reading to the memory.