Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device having a main controller including a host interface and a device interface, a first plurality of arrays of magneto-resistive random access memory (MRAM) cells, a first device controller coupled to the device interface and the first plurality of arrays, a second plurality of arrays of MRAM cells, and a second device controller coupled to the device interface and the second plurality of arrays. The first device controller is configured to communicate with the device interface to pass first data between the first plurality of arrays and the host interface, and wherein the second device controller is configured to communicate with the device interface to pass second data between the second plurality of arrays and the host interface.

Abstract: A parallel data outputting circuit equipped with a data inversion function, comprises P number of data comparator means, P number of majority decision circuits, P number of inversion flag generating means and P number of data inversion circuits, these being activated in parallel in one cycle. In generating an inversion flag indicating whether or not the parallel data are to be inverted and output in the inverted state, inversion flags are calculated from outputs of the inversion flag generating means and the inversion flag generating means of a cycle directly previous to a current cycle.

Abstract: A passive matrix-addressable device may include individually addressable cells of a polarizable material. The cells store data in one of two polarization states in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines. The cells are provided in or at the crossings between the word and bit lines and a voltage pulse protocol is used read and write data to cells. During reading, a word line is activated by applying voltage which relative to the potential on all crossing bit lines corresponds to the voltage Vs and data stored in the cells connected to this active word line are determined by detecting the charge values of the cells.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

Abstract: An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits to service an N column driver for a display. Additionally, the architecture of the memory allows for a signal input port for writing the data to the cell while allowing for multiple parallel output ports for reading the data. The unique architecture eliminates the need for addressing logic and refresh circuitry for display applications.

Abstract: The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.

Abstract: Provided are a circuit and a method for transforming a data input/output format of a semiconductor memory device which is capable of generating various types of data patterns when the number of memory cells connected to one column selection line is greater than the number of data input pins. The circuit for transforming a data input/output format of a semiconductor memory device includes a first transmission circuit, a second transmission circuit, and a mode register set (MRS). The first transmission circuit is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells. Here, n and m are natural numbers and m is greater than n. The second transmission circuit is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells.

Abstract: A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A nonvolatile memory device, in a continuous read operation, requires no dummy bytes between receipt of a read command and commencement of a scanning out of a first target data byte. The highest order bits of a range of possible target data bytes are speculatively read while only a partial set of the highest order address bits are received. The proper set of highest order target data bits is available and scanned out at a time a complete target data address is received. During this scan out time, the remainder of the target data byte is read and prepared for scanning out starting at the next highest order bit. In this way, the data byte targeted by a read command is available immediately and continuously after receipt of the full read command and address.

Abstract: A semiconductor integrated circuit device comprises a control unit for switching a mode about the trimming or estimation in an internal circuit, the control unit including a controller capable of realizing the mode switching control about the trimming or estimation by the JTAG method. The controller includes an instruction decoder for decoding an input instruction, a shift scan register circuit for enabling a boundary scan based on the decoded result of the instruction decoder, and an operation controller for controlling the operations of the instruction decoder and the shift scan register circuit. Therefore, the trimming becomes possible after sealing a semiconductor chip into a package.

Abstract: A nonvolatile ferroelectric memory device having a multi-bit control function performs read/write operations by selecting a plurality of cells simultaneously, thereby improving the operation speed of a chip. In the nonvolatile ferroelectric memory device, a plurality of cells are selected at the same time, and stable sensing values of data having a small distribution can be obtained by using average characteristics of a plurality of selected cells. Accordingly, since two or more cells are simultaneously selected and a plurality of bits are read/written in the cells depending on stabilized charge, the operation speed of a chip can be improved.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture.

Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory includes first and second memory cells and a read controller coupled to the first and second memory cells. An output controller coupled to the read controller and to the first and second memory cells, wherein the output controller is configured to receive read data in parallel only from the first or second memory cells which have completed the current read operation regardless of whether both the first and second memory cells have completed the current read operation and convert the parallel data to serial data and shift the parallel data to an output in synchronism with the system clock signal.

Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

Abstract: The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing to the plurality of data banks, pointers associated with the respective banks for identifying table locations suitable for overwriting by upcoming entries, wherein an entry is suitable for overwriting when it is deemed invalid by the inventive system. A preferred embodiment is disclosed involving two ports writing to two banks wherein a plurality of factors is considered in deciding where prospective entries from the two ports will be written in the table. The Factors include, matches between existing and prospective entries, the default designated data bank for a given port, whether two write operations are being attempted simultaneously, and the number of entries already present in each data bank.

Abstract: The present invention involves a synchronous semiconductor memory device having a 4-bit prefetch mode a method of processing a data thereof, comprising first to fourth memory cell arrays each having memory cells, a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data, a data loation control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays, by a sequential method or by an interleaving method, during the write operation, a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays, and location-controlling and outputting them in response the first to fourth decoding signals, by a sequential method or by an interleaving method, during a read

Abstract: A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).

Abstract: There is provided a display driver incorporating a RAM in which a plurality of memory cells having a three-port configuration can be provided within an interval of output electrodes thereof, and a display unit and an electronic apparatus utilizing the same. The memory cells include a flip-flop comprised of first and second inverters. A first node of the flip-flop is connected to a CPU bit line and an RGB bit line through an N-type MOS transistor. A P-type MOS transistor and an N-type MOS transistor are connected to a second node of the flip-flop. The N-type MOS transistor is connected to a ground potential level at the source terminal thereof. A set signal for each pixel is supplied to the gate terminal of only the flip-flop associated with the pixel to be written, and the set signal sets the second node at the ground potential level.

Abstract: A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n×n (e.g., four) memory cells alternatively selected according to a combination of n (e.g., two) pairs of positive and negative phase signals and provided to output the positive and negative phase signals according to the data stored in the selected memory cell, variable wiring unit provided with signal lines for inter-connecting the variable logical circuits and switching elements for connecting/disconnecting signal lines inter-secting to each other, a wiring connection state storage memory circuit where the states of the switching elements are stored.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: The semiconductor memory device comprises a plurality of data output terminals outputting in parallel data of a plurality of bits, the number of bits being a plurality of times as large as the number of the plurality of data output terminals, an address transition detecting circuit to output a latch control signal, and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel in each read cycle is held by a latch circuit, and the data held by the latch circuit is divided by a plural number and one group of the divided data is outputted to the plurality of data output terminals during the cycle, with the remaining group of divided data being outputted to the plurality of data output terminals during the next read cycle.

Abstract: In a data processor which comprises a semiconductor memory device, a potential on a bit line of the semiconductor memory device is monitored at the end of a precharge, required for the semiconductor memory device, to detect an anomalous frequency of a clock applied from the outside. The anomalous frequency is detected by determining whether or not the potential on the bit line has reached a predetermined potential. When the potential on the bit line has not reached a predetermined potential, the operation of a CPU is reset.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.