Abstract: A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes.

Abstract: A method is described that writes a first and a second data of a first data width into a memory that stores data at a second data width greater than the first data width. The method includes the step of selecting via a select circuit a plurality of memory cells that correspond to the second data width from a memory array of the memory. The first data is then written into a first number of the memory cells corresponding to the first data width while writing invalid data into a second number of the memory cells also corresponding to the first data width during a first write operation. The second data is then written into the second number of the memory cells while again writing the first data into the first number of the memory cells during a second write operation. A memory that can operate with either the first data width or the second data width without changing its column select circuit is also described.

Abstract: A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

Abstract: A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.

Abstract: A method of transferring data into or out of plural memory cells of a dynamic random access memory (DRAM) comprised of precharging bitlines of the DRAM for a predetermined interval, addressing a first group of wordlines for a first period of time, after the first period of time, addressing a second group of wordlines for a second period of time, the first and second periods of time being contained within the predetermined interval, addressing and sensing a first group of memory cells from the first group of wordlines for an interval within the first period of time, addressing a second group of memory cells from the second group of wordlines within the second period of time, and transferring sensed bits from the first group of memory cells to the second group of memory cells while the second group of memory cells is being addressed.

Abstract: A digital video memory circuit. The circuit includes a DRAM for storing thereto and reading data therefrom, a register group having registers for holding data to be written to and read from the DRAM, a selector having switching transistors connecting registers in the register group to an I/O data bus, respectively, for storing data on the I/O data bus to the DRAM and for transferring data from the DRAM to the I/O data bus. The register group includes a first register set and a second register set connected serially between the DRAM and the selector, the second register set transferring data on the I/O data bus to the first register set, and the first register set transferring data from the second register set to the DRAM. The second register set can receive data on the I/O data bus while the first register set writes previously received data to the DRAM.

Abstract: An integrated circuit multiport memory supports synchronous access through a serial port. In operation, a multiport memory of the present invention is coupled to a free running clock signal and a clock enable signal for internally synchronizing serial access. The external clock enable signal prevents incrementing the sequence of serial access when serial access is interrupted. In a synchronous memory of the present invention, the write data signal need not be held after the active edge of the serial clock, since serial data hold time is made independent of serial access memory write timing parameters. When serial data signals are conveyed on a bidirectional line of a asynchronous serial data port of the present invention, a direction control circuit of the present invention is responsive to transfer and write enable signals and independent of the conventional serial output enable signal.

Abstract: A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal.

Abstract: A contactless parallel data transfer device which is miniature, highly densed, and highly reliable having a coil block consisting of a first coil group installed in a portable memory and a coil block consisting of a second coil group installed in a data server for transferring access data in parallel between the portable memory (memory card, etc.) and the data server by contactless coupling, wherein the opposite coils of the first and second coil blocks are held close and opposite to each other on a contactless basis, and a parallel pulse group which is transferred in parallel between the both coil blocks is divided at least into a first parallel pulse group consisting of the first number of bits and a second parallel pulse group consisting of the second number of bits, and the parallel transfer timings of the both parallel pulse groups are different from each other, and an induced signal to the neighboring coils of each opposite coil pair of the first and second coil blocks is negated in the opposite phase.

Abstract: A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selector circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selector circuit; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.

Abstract: Disclosed is the FIFO buffer memory, comprising a core memory 12 having a dual port structure, for substantially storing data, first and second address decoders 13 and 14 responsive to read and write clock signals, for producing addresses indicative of directing locations in the core memory when data is written in the core memory or when the data is read from the core memory, and a status detector 15 for generating memory status signals indicating whether the data can be written in the FIFO buffer memory or whether the data can be read from the FIFO buffer memory, i.e. full and empty flags. The buffer memory can be embodied without use of complicated circuits such as address counter, address register and comparator, which can be operated at high speed and embodied with high-density integration.

Abstract: A distance measuring circuit includes an array of non-volatile analog storage cells arranged in rows and columns, input circuits to apply complementary analog voltages to pairs of row lines, and current measurement circuits connected to the column lines. Pairs of storage cells in a column are programmed to threshold voltages linearly related to a component of a stored vector and the negative of the component of the stored vector. During distance measurement, input voltages on a corresponding pair of the row lines are similarly linear related to a corresponding component of an input vector and the additive inverse of the component of the input vector. The storage cells are biased in the saturation regions so that the current through each storage cell is approximately proportional to the square of the difference between the voltage on the row line and the cell's threshold voltage, and currents on the column lines indicate the squared distance between user stored analog vectors and the input analog vector.

Abstract: A memory and a method involving the memory. The memory includes a memory array having a data quantity output for outputting a data quantity and a data output driver having an input for receiving the data quantity and an output for outputting the data quantity from the memory. The memory further includes a data quantity pipeline register having an input for receiving the data quantity and an output coupled to the input of the data output driver. Finally, the memory includes means for selectively coupling a data quantity from the data output of the memory array to the input of the data output driver in a first operational mode and to the input of the data quantity pipeline register in a second operational mode.

Abstract: A dual port random access memory capable of inputting/outputting data bit by bit includes a plurality of memory cell arrays (100a, 100b, 100c, 100d) accessible in parallel, a plurality of data registers (9a, 9b, 9c, 9d) arranged to be connected to memory arrays, and transfer gates (8a', 8b', 8c', 8d') for selectively connecting each of the data registers to one memory array in response to a destination designating signal. The transfer gate includes elements (T1, T2) for connecting the data registers and the memory arrays such that each of the plurality of memory arrays is connected to different data registers. Each of the data registers is capable of transferring data of one row of the memory array at one time. The data register is capable of serially inputting and outputting data. This structure enables rearrangement of data and transfer of data row by row between memory arrays in the memory device.

Abstract: A camera image data processor provides scan conversion at extremely high speed while allowing static and dynamic correction of image data particularly for a high data output rate CCD image transducer in a confocal imaging system for automated optical inspection in manufacturing processes. Scan conversion and data collation is accomplished at bit rates in excess of 1 Gigabyte by accessing a double buffer memory with different sequences of addresses covering a field of an image corresponding to a field in the memory during read and write operations. Highly parallel output is provided for confocal height data in a raster line by providing a delay equal to an integral multiple of the access time for a field for each confocally imaged height within a sample.

Abstract: y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

Abstract: A read/write memory for use with a central processing unit is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. In response to a control signal generated in the read/write memory, the capacitor is connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected.

Abstract: A configurable network interface controller provides a multi-chip FIFO extension protocol. Utilizing this protocol, FIFOs that are physically separated (e.g., in separate chips) can be made to operate as though they are a single FIFO.

Abstract: A serial/parallel converter has a function of forwarding data of remainder bits of p in number (e.g., 3) less than the serial/parallel number, which are positioned at the end of serial data, from the head from latches to p parallel output terminals via selectors. Accordingly, parallel data in which the data of remainder bit number are arranged correctly can be serially developed even though a simple delay amount is an arbitrary bit width. Thus, contemplated is a line memory of simple delay type which can set the simple delay amount to an arbitrary bit width, while performing serial/parallel conversion.

Abstract: A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.

Abstract: The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.

Abstract: A read-write semiconductor memory comprises a first data input buffer which takes in external data and which has a pair of signal output nodes for outputting a pair of signals corresponding to the taken-in data, a pair of signal lines connected to a pair of signal output nodes of the first data input buffer, and second data input buffers which are connected to the pair of signal lines and which have internal data set according to the signals on the pair of signal lines.

Abstract: A word oriented processing system includes a processing unit and a ferroelectric memory having a plurality of memory units organized in a matrix of rows and columns. Each memory unit stores a processor dataword of, for example, 8 or 16 bits, and contains a plurality of serial arrangements of, successively, a bitline connection, a first switching element, a ferroelectric capacitor and a node. The serial arrangements have the node in common. The node is connected to a plateline connection of the unit via second switching element. The processor reads or writes all bits of a word from one memory unit at a time. During reading or writing in one memory unit the first and second switching elements isolate the capacitors in other memory units from pulses on any of their plates.

Abstract: In order to permit the selection of aspect ratio for a given memory size, a semiconductor array utilizes switches to segment bit line columns, where each segment is associated with a specific set of memory locations and their respective data latches. After all of the data latches are loaded, the switches segment the bit line columns to allow simultaneous programming of those memory locations cells associated with each set of data latches. This sequence is repeated until all desired data storage cells are programmed.

Abstract: A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

Abstract: A parallel data transfer circuit wherein processing at a data transfer source circuit is simplified to reduce the time required for transfer and a data storage area of a data transfer destination circuit can be used effectively is disclosed. A plurality of data register sets for temporarily latching parallel data and a plurality of corresponding flag register sets are provided between a data transfer source circuit and a data transfer destination circuit. A register designation signal is outputted from the data transfer source circuit to designate a data register into which data should be written. Only when data should be written into the data register, a flag is placed into a corresponding flag register. Since the data transfer destination circuit fetches data only from those data registers corresponding to those flag registers in which a flag is held, parallel data can be received without forming a discontinuous empty portion in data storage area of the data transfer destination circuit.

Abstract: The dual port DRAM comprises a SAM section having a plurality of registers, for inputting and outputting data in series between a SAM input/output port and the outside in synchronism with a control signal; a RAM section having a plurality of memory cells, for inputting and outputting data at random between a RAM input/output port and the outside; a plurality of transfer gates connected between the SAM section and the RAM section, for transferring data in parallel; and a selecting section for selectively turning on or off only the transfer gates connected to the registers in the SAM section to which data are inputted from the SAM input/output port in series in synchronism with the control signal, to execute partial parallel-data transfer from the SAM section to the RAM section via the transfer gates.

Abstract: The present invention is a dynamic type semiconductor memory device comprising a plurality of memory cells (not shown), plural pairs of bit lines, a first sense amplifier (20), arranged for each of the plural pairs of bit lines, for amplifying a bit line signal. A pair of data input/output lines extracts data from a pair of bit lines. A second sense amplifier (22), is arranged for each of said plural pairs of bit lines and consists of first and second driver MOS transistors (52 in FIG. 3) gates of which are connected to the pair of bit lines. The second sense amplifier is activated when said first sense amplifier is activated, for amplifying signals of the pair of data input/output lines. First and second column selecting transistors (30 in FIG. 2) are inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line. A first write transistor (54 in FIG.

Abstract: There is a hardware implemented row copy operation mode for a DRAM to relieve the VRAMs from this slower repetitive operation. In addition, by providing circuitry that will generate a solid repetitive pattern for the full or portions of the screen. Another advantage of the invention occurs during testing of a DRAM with this circuitry. By having the ability of filling the memory array with, for example all digital ones in each cell, the quality of the die can easily be tested by modifying individual cells with a digital zero. Uniquely, this circuitry relieves the testing circuitry from filling in a background of information like the all ones background. Another feature of the invention allows graphic cards that exclusively use DRAMs, to eliminate the additional circuitry needed to perform the row copy feature, or creation of backgrounds.

Abstract: Non-volatile semiconductor memory integrated circuits which partition a main memory array into sub-arrays. Address lines of the main memory array are also partitioned into four groups. The first group and the second group are dedicated for the addressing of the sub-arrays. Each of the sub-arrays can be addressed by a simultaneous energization of a pair of address lines selected from the first and the second group. The third group and the fourth group are used for the addressing for individual memory cells in the sub-arrays. The simultaneous energization of a pair of address lines selected from the third and the fourth group can address any of the memory cells within a selected sub-array. The memory circuits of the present invention are applicable for memory cells with four terminals. In a first embodiment of the invention, the memory circuit is a one-bit wide circuit.

Abstract: In a nonvolatile semiconductor memory device formed by nonvolatile memory cells connected to word lines and bit lines, one of the word lines is selected and driven by row address decoders, and one of the bit lines is selected and driven by column address decoders. An address degenerating circuit formed by NAND circuits, OR circuits or the like is interposed at a prestage of the row address decoders or the column address decoders, thus enabling a parallel write and read function.

Abstract: A multiport memory having a plurality of serial output ports includes a semiconductor memory for storing data in a plurality of memory elements arrayed in rows and columns and coupled by respective row and column connecting lines. A first register stores data read in parallel from the semiconductor memory via the connecting lines of one of the rows and columns of the arrayed memory elements and serves to supply the data stored therein in serial form to a first one of the serial output ports. The first register is also operative to supply the data stored therein in parallel to a second register for storage therein. The second register is operative to supply the data stored therein to a second one of the serial output ports.

Abstract: A dual port memory is disclosed capable of serial data reading and writing between a memory array including a memory cell formed by one MOS transistor and one capacitor and a single data input/output line. A flipflop and a sense amplifier are provided corresponding to each memory cell column of the memory array. Each flipflop includes a first inverter having a large drive capability and a second inverter having a small drive capability, connected to the input end and the output end of each other. The input end of the first inverter is connected to the corresponding sense amplifier via a single MOS transistor. The output ends of the firs and second inverters are connected to the data input/output line via first and second MOS transistors, respectively. At the time of data reading from the memory array to the data input/output line, the single MOS transistor and the first MOS transistor conduct.

Abstract: A static RAM cell having first and second differentially connected lines reads binary information stored in the cell by providing a current through the cell and the first line to read a binary "1" or through the cell and the second line to read a binary "0". First and second transistors in a pre-amplifier respectively connected in the first and second lines provide outputs respectively representing a binary "1" and a binary "0". The first and second transistors pass control currents respectively through third and fourth transistors to produce bias currents in one of the first and second transistors when reading currents are not passing through that transistor and the cell. The control of the third and fourth transistors increases the frequency at which information is read from the cell and is amplified. In this improvement, the bias current in the line providing an output at each instant is reduced by respectively providing a negative feedback from the outputs (e.g.

Abstract: An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.

Abstract: The present invention is a circuit comprising: a plurality of memory cells (not shown); a plurality of first amplifiers (each first amplifier is preferably comprised of; a plurality of sense amplifiers (e.g. 20), a block amplifier (e.g. 22), and a second means, preferably a block-I/O pair (e.g. 24 and 26), to connect the plurality of sense amplifiers to the block amplifier), wherein each first amplifier is selectively connected, preferably by a bitline pair (not shown), to a portion of the plurality of memory cells; a second amplifier (e.g. 34 in FIG. 2) connected to the plurality of first amplifiers by a first means, preferably a local-I/O pair (e.g. 28 and 32); and a means of comparing data, preferably determining whether the data are comprised of the same data states on the first means, from the selectively connected portions of the plurality of memory cells with data from the remainder of the selectively connected portions of the plurality of memory cells.

Abstract: A semiconductor memory device having normal columns and redundant columns includes normal column decoders for designating the normal columns and redundant column decoders for designating the redundant columns so that the bits from the normal columns are combined with the bits from the redundant columns so as to provide an entire byte. The normal column decoders are to be operated simultaneously with the redundant column decoders.

Abstract: Communication of digital information between digital systems (2, 3) comprising clock generators (8, 9) is effected via storage in memory locations a1 to a8 and b1 to b8 of a cyclic buffer 4, in which, in succession, the information is written and read on a time base determined by the various clock generators (8, 9). Pointers stored in pointers (12, 13) determine the memory locations to be read out or written. If the pointers have become equal as a result of phase deviations of the clock generators (8, 9), this is detected by an address distance monitoring means (14) and made unequal and set to a maximum difference value relative to each other. The difference value amounts to half the number of memory locations n in a row of the buffer 4. For full duplex transmission the buffer 4 preferably comprises a double row of memory locations a1-an and b1-bn respectively.

Abstract: The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.

Abstract: Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column conductors of the array. Data to be stored is written in parallel to cells of the memory a column at a time at a rate determined by the write sequential pulse generator and is recovered a column at a time at a rate determined by the read sequential pulse generator. Advantageously, (1) the ratio of the read and write rates may be selected to provide time compression, time expansion or constant delay of video data; (2) additionally data may be written and read concurrently without bus contention and (3) addressing is simplified by a timed application of trigger pulses to the pulse generators whereby there is no need for application to the memory of binary addressing data.

Abstract: A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).

Abstract: The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

Abstract: A semiconductor memory includes an input buffer means for storing inputted data, an output buffer means for storing the data and for outputting the data and a storage means for storing the data outputted from the input buffer means and for transferring the data to the output buffer means. The input buffer means includes a plurality of memories having equal capacity. The output buffer means also includes a plurality of memories having equal capacity. The memory means have memory capacity of a divisor of memory capacity per line of the storage means. In addition, the semiconductor memory can also include a dividing means for dividing image data outputted from said input buffer into smaller data units to be written on said storage means and a recombining means for said smaller data units outputted from said storage means to supply to said output buffer means.

Abstract: An input/output circuit wherein a plurality of data lines are provided with a serial/parallel conversion means common to all, so that the circuit is enabled to consume less power and draw a reduced instantaneous current in its operation and be fabricated in an integrated circuit form.

Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value.

Abstract: The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in the system by controlling the routing of data between the memory units. Each one of the memory units includes a set of input multiplexers (100-103), a set of shift/shadow registers (110-113) and a memory component (120) having a RAM memory array (121). The components of the memory units are implemented on a single integrated circuit chip. The input multiplexers allow alternate data streams to be selected for input to the shift/shadow registers. The shift/shadow registers are operative for enabling data to be transferred to and from the memory array at speeds slower than the rate at which these data are received by the system.

Abstract: An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed. The stored analog value may be read out of the synapse by applying a voltage to a read line. An array of the readable synapses may be provided and used in conjunction with a dummy synapse to compensate for an error offset introduced by the operating characteristics of the synapses.

Abstract: In a memory system having a storage device and a key storage keeping key data controlling an access to the storage device, there is disposed a key address translation structure for obtaining an address of an entry of the key storage based on an address of the storage device to which an access request is issued. As a result, when subdividing the storage device according to the key data setting unit, each subdivided area can be assigned with a variable size and a plurality of sizes are enabled to be specified for the key data setting units at the same time.