Parallel Read/write Patents (Class 365/220)
  • Patent number: 4896302
    Abstract: In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output terminal of the driver circuit is connected directly with a data input/output portion for the first memory cell array and connected with another data input/output portion for the second memory cell array through wirings traversing the decoder circuit.
    Type: Grant
    Filed: November 22, 1988
    Date of Patent: January 23, 1990
    Assignee: Fujitsu Limited
    Inventors: Kimiaki Sato, Yoshihiro Takemae, Masao Nakano, Nobumi Kodama
  • Patent number: 4870621
    Abstract: A dual port memory which enables consecutive access operations from an arbitrary column address and is fabricated on a reduced area of a semiconductor chip. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array and having a column decoder, and a serial access peripheral circuit having a shift register for serially selecting the columns of the array and a control circuit for determining the state of the shift register in accordance with the output of the column register.
    Type: Grant
    Filed: November 27, 1987
    Date of Patent: September 26, 1989
    Assignee: NEC Corporation
    Inventor: Kazuhiro Nakada
  • Patent number: 4819213
    Abstract: A semiconductor memory for serially reading data of memory cells connected to the selected one word line based on the clock signal which defines a picture element and for writing the write data serially input to the latch circuit based on such clock signal to the memory cells, during the horizontal blanking time of a CRT monitor.
    Type: Grant
    Filed: December 11, 1986
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yasunori Yamaguchi, Masamichi Ishihara
  • Patent number: 4773045
    Abstract: A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion.
    Type: Grant
    Filed: October 16, 1985
    Date of Patent: September 20, 1988
    Assignee: Fujitsu Limited
    Inventor: Junji Ogawa
  • Patent number: 4771404
    Abstract: A memory device which employs multilevel memory cells has a basic arrangement in which a write device writes multilevel information corresponding to binary data of plural bits in the memory cells and a readout device outputs binary data of plural bits representing the multilevel information read out of the memory cells. The memory device includes a multilevel detector for detecting the information of the memory cells at one time and reference level generator for generating reference levels therefor, thereby permitting the reduction of the bit area of each memory cell and increased speed during the operation of the memory device.
    Type: Grant
    Filed: August 28, 1985
    Date of Patent: September 13, 1988
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tsuneo Mano, Junzo Yamada, Nobutaro Shibata
  • Patent number: 4725987
    Abstract: A fast frame store incorporating a memory array having selectable memory banks which include a plurality of relatively slow dynamic RAMs (DRAMs) is disclosed. The frame store has a buffered input and a buffered output to slow the data rate. Data can be read in parallel into a selected memory bank while at the same time other data are being read in parallel out of another selected memory bank. Refresh of DRAMs of an unselected bank occurs simultaneously with the transfer of data to or from the frame store. Several memory banks of the frame store are connected to a single row address select (RAS) line, so that when a selected bank is being addressed for data transfer, the memory location of several other unselected banks are being refreshed.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: February 16, 1988
    Assignee: Eastman Kodak Company
    Inventor: Billy E. Cates
  • Patent number: 4710966
    Abstract: A plurality of digital words representing picture elements are sequentially loaded into a readin register, which words are thereafter written in parallel into a random access memory via a write data register. The words are subsequently readout of the random access memory in parallel into a read data register and to a readout data register which thereafter sequentially transmits the words stored therein to an output circuit. The arrangement is such that each word may flow through the pipeline to be processed during a clock period of P ns; although the RAM response time is greater than P ns.
    Type: Grant
    Filed: November 12, 1986
    Date of Patent: December 1, 1987
    Assignee: Itek Corporation
    Inventor: James M. Aufiero
  • Patent number: 4701884
    Abstract: A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided.
    Type: Grant
    Filed: August 14, 1986
    Date of Patent: October 20, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Aoki, Masashi Horiguchi, Yoshinobu Nakagome, Shinichi Ikenaga, Katsuhiro Shimohigashi, Toshiaki Masuhara, Kiyoo Itoh, Hideo Nakamura, Osamu Minato
  • Patent number: 4633440
    Abstract: A hierarchical memory system in which a lower level transfers data serially to an upper level and in parallel to a yet lower level. The lower level includes a two-port memory chip having a wide buffer for parallel accesses to the memory array, to the yet lower level, and to a serial buffer. The serial buffer is serially accessed to the upper level simultaneously with accesses to the wide buffer.
    Type: Grant
    Filed: December 31, 1984
    Date of Patent: December 30, 1986
    Assignee: International Business Machines
    Inventor: Francis J. Pakulski
  • Patent number: 4633441
    Abstract: Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting state of the counter at an optional value, a selection circuit for consecutively selecting the array in response to the output of the counter, and a control circuit for advancing the state of the counter in response to a shift pulse.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: December 30, 1986
    Assignee: NEC
    Inventor: Shoji Ishimoto
  • Patent number: 4597061
    Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.
    Type: Grant
    Filed: January 3, 1983
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: James H. Cline, David M. Chastain
  • Patent number: 4590465
    Abstract: The present invention provides a relatively inexpensive raster-scan type graphics system capable of real time operation, utilizing logic-enhanced pixels within an image buffer, permitting parallel (simultaneous) calculations at every pixel. A typical implementation would be as custom VLSI chips. In the sequence of most general applications, each polygon is operated upon in sequence, and the image is built up as the polygons are processed without the necessity of sorting. With respect to each successive polygon, the following operations are effected: (1) all pixels within the polygon are identified; (2) the respective pixels which would be visible to the observer, that is, not obstructed by some previously processed polygon, are determined; and (3) the proper color intensities for each visible pixel are determined.
    Type: Grant
    Filed: February 18, 1982
    Date of Patent: May 20, 1986
    Inventor: Henry Fuchs
  • Patent number: 4493055
    Abstract: A wafer-scale integrated circuit wherein a plurality of memory cells on a wafer are connectable from a port to form a chain memory looping away from and back to the port by means of a serial connection of forward moving data registers and a serial connection of backward moving data registers between cells, has a reduced risk of any individual, otherwise functional cell being non-functional as a result of a failure elsewhere on the wafer of an associated global signal line by achieving a reduction in the numbers of global lines by providing the clock signal for controlling the shifting of data in the registers between the cells in parallel with the data, the inter-cell clock operating a multiple clock pulse generator in each cell.
    Type: Grant
    Filed: December 14, 1981
    Date of Patent: January 8, 1985
    Assignee: Burroughs Corporation
    Inventor: Ismet M. F. M. Osman
  • Patent number: 4410964
    Abstract: A memory device is constructed having a plurality of output ports, each output port being one word wide, such that a plurality of words may be accessed from the memory simultaneously.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: October 18, 1983
    Inventors: Karl I. Nordling, Scott Nance
  • Patent number: 4150364
    Abstract: Memory system having contiguous storage locations with sequential addresses is partitioned into units to permit separate unit write-in and parallel unit read-out, operations. Each unit is responsive to common word address signals and unique combinations of block address signals. In response to a control signal in a first of two possible states, the memory system operates in a conventional manner, i.e., data is read from or written to a particular location in the memory to or from a data bus, the address of the particular location being supplied over an address bus and having a block select portion and a word select portion. When the control signal is in its second state, each unit is responsive only to the word address signals to read data from or write data to common word locations in each unit simultaneously.
    Type: Grant
    Filed: June 29, 1977
    Date of Patent: April 17, 1979
    Assignee: RCA Corporation
    Inventor: Philip K. Baltzer
  • Patent number: 4139787
    Abstract: A decoupling apparatus for a charge-coupled device line-addressable random-access memory includes a series of bipolar transistors, the bases of which are connected to output lines from the CCD LARAM. The emitters of the bipolar transistors, connected together, are connected to the source of a depletion-mode MOS reset transistor and to a comparator circuit.
    Type: Grant
    Filed: October 11, 1977
    Date of Patent: February 13, 1979
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Gilbert F. Amelio