Abstract: A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.

Abstract: A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A method of refreshing a memory device includes counting the number of accesses to each of a plurality of memory blocks, comparing the counted numbers of accesses resulting from the counting with a first reference count, and performing an additional refresh operation on a corresponding memory block according to a comparison result.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.

Abstract: A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device and a second memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk.

Abstract: In a nonvolatile memory array, power is provided to groups of memory dies by power management circuits that have different power modes. While one power management circuit is in a high-power mode supplying power for power-hungry memory operations, another power management circuit is in a low-power mode so that overall power usage is balanced.

Abstract: A computer system maintains a threshold value, wherein the threshold value indicates a period of time. The computer system determines that a processor is in any one of a plurality of low power consumption states. Responsive to a determination that the processor is in any one of the plurality of low power consumption states, the computer system increments a counter. The counter indicates the period of time the processor has been in any one of the plurality of low power consumption state. The computing system determines that the counter value is equal to or greater than the threshold value. Responsive to a determination that the counter value is equal to or greater than the threshold value, the computer system sends a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate.

Abstract: An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M?1) word lines of the L remained sectors respectively in the other (M?1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed.

Abstract: A memory device is transitioned to a low-power mode in which an active-mode resource required to receive memory access commands from a memory controller at a first command-signaling frequency of the memory device is disabled. A first memory access command, transmitted by the memory controller, is received within the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.

Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

Abstract: A method of performing a refresh operation of a memory device including a plurality of memory cells connected to a plurality of word lines. The method includes performing a table-based refresh operation on at least a first word line of the plurality of word lines in a first time period of a refresh cycle, and performing a detector-based refresh operation on at least a second word line of the plurality of word lines in a second time period of the refresh cycle. The first word line includes at least one memory cell predetermined to be a weak cell. The second word line includes at least one memory cell dynamically determined to be a weak cell.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change between refresh operations of the memory device. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract: A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

Abstract: Systems and methods are disclosed for correction block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.

Abstract: An integrated circuit memory interface device coupled to a dynamic random access memory device is provided. The device includes an address match table. The address match table includes a plurality of first addresses. Each of the first addresses is associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device. The device has a plurality of second addresses. Each of the second addresses is associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range.

Abstract: Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

Abstract: A method for operating a semiconductor memory device including a memory block constituted by first memory cells used as main memory cells and second memory cells includes reading out an erase count of the memory block stored in the second memory cells, erasing the memory block, increasing the read-out erase count, and storing the increased erase count in the second memory cells.

Abstract: Provided is a device and method for controlling self-refresh which reduces current when a semiconductor device stays in a self-refresh operation. The device for controlling self-refresh includes a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage, a bulk voltage driver configured to vary a level of the bulk voltage in response to the control signal, and output the bulk voltage with a different level, and a refresh controller configured to output the self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage.

Abstract: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A system for bi-directional data content transfer between a plurality of mobile platforms, such as aircraft or cruise ships, and a ground-based control segment. The system includes the ground-based control segment, a space segment and a mobile system disposed on each mobile platform. The ground-based control segment includes an antenna which is used to transmit encoded RF signals representative of data content to the space segment. The space segment includes a plurality of satellite transponders, with one of the transponders being designated by the ground-based control segment to transpond the encoded RF signals to the mobile system. The mobile system includes steerable receive and transmit antennas. The receive antenna receives the encoded RF signals from the satellite transponder, which are thereafter decoded, demodulated, D/A converted by a communications subsystem and transmitted to a server. The server filters off that data content not requested by any occupants on the mobile system.

Abstract: A buffer memory is provided that comprises a plurality of memory elements for storing data elements in an order of arrival, wherein the plurality of memory elements have a variable size and wherein each memory element comprises a pointer (such as a next block starting index) to a memory element storing a next data element. Additionally, each memory element optionally further comprises a block size field indicating the variable size and/or a sequence number field indicating a sequence number of the corresponding data element. The buffer memory optionally comprises a largest sequence variable to store a sequence number of a data element in the buffer memory having a largest sequence number. The largest sequence variable is updated if a newly arrived data element has a sequence number that is larger than the largest sequence variable. A method is also provided for managing the disclosed buffer memories.

Abstract: According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters.

Abstract: Methods, computer-readable mediums and systems for reducing transistor recovery are disclosed. Data which toggles at least one bit may be periodically communicated over a data path, where toggling of at least one bit may effectively reset the recovery period for any transistors in the data path associated with the at least one bit. Timing uncertainty associated with a given transistor may be reduced by limiting the amount of recovery experienced by the transistor. Accordingly, recovery of transistors in a data path may be limited to predetermined amount by toggling bits of the data path at a predetermined frequency, thereby reducing timing uncertainty and allowing a smaller system margin and/or higher data transmission speeds.

Abstract: Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.

Abstract: A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals.

Abstract: An embodiment provides a method, including: determining current validity timing of a non-volatile memory device having changing validity timing via: writing information to a non-volatile memory device; waiting a time after the writing; and reading the information written to the non-volatile memory device following the time. Other aspects are described and claimed.

Abstract: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2N cells for both normal and self refresh operation modes.

Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract: A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a clock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.

Abstract: A variable resistance memory device includes a plurality of cell blocks each of which includes a plurality of first lines extending in parallel to each other along a first direction, a plurality of second lines extending in parallel to each other along a second direction crossing the first direction, and a plurality of memory cells including variable resistance layers arranged at intersections of the plurality of first lines and the plurality of second lines and a plurality of selection units coupled to the plurality of first lines and coupling two neighboring cell blocks.

Abstract: A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value.

Abstract: A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

Abstract: A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. The semiconductor device generates the temperature code signals according to a level combination of the offset signals. Further, the semiconductor device controls a refresh cycle time determined by the level combination of the offset signals.

Abstract: A power supply and monitoring apparatus such as in a non-volatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions.