Abstract: A refresh control device and a semiconductor device including the same, for preventing a row hammer failure from occurring, may include an enable signal generator configured to generate an enable signal for performing a smart refresh operation and a plurality of active controllers configured to generate a plurality of refresh signals for refreshing word lines located at different positions within one bank, based on receiving the enable signal.

Abstract: A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

Abstract: Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.

Abstract: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.

Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a USB (Universal Serial Bus) device. The method also includes detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint. The method also includes entering a low power mode state, in response to the detecting, where the USB device includes a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and a clock tree block located outside of the USB clock domain. The entering the low power mode state includes disabling the clock tree block, and clocking the USB clock domain using the IRC and clock recovery logic.

Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling at least two types of refresh operations according to an external refresh signal; and a 2nd controller suitable for controlling the at least two types of refresh operations to be evenly and alternately performed on a plurality of word lines according to the refresh control signals, a predetermined number of times during a unit refresh period corresponding to the external refresh signal.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals and a plurality of data. The second semiconductor device generates a first mode signal and a second mode signal according to a combination of the command/address signals. The second semiconductor device is suitable for inverting the plurality of data inputted through a pad in response to the first or the second mode signal to store the inverted data suitable for blocking input of the inverted data in response to the second mode signal if a number of bits having a predetermined level in the plurality of data is equal to or greater than a predetermined number.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command and external addresses. The second semiconductor device generates an internal active command in response to the external command, generates active addresses in response to the external addresses, generates a refresh signal and refresh addresses in response to the internal active command, performs an internal operation in response to the internal active command and the active addresses, and performs a refresh operation in response to the refresh signal and the refresh addresses.

Abstract: A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.

Abstract: Systems, methods, and other embodiments associated with conserving power using variable width pulses to activate word lines are described. In one embodiment, a memory device embedded within a processor. The memory device includes a pulse shaper to generate a first timing delay and a second timing delay according to power state information. The power state information indicates a current operating state of the processor. The memory device includes a memory controller to generate, in response to receiving a request to access one or more memory cells of the memory device, a word line enable signal that activates the one or more memory cells according to the first timing delay, the second timing delay, and a clock signal by generating the word line enable signal with a pulse width that is variable to conserve power when the state information indicates the processor is in a power saving state.

Abstract: An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality of counter cells configured to count through count values between a minimum count value to a maximum count value, wherein an output of each of the plurality of counter cells each corresponds to an address bit of the refresh address, and a reset circuit coupled to a counter cell of the plurality of counter cells, wherein the reset circuit is configured to reset the counter cell of the plurality of counter cells to an initial value responsive to the plurality of counter cells changing from a first count value to a second count value to skip at least some of the count values to provide the refresh addresses, wherein the first and second count values are less than the maximum count value.

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

Abstract: At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.

Abstract: A trace to be coupled to an input of a receiver, the trace including: a plurality of first portions; and a plurality of second portions alternately coupled in series with the first portions, the second portions having a width that is different from that of the first portions.

Abstract: A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a second block control signal in response to a refresh pulse signal, a second refresh control block for generating a first refresh control pulse signal and a second refresh control pulse signal corresponding to a first refresh operation section of the first memory block and a second refresh operation section of the second memory block, respectively, in response to the refresh pulse signal and the first and second block control signals, and a third refresh control block for controlling the first and second memory blocks so that a first refresh operation of the first memory block and a second refresh operation of the second memory block are discontinuously performed in response to the first and second refresh control pulse signals.

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.

Abstract: A solid state drive in accordance with embodiments of the present inventive concepts may include a nonvolatile memory, a volatile memory, a memory controller controlling the nonvolatile memory and the volatile memory, and a power generator providing power to the nonvolatile memory, the volatile memory, and the memory controller. A method of operating the solid state drive may include designating a bank that will perform a self refresh among a plurality of banks included in the volatile memory in response to a power saving mode signal. Information of the designated bank may be stored in a register in response to a command and an address signal; and a self refresh of the designated bank may be performed on the basis of the information stored in the register.

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array.

Abstract: According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

Abstract: A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract: A semiconductor storage device according to an embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are connected to the memory cells. A plurality of bit lines are connected to one end of current paths of the memory cells. A sense amplifier part repeats a detection operation plural times when detecting data of memory cells connected to a word line WLn (n is an integer) among the word lines. A controller selects one of a plurality of detection results obtained by the detection operations, based on data of memory cells connected to a word line WLn?1 and data of memory cells connected to a word line WLn+1.

Abstract: A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals.

Abstract: A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval.

Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.

Abstract: A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Abstract: A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. The boot-up period signal may be enabled during the boot-up operation period. The semiconductor device may include a sensing circuit configured for sensing the boot-up period signal and a clock enablement signal to generate a first detection signal and a second detection signal. The semiconductor device may include an initialization circuit configured for executing an initialization operation in response to the first and second detection signals. Related semiconductor systems may also be provided.

Abstract: A control circuit may include a refresh time control circuit configured for controlling a refresh time on the basis of an area setting signal for setting a usage area of a memory. The control circuit may include an address control circuit configured for fixing at least one bit included in an external address on the basis of the area setting signal and an area mode signal and provide an internal address.

Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

Abstract: An image forming apparatus includes a volatile memory and System-on-Chip (SoC) part. The SoC part includes an internal memory, a CPU for accessing the volatile memory in the normal mode; an interface part for receiving a external signal, and a control part for, when the interface part has no input during a first preset time, copying information stored to the volatile memory to the internal memory and converting to a first power saving mode to lower an operating frequency of the volatile memory and an operating frequency of the CPU, and when a normal mode switch signal is not input during a second preset time in the first power saving mode, controlling the CPU to access the information copied to the internal memory and converting to a second power saving mode to change the volatile memory to a self-refresh mode.

Abstract: A memory device includes a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells, and a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines.

Abstract: A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.

Abstract: Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.

Abstract: A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.

Abstract: According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function. The reconfigurable look-up table may include a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The reconfigurable look-up table may be configured to perform one logic function at a time, and wherein the logic function is dynamically selected. The plurality of look up tables stored in the memory cells may be configured to be dynamically altered via a write operation to the random access memory array.

Abstract: In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.