Abstract: A refresh apparatus includes a flash memory and a refreshing unit. The flash memory includes a plurality of blocks, the plurality of blocks storing data. The refreshing unit sequentially refreshes the plurality of blocks in units of blocks. The refreshing unit includes a reading unit, a data deleting unit, and a data writing unit. The reading unit performs batch reading of data from the plurality of blocks. The data deleting unit deletes data stored in a target block for the refresh during the refresh in units of blocks. The data writing unit writes data corresponding to the deleted data among the plurality of read data to the target block so as to complete the refresh in units of blocks.

Abstract: A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.

Abstract: A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.

Abstract: A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.

Abstract: A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification.

Abstract: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

Abstract: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Abstract: A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device.

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.

Abstract: To measure an inner temperature of a chamber included in a test handler, self-refresh currents of semiconductor memory devices under test are measured. The semiconductor memory devices are disposed in the chamber and have a function of linear temperature compensated self-refresh (Li-TCSR). Local temperature values are generated based on the self-refresh currents, where each local temperature value indicates a temperature near the corresponding semiconductor memory device of the semiconductor memory devices under test.

Abstract: A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

Abstract: According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.

Abstract: The semiconductor device includes a pre-internal refresh signal generator and an internal refresh signal generator. The pre-internal refresh signal generator receives a first periodic signal during a refresh operation to generate a pre-internal refresh signal including pulses which are periodically created. The internal refresh signal generator receives a second periodic signal during the refresh operation to generate first and second internal refresh signals sequentially enabled by the pulses of the pre-internal refresh signal.

Abstract: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage.

Abstract: A memory connection structure of a storage device is disclosed. The storage device includes a circuit board, a memory controller, a bus, and a memory module. The memory controller, the bus, and the memory module are electrically connected on the circuit board. The memory module is composed of a plurality of memory sockets and a plurality of volatile memories. The volatile memories are connected to the same bus via the corresponding memory sockets and connected to the memory controller via the bus. The bus has at least one connection point and each connection point is connected to two memory sockets. The circuit board has a front surface and a rear surface, and two memory sockets connected to the same connection point are correspondingly installed on each of the two surfaces of the circuit board. In addition, two distances between the each memory socket and the memory controller are identical.

Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

Abstract: A display device for displaying a standby screen in a standby mode (SM), and a method for driving the same are disclosed. The display device includes: a display panel including pixels, and gate lines (GLs), data lines (DLs), and a common line (CL) connected to the pixels, a gate switching unit connecting the GLs due to an external SM signal, a data driver (DD): converting input data signals into analog signals due to a display mode signal, and supplying the analog signals to the DLs, a data switching unit: grouping the DLs due to the SM signal, and connecting DLs of the same group, and a SM driving unit: driving the GLs due to the SM signal, and driving the DLs of at least one group and the CL to generate a potential difference therebetween. When the SM signal is supplied to the DD, operation of the DD is stopped.

Abstract: A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.

Abstract: A method for manufacturing a dynamic random access memory device is provided. The method includes fabricating a dynamic random access memory device having a plurality of memory cells. Each of the memory cells has a refresh characteristic that meets or exceeds a refresh specification provided for a DDR3 SDRAM device or a DDR4 SDRAM device. The method includes testing the dynamic random access memory device. The testing includes determining the refresh characteristic for each of the memory cells, classifying each of the memory cells as a good memory cell or a bad memory cell based upon the refresh characteristic, identifying each of the bad memory cells, and storing an address location for each of the bad memory cells. The method then includes transferring the address location for each of the bad memory cells into an address match table.

Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.

Abstract: A method for operating a dynamic random access memory device includes providing a clock signal to a clock terminal of the dynamic random access memory device, selecting one of a first operating mode and a second operating mode of the dynamic random access memory device, the first operating mode, when selected, corresponding to the DRAM periodically refreshing a first number of word lines, and the second operating mode, when selected, corresponding to the DRAM periodically refreshing a second number of word lines different from the first number, and providing a self-refresh command to a command terminal of the dynamic random access memory device.

Abstract: Disclosed herein are an active control device, a semiconductor device and system including the same. The active control device may include a refresh control unit configured for outputting a refresh signal by controlling a delay time for a refresh start time when a refresh operation is performed and a precharge signal generation unit configured for generating a bank precharge signal for precharging a bank in response to the refresh signal. The refresh control unit may include a refresh delay unit for delaying a bank-active signal for a specific time and outputting a delay signal, and the refresh delay unit may be operably coupled with a plurality of banks in common.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.

Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.

Abstract: Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. Voltage sensing circuitry senses a voltage level of the memory array and outputs a power status signal. The power status signal is used to determine when the memory array is awake and can be accessed.

Abstract: A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

Abstract: A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. The plurality of chips may respectively receive refresh period signals allocated to them according to chip ID signals, and may perform the refresh operations.

Abstract: A semiconductor device including an operation initiation block suitable for sequentially generating a plurality of operation initiation signals at a predetermined time interval in response to an operation initiation source signal, a clock-based signal generation block suitable for generating an operation termination source signal in response to one of the multiple operation initiation signals and a clock, an operation termination block suitable for sequentially generating a plurality of operation termination signals at the predetermined time interval in response to the operation termination source signal, and an operation control block suitable for sequentially generating a plurality of first operation control signals in response to the multiple operation initiation signals and the multiple operation termination signals.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: A memory controlling device and method are disclosed for controlling a memory having a partial array self refresh (PASR) function and a plurality of memory segments. The memory controlling device comprises an address mapper, an address decoder, an address selector, and a PASR configuration register storing a PASR configuration. The address mapper converts an input address set into a mapped address set according to an address offset. The mapped address set comprises a plurality of consecutive mapped addresses or at least one mapped address within a limited range. The address decoder updates the PASR configuration during writing. The address selector generates an updated address set, which is used for setting at least one mode register of the memory, according to the PASR configuration register under a sleep-or-standby mode in order that the memory can self refresh at least one of the memory segments correspondingly.

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract: A semiconductor memory device includes an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit.

Abstract: A method for storing a data value in a memory cell is provided. The data value includes one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges. The method includes, within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period. The write cycle is shorter than a sum of the first write period and the second verify period.

Abstract: Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate.

Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.

Abstract: A semiconductor memory device includes a cell array including a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.

Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.

Abstract: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.

Abstract: A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.

Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.

Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory. Execution of refresh copy commands may be prioritized over other commands based on a remaining length of time. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.

Abstract: Apparatus and associated methods may relate to Magneto-Resistive Sensing Devices (MRSDs). In accordance with an exemplary embodiment, an MRSD comprises an underlying semiconductor device and a magneto-resistive sensor. In some exemplary embodiments, the semiconductor device is processed through most of a standard process flow. After the standard process flow, in various embodiments, a planarization step may be performed to create a more planar top surface. In some embodiments, the magneto-resistive material, which may be made from a Nickel-Iron alloy, called Permalloy, is deposited on the planar surface. A layer of interconnect metallization also may reside in this top region. The magneto-resistive material may contact the topmost layer of metallization of the semiconductor device via contact openings in the planarized surface. In some embodiments, the magneto-resistive material may similarly contact the topmost layer of metallization through these contact openings.

Abstract: Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode.

Abstract: A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.

Abstract: A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A method of refreshing a memory device includes counting the number of accesses to each of a plurality of memory blocks, comparing the counted numbers of accesses resulting from the counting with a first reference count, and performing an additional refresh operation on a corresponding memory block according to a comparison result.