Abstract: A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.

Abstract: A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for performing an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge, and a refresh control section suitable for controlling refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat.

Abstract: A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an address output control unit suitable for generating a plurality of output control signals in response to a single bank refresh pulse signal; an address latch unit suitable for outputting a target row address of a bank corresponding to an activated output control signal; and an address output unit suitable for outputting a row address adjacent to the target row address to a selected bank.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.

Abstract: A clock channel to couple a transmitter to a plurality of receivers, the clock channel including: a transmission line to be coupled to an input of at least one receiver from among a plurality of receivers, the transmission line including: a reflection portion to reflect a clock signal propagating through the clock channel according to a clock frequency.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: According to various embodiments, a memory arrangement is described having a first bit line, a first precharge device for precharging the first bit line to a precharged state, a second bit line, a second precharge device for precharging the second bit line to a precharged state, a memory control apparatus that is set up to interrupt the precharging of the first bit line by the first precharge device for memory access and to interrupt the precharging of the second bit line by the second precharge device for the memory access, a memory access apparatus that is set up to follow the interruption of the precharging of the first bit line and the interruption of the precharging of the second bit line by performing the memory access and reading the state of the second bit line, and a detector that is set up to take the state of the second bit line as a basis for detecting an attack on the memory arrangement.

Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

Abstract: A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.

Abstract: Semiconductor systems are provided. A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a command and a power supply voltage. The second semiconductor device may generate pulses of a reset signal for an initialization operation and pulses of an auto-refresh signal for an auto-refresh operation in response to a first reset command generated in response to the command after the power supply voltage reaches a target voltage level. The second semiconductor device may generate the pulses of the reset signal in response to a second reset command generated in response to the command.

Abstract: A semiconductor memory device includes: a command generator suitable for generating an internal active command signal corresponding to an active command signal, wherein, when an active section of the active command signal lasts for a predetermined time or longer, the internal active command signal is additionally activated; an address storage suitable for storing an address signal based on an activation number of the internal active command signal; and a refresh operation driver suitable for performing a refresh operation on a word line corresponding to the stored address signal.

Abstract: A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.

Abstract: Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract: In the original reading apparatus configured to store the image data in the image storing unit such as temporary storage memory, time required to complete the overwriting for erasure is reduced. The image data read by the image reading unit is stored in the image data storing unit and the stored image data is output. To hold data stored in the image data storing unit, refresh processing, which is to perform processing intermittently required to hold the data stored in the image data storing unit, is performed at a predetermined execution frequency. After the image data is output, frequency to execute the refresh processing is reduced as compared to a predetermined execution frequency to perform writing of the dummy data.

Abstract: A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

Abstract: A memory includes a first cell block comprising a plurality of first word lines and one or more first redundancy word lines for replacing at least one of the plurality of first word lines; a second cell block comprising a plurality of second word lines and one or more second redundancy word lines for replacing at least one of the plurality of second word lines; and a control unit suitable for sequentially receiving one or more input addresses, during a target refresh section, selecting one of the first cell block and the second cell block and a word line included in the selected cell block in response to a first input address, and activating one or more adjacent word lines adjacent to the selected word line, which is selected based on the first input address, when the selected word line is adjacent to the redundancy word line, wherein the adjacent word lines comprise the redundancy word line.

Abstract: For non-volatile random access memory (NVRAM) power management using self-refresh commands, a low-power module intercepts a memory self-refresh command and powers down an NVRAM in response to the memory self-refresh command. A resumption module intercepts a self-refresh exit command and powers up the NVRAM in response to the self-refresh exit command.

Abstract: The present invention relates to a semiconductor device, including memory blocks suitable for storing data, peripheral circuits suitable for refreshing the memory blocks, and a control circuit suitable for controlling the peripheral circuits to change data stored in a first memory block among the memory blocks and refresh the first memory block with changed data, and an operating method thereof.

Abstract: A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).

Abstract: A refresh method of a volatile memory includes at least the following steps: detecting at least one parameter of the volatile memory; selecting a target refresh type from a plurality of candidate refresh types according to the at least one parameter; and performing a refresh operation upon the volatile memory according to the target refresh type. In one embodiment, the candidate refresh types include at least a first candidate refresh type and a second candidate refresh type, each refresh command complying with the first candidate refresh type is arranged to refresh a first number of banks of the volatile memory, and each refresh command complying with the second candidate refresh type is arranged to refresh a second number of banks of the volatile memory.

Abstract: A method of performing refresh operations on a storage device includes identifying word lines coupled to weak storage elements. The method also includes grouping a plurality of word lines having distinct bank offsets onto a single refresh address. Each of the plurality of word lines is coupled to a corresponding weak storage element. The method further includes performing a refresh of the single refresh address.

Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Abstract: A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals.

Abstract: Various techniques for reducing power consumption of a computing device are described herein. In one example, a method includes detecting that the computing device is to execute a first operation for a first hardware component. The method can also include determining that the computing device is not to execute a second operation for a second hardware component during a period of time. Furthermore, the method can include loading operation data corresponding to the first operation into a processor cache from a non-volatile storage device and detecting that the first operation is not to request memory data from a volatile storage device. The method can also include removing power from at least one storage device.

Abstract: Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency measurements utilize a reference clock. Some measurements count periods of the oscillator signal independently of the reference clock, and some measurements count periods of the reference clock independently of the oscillator signal. After one oscillator on the device has been trimmed, that trimmed oscillator may then be used to make oscillation frequency measurements for trimming another oscillator on the device.

Abstract: The semiconductor memory device includes a power control signal generator and a sense amplifier circuit. The power control signal generator generates a first power control signal that is enabled in response to a temperature latch signal generated in response to latching a temperature signal in a predetermined mode. The sense amplifier circuit generates a first power signal having a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit senses and amplifies a voltage level of a bit line using the first power signal as a power supply voltage.

Abstract: Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.

Abstract: Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT?PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate.

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract: A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal, and a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

Abstract: A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.

Abstract: Apparatuses and methods of providing word line voltages include an example apparatus including a voltage driver and a word line driver. The voltage driver is configured to provide a word line voltage, wherein the word line voltage is a pumped supply voltage responsive to an active mode and the word line voltage is a non-zero voltage less than the pumped supply voltage during a standby mode. The word line driver is coupled to the voltage driver and is configured to drive a respective word line to the word line voltage during the active and standby modes.

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed.

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.