Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.

Abstract: The present invention provides an on-line method for stabilizing surface compressive stress of chemically-tempered glass, which comprises the steps of: placing glass to be tempered together with a stabilizer in a tempering furnace containing a molten salt bath for glass tempering; and after reacting at a temperature for a period of time, removing the glass and the stabilizer from the tempering furnace. The stabilizer is capable of chemically reacting with impurity ions in the molten salt bath for glass tempering, to remove the impurity ions in the molten salt bath. Therefore, the presence of the stabilizer allows the impurity ion content in the molten salt bath for glass tempering to be stable without gradual accumulation.

Abstract: A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.

Abstract: A memory device and a data refreshing method of the memory device are provided. The memory device includes a memory array and a memory control circuit. The memory control circuit counts the number of access commands to generate a first count value and counts the number of refreshing commands to generate a second count value. If the first count value is equal to the second count value, the memory control circuit latches a memory bank address and a memory row address corresponding to the access commands to obtain a row hammer refreshing bank address and a row hammer refreshing row address. The memory control circuit performs a row hammer refreshing operation on a memory bank according to the row hammer refreshing bank address and the row hammer refreshing row address.

Abstract: An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.

Abstract: A method for managing a plurality of data blocks of a data storage device includes steps of: reading a plurality of data pages in the data blocks which having valid data; updating a plurality of access counts of the data pages in the data blocks; determining whether an access count of the data block is greater than or equal to an access count threshold, wherein the access count of the data block is selected from one of the access counts of the data pages therein; and when the determination is positive, storing data in the data block into a spare data block of the data blocks. The access count threshold is updated when an erase count of the data block is determined to be greater than or equal to an erase count threshold. A method of data management for a data storage device is also provided.

Abstract: The following description is directed to dynamically adjusting a refresh rate. In one example, a method can include determining a rate of memory errors, and dynamically adjusting a refresh rate of a memory based at least partially on the determined rate of memory errors.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.

Abstract: Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

Abstract: A control device includes: a memory controller configured to output a control signal to a nonvolatile memory in response to a write request from a processor; a voltage monitoring portion configured to monitor an input voltage supplied from an input power supply; a mask signal generating portion configured to generate and output a mask signal when the voltage monitoring portion determines that the input voltage has decreased; and a masking portion configured to apply, when receiving the mask signal outputted from the mask signal generating portion, a masking processing to the control signal outputted from the memory controller to the nonvolatile memory. When the voltage monitoring portion determines that the input voltage has decreased, and the data is being written to the nonvolatile memory, then the mask signal generating portion outputs the mask signal after the completion of the data writing.

Abstract: In accordance with one or more embodiments, a system can include a plurality of twisted insulated conductors, and a communication device coupled to a first conductive endpoint of each insulated conductor of the plurality of twisted insulated conductors. The communication device can facilitate generating transmission signals at each first conductive endpoint of each insulated conductor of the plurality of twisted insulated conductors. The transmission signals in turn can induce electromagnetic waves that propagate along interstitial areas between the plurality of twisted insulated conductors. Other embodiments are disclosed.

Abstract: A semiconductor device may include: a low-order bit storage block configured for storing N low-order bit signals contained in N access information signals based on an access address signal, the N access information signals indicating the numbers of accesses to N access target blocks, and generating an indication signal indicating whether a low-order bit signal corresponding to the current input access address signal among the N low-order bit signals has reached a predetermined value; a high-order bit storage block configured for storing M high-order bit signals contained in M access information signals among the N access information signals based on an allocation control signal; and a high-order bit control block configured for generating the allocation control signal corresponding to positions in which the M high-order bit signals are to be stored, based on the access address signal and the indication signal.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: A method for power management of a mobile device includes detecting whether a removable power source has been removed from the mobile device. In response to detecting that the power source has been removed, entering a hot swap mode for a first time period by deactivating a first component of the mobile device and maintaining, via a backup power source in the mobile device, a powered state of a second component of the mobile device and an application state of the mobile device. The method further includes, after the first time period, entering a suspend mode for a second time period by deactivating the second component and continuing to maintain the application state of the mobile device for the second time period.

Abstract: A nonvolatile memory device includes a plurality of gate lines extending in a first direction and stacked in a second direction to form a memory block, where the second direction is perpendicular to the first direction, an address decoder disposed at a first side of the plurality of gate lines to drive the plurality of gate lines, a voltage compensation line extending in the first direction substantially in parallel with the plurality of gate lines, and overlapping with a target gate line among the plurality of gate lines in the second direction, a rising vertical contact extending in the second direction to connect the address decoder and a first portion of the voltage compensation line, and conduction paths connecting in the second direction the first and second portions of the voltage compensation line with near and far end portions of the target gate line.

Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a controller configured to generate and output a first command corresponding to a normal operation or a second command corresponding to a deep power down (DPD) mode; and a semiconductor memory device configured to perform the normal operation in response to the first command, wherein the normal operation is performed using an internal power voltage generated by down-converting a first external power voltage, and operate in the DPD mode in response to the second command, wherein, in the DPD mode, the semiconductor memory device operates using a second external power voltage as the internal powervoltage.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. Respective ones of the first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells.

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

Abstract: A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path. The command address input circuit includes a counter that stores and increments the row address. The system also includes a flip-flop that stores the row address in response to receiving a command to refresh the first set of memory banks.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract: The apparatus includes: a row hammer refresh (RHR) circuit configured to: steal a first stolen cycle to implement an RHR operation or a portion thereof, and steal a second stolen cycle after one or more operating cycles, the second stolen cycle to implement the RHR operation or a different portion thereof.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of detective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.

Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

Abstract: In an embodiment, an apparatus includes: an interface circuit to receive thermal information from a system memory; a calculation circuit to determine a rate of thermal change of the system memory based on a current temperature of the system memory, a prior temperature of the system memory and a time duration; and a policy enforcement circuit, in response to a result of a comparison of the rate of thermal change to a threshold, to perform at least one protection measure on the system memory. Other embodiments are described and claimed.

Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Abstract: An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

Abstract: The present disclosure relates to a memory device and an operating method thereof. A memory device includes an enable signal generation unit generating an enable signal in response to a command; a storage unit storing product information of the memory device; an information generation unit generating variable information of the memory device; and an output unit combining the product information from the storage unit with the variable information from the information generation unit and outputting the combined information in response to the enable signal.

Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a power budget operation associated with the memory operation to be performed, based at least in part on information stored in a budget area, such as a register. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation, or incremented upon completion of an operation, associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory (PIM) operation.

Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.

Abstract: The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Techniques are disclosed for notifying network control software of new and moved source MAC addresses. In one embodiment, a switch detects packets sent by a new or migrated virtual machine, and sends a copy of a detected packet to the network control software as a notification. The switch further learns the source MAC address, thereby permitting the entry to be used for normal forwarding prior to validation of the entry and the VM associated therewith by the network control software. Until the network control software has validated the VM, the switch may periodically retry the notification to the network control software. “No_Redirect” and “Not_Validated” flags may be used to indicate whether a notification has already been attempted and thus no retry is necessary, and that the VM associated with the VM has not yet been validated, respectively.

Abstract: Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main word lines, each of which includes paired word lines. Each paired word line includes two redundant word lines. The steering logic circuitry also includes border determination logic that determines whether the redundant word line is on a border between the redundant word lines and an end of the memory bank or the normal word lines. The steering logic circuitry further includes main word line steering logic that determines a neighboring main word line that a second neighboring redundant word line adjacent to the redundant word line is disposed in, and paired word line steering logic that determines a neighboring paired word line that the second neighboring redundant word line is disposed in.

Abstract: An embodiment is directed to an apparatus that comprises a host controller and a flash memory. The host controller monitors a temperature in a first memory block of the flash memory (e.g., based on a reported temperature measurements from the flash memory), and selectively synchronizes a first refresh of the first memory block with a second refresh of a second memory block of the flash memory based in part upon the monitored temperature. For example, an immediate refresh of the first memory block may be performed if there is a pending I/O request for the first memory block, an error rate associated with the first memory block exceeds an error rate threshold and/or the monitored temperature of the first memory block exceeds a temperature threshold; otherwise, a synchronized refresh of the first and second memory blocks may be executed.

Abstract: In accordance with one or more embodiments, a system can include a plurality of uninsulated conductors that is stranded together. The plurality of uninsulated conductors can form a hollow pathway that is bounded by internal conductive surfaces of at least three of the plurality of uninsulated conductors. The system can further include a communication device coupled to a first plurality of external conductive surfaces of the plurality of uninsulated conductors, where the communication device facilitates generating transmission signals at the first plurality of external conductive surfaces, and where the transmission signals induce electromagnetic waves that propagate along the hollow pathway without requiring an electrical return path. Other embodiments are disclosed.