Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: The technology disclosed herein provides a system including multiple selectable storage devices in an enclosure communicatively coupled to shared control electronics the shared control electronics including a first controller for selecting a storage device of the multiple selectable storage devices for execution of a device access command, the multiple scalable storage devices including a plurality of NVM storage devices and at least one hard disc drive (HDD) and a first signal path for transmitting a drive selection instruction from a host external to the enclosure to a first controller the first signal path being a PCIe electronic interface configured to communicate with a host, wherein the plurality of NVM storage devices shares a capacitor bank for power loss protection.

Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.

Abstract: An operating method for a memory system including a host and a memory system.

Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.

Abstract: A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.

Abstract: A method, system, and program product for controlling power associated with connectivity between devices is provided. The method includes scheduling a copy function associated with copying data from a production hardware device to a secure hardware device at a specified time period. A first hardware connection between the production hardware device and a production network associated with the production hardware device is disabled during the specified time period and a second hardware connection between the production hardware device and the secure hardware device is enabled. A subsequent copy function is enabled for copying the data from the production hardware device to the secure hardware device. The second hardware connection between the production hardware device and the secure hardware device is disabled after the copy function has completed. In response, the first hardware connection between the production hardware device and the production network is enabled.

Abstract: According to one embodiment, a memory system includes a controller controls writing data to a non-volatile memory and a volatile memory, a power supply circuit generates voltages with a first voltage externally supplied and supplies the voltages to the non-volatile memory, volatile memory, and controller, and a backup power supply circuit. The power supply circuit, when the first voltage drops irrespective of a shutdown command, generates the voltages with an output voltage of the backup power supply circuit. The controller changes a size of data storable in the volatile memory in accordance with a supply capability fed from the backup power supply circuit.

Abstract: A data storage device and method for prediction-based improved power-loss handling. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to predict a probability of an ungraceful shutdown of the data storage device; determine whether the probability is greater than a threshold; and in response to determining that the probability is greater than the threshold, reduce a risk of data loss that would occur in response to the ungraceful shutdown of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A power management integrated circuit (PMIC) chip provides power loss protection to an application device. The PMIC chip has several storage pins that each receives a set of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

Abstract: A storage device including a non-volatile memory device which receives an operating command and performs an operation corresponding to the operating command, a voltage generating circuit which generates an operating voltage according to the operating command, and a flag generating circuit which receives a busy signal indicative of the non-volatile memory device performing the operation and a pump enable signal instructing pumping of the operating voltage, and outputs a flag signal based on the busy signal and the pump enable signal. The busy signal has a first level when the non-volatile memory device performs the operation, and the flag signal transitions from a second level to the first level in response to the operating voltage becoming equal to or higher than a first reference voltage while the busy signal is at the first level.

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

Abstract: Systems and methods for selective rebuild of interrupted data storage devices in storage arrays are described. A controller determines an operating interruption of a data storage device in a redundant array of independent disks (RAID) configuration. In response to the interruption, the controller determines a last block time value for the last successfully stored RAID block in the interrupted storage device and one or more incomplete RAID stripes that the interrupted storage device did not complete. The controller then selectively rebuilds the incomplete RAID stripes from the other storage devices in the RAID configuration.

Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.

Abstract: An electronic apparatus includes a circuit board, a memory chip mounted on the circuit board, a memory controller to control an operation of the memory chip, a conductive pattern including a first control line to connect from a first terminal of the memory chip to a first terminal of the memory chip and a second control line to connect from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element to provide a termination voltage. The first control line is connected to the capacitive element and the second control line is not connected to the capacitive element.

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Abstract: A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.

Abstract: The invention provides a method for dynamically adjusting user interface, an electronic device and a computer-readable storage medium. The method includes: displaying a user interface, wherein the user interface partially displays a first block, and the first block includes at least one layer; monitoring a first moving direction of a first specific object; in response to determining that the first specific object moves toward the first block, moving at least one of the at least one layer in the first block toward a reference point in the user interface.

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

Abstract: An integrated circuit (IC) layout includes various memory blocks arranged in rows and columns, and a memory controller arranged in parallel to one of the rows and the columns. The IC layout further includes metal routes that are created over the memory blocks for coupling the memory and the memory controller and facilitating signal routing therebetween. Each memory block is coupled with the memory controller by way of one or more metal routes. When the memory controller is arranged in parallel to the rows, the one or more metal routes are created over memory blocks that are included in a column, whereas when the memory controller is arranged in parallel to the columns, the one or more metal routes are created over memory blocks that are included in a row.

Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.

Abstract: A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.

Abstract: An integrated circuit, comprising: a volatile memory module configured to store a cryptographic key; a capacitor array for providing power to the volatile memory module; and a power switching logic arranged to connect and disconnect the memory module from the capacitor array, the power switching logic being configured to operate in at least one of a first operating mode and a second operating mode, wherein, when the power switching logic operates in the first operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting a change of state of a break line, and, when the power switching logic operates in the second operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting that a voltage at a connection terminal of the integrated circuit exceeds a threshold.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.

Abstract: Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.

Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.

Abstract: An address mapping method of a storage device which includes a plurality of sub-storage devices each including an over-provision area includes detecting mapping information of a received logical address from a mapping table, selecting a hash function corresponding to the received logical address depending on the mapping information, selecting any one, which is to be mapped onto the received logical address, of the plurality of sub-storage devices by using the selected hash function, and mapping the received logical address onto the over-provision area of the selected sub-storage device. The selected hash function is selected from a default hash function and a plurality of hash functions to provide a rule for selecting the any one of the plurality of sub-storage devices.

Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

Abstract: A region of a volatile memory can be dynamically resized based on a charge level of a backup battery supply. For example, a computing device can have a volatile memory with a memory region for storing data. The computing device can also have an attached backup battery supply. The computing device can determine a charge level of the backup battery supply and adjust a size of the memory region based on the determined charge level. Adjusting the size of the memory region can involve changing an amount of the volatile memory that is allocated to the memory region.

Abstract: According to an embodiment of the present disclosure, a semiconductor memory device includes a first buffer circuit suitable for receiving a command/address signal to output a first buffered signal according to a first control signal; a first setup/hold circuit suitable for delaying the first buffered signal to output an internal command/address signal according to a second control signal; a command decoder suitable for generating a plurality of internal signals by decoding the internal command/address signal according to a third control signal and an internal dock signal; and a timing controller suitable for delaying a dock enable signal to generate the first to third control signals, and controlling the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from is the first sequence when exiting the power-down mode.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.

Abstract: A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: A method for operating an automation device having a CPU module for processing a control program and a source module that is connected via a bus and is intended to supply sink modules of the automation device with electrical energy, wherein variables that are available to the automation device and which influence the operation of the automation device are recorded so as to make it possible to relieve the load on the CPU module when preprocessing the influencing variables.

Abstract: Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.

Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.

Abstract: A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R1. The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R1 and the pull-up resistor or the pull-down resistor, and the resistor R1 is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: An electronic device can include a battery bus, a load having a transient power requirement, and a transient power management circuit coupled between the battery bus and the load and configured to meet the transient instantaneous power requirement of the load while maintaining a minimum voltage on the battery bus. The transient power management circuit can include a boost converter coupled between the battery bus and a capacitor bank, and the load may be coupled to the capacitor bank. A control circuit may be configured to operate the boost converter to charge the capacitor bank. A control switch may be coupled between the boost converter and the capacitor bank, and the control circuit may be further configured to limit inrush current into the capacitor bank. Additionally, a state of charge of the battery may be estimated from a time required to charge the capacitor bank.

Abstract: A computer system includes a front end interface configured for data communications over a network with data producer terminals, multiple distributed data processors coupled to the front end interface by a data messaging infrastructure, the multiple distributed data processors including a first distributed data processor and a second distributed data processor, and an information bus coupled to the multiple distributed data processors and to multiple independent consumer modules. The first processor receives and processes data order messages for the first security, and maintains a first order book that stores outstanding orders for the first security. The second processor receives and processes received data order messages for the second security, and maintains a second order book that stores outstanding orders for the second security.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a first node and having an input terminal that receives a third voltage, a first transistor having a first gate, and a first source and a first drain between the first node and a second voltage source, a second transistor having a second source connected to the second voltage source, and a second gate and a second drain connected to the first node, and an amplifier having an input terminal connected to an output terminal of the inverter and configured to output a first voltage from the first voltage or a second voltage from the second voltage source based on or in response to an output of the inverter.

Abstract: A multi-function display system is configured to allow customization of inputs, outputs, and a display to an aircraft or other vehicle. The multi-function display provides custom outputs and a custom display by utilizing a configuration file, while maintaining the initial certification basis of the product hardware and software. The multi-function display is configured to receive a configuration file from a user via the communications element, wherein the configuration file includes information that defines the custom outputs; receive, during flight mode and from a sensor, a first parameter; access, during flight mode, the configuration file; perform, during flight mode, a data function on the first parameter; calculate, during flight mode, an output function based upon the data function and the configuration file; and provide, during flight mode, the output on the display or to another computing device.

Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.