Data Preservation Patents (Class 365/228)
  • Patent number: 10970219
    Abstract: A storage system may maintain a purge counter for one or more logical storage units. When an instruction is received to perform an operation that will modify data across the one or more logical storage units, the purge counter may be incremented. One or more host systems implementing host caching may periodically poll the storage system to determine the purge counter value. When the current value of the purge counter value is different than a previously polled purge counter value recorded on a host system, the host system may purge from its host cache any entries for logical storage units associated with the purge counter. The data storage system may not execute the data modification instruction until it receives acknowledgement from all host systems caching data affected by the modification instruction that the host system has purged any host cache entries corresponding to the LSUs affected by the modification operation.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael J. Scharland, Ian Wigmore, Arieh Don
  • Patent number: 10892882
    Abstract: Systems and methods presented herein provide for improved duplex communications in an RF cable network comprising a plurality of CMs. In one embodiment, a system includes a CMTS operable to transmit downstream communications to the CMs and to process upstream communications from the CMs. The system also includes a duplex RF communication path between the CMTS and the CMs. The CMTS is further operable to transmit a control signal that directs a first of the CMs to transmit, to direct the remaining CMs to receive the transmission from the first CM, to direct the CMs to report received power levels of the transmission from the first CM, and to calculate RF isolations of the remaining CMs with respect to the first CM based on the reported power levels.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Belal Hamzeh, Thomas H. Williams, Daniel Rice, Luis Alberto Campos
  • Patent number: 10831381
    Abstract: A method includes detecting a change to one or more of: a credential of set of storage units supporting a logical storage vault and access control information for a user group affiliated with the logical storage vault. The method further includes, in response to the detecting, determining, whether the logical storage vault is in a relationship with another logical storage vault. When the logical storage vault is in the relationship, determining whether the logical storage vault is an originating vault or a subservient vault. When the logical storage vault is the originating vault, sending updated access control information to the second set of storage units regarding a change to the access control information. When the logical storage vault is the subservient vault, sending an updated credential of the set of storage units to the computing device regarding a change to the credential of the set of storage units.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10824344
    Abstract: A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Abhijeet Gole, Philip A. Kufeldt
  • Patent number: 10802917
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuji Nishikubo, Jun Kano
  • Patent number: 10804631
    Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Timothy Wig, Manisha M. Nilange, Thane M. Larson, Horthense Delphine Tamdem
  • Patent number: 10789163
    Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Wen-Sheng Lin
  • Patent number: 10783034
    Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Chihoko Shigeta, Kazuya Kitsunai
  • Patent number: 10762971
    Abstract: Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Bonitz
  • Patent number: 10725532
    Abstract: Data storage system power shedding for vaulting and/or backup is provided herein. A data storage system can include a processor that executes computer-executable components, at least one memory, and a basic input/output system device that stores respective ones of the computer-executable components executed by the processor. The computer-executable components comprise a power monitor component that monitors an input alternating current power level of the data storage system, a processor management component that causes the processor to transition from a multiple-core operating mode to a single-core operating mode in response to an indication from the power monitor component that the input AC power level has decreased below a threshold, and a backup component that initiates a transfer of data stored by the at least one memory to at least one backup storage device in response to the processor being configured to operate in the single-core operating mode.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: July 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: James C. Tryhubczak, Wuck Foo Wong
  • Patent number: 10640086
    Abstract: A motorcycle (1) including: an electronic system of authorization control (100,200); wherein: a first electronic control unit (200) is adapted and configured to determine whether the motorcycle (1) is in an authorized or non-authorized usage state and is adapted to interrogate a portable transponder, which can have a master identification electronic code or a slave identification electronic code, in order to acquire said electronic code and to verify if said electronic code is correct; and wherein: if the first control unit (200) acquires the master identification electronic code, starting the traction engine is allowed independently from the second electronic control unit; if the first control unit (200) acquires the slave identification electronic code, it is determined that the motorcycle (1) is in the authorized usage state and starting the traction engine is allowed if it receives consent information from the second electronic control unit (100).
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 5, 2020
    Assignee: PIAGGIO & C. SPA
    Inventor: Luigi Baracchino
  • Patent number: 10613943
    Abstract: Systems, methods, and/or devices are used to manage open blocks within non-volatile storage devices, in order to improve the reliability of non-volatile storage devices. In some embodiments, when a shut-down request is received from a host device, the storage device fetches information about open blocks and their boundary regions susceptible to data reliability issues, and for each identified boundary region, the storage device programs a region contiguous to the identified boundary region. In some embodiments, the device updates an XOR parity table used for XOR parity management with the information that the region contiguous to the identified boundary is programmed. Subsequently, in some embodiments, the storage device can use the information, stored in the contiguous region and/or the XOR parity table, for data recovery in the event of a data loss. As a result, the reliability of the non-volatile storage device is improved.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zelei Guo, Chao-Han Cheng, Nan Lu, Tienchien Kuo, Niles Nian Yang
  • Patent number: 10599503
    Abstract: An information handling system may implement techniques for triggering power loss protection on solid-state storage devices (SSDs) based on PSU pre-warning signals (such as de-asserted POK or VIN_GOOD signals) indicating that power loss is imminent. The pre-warning signals may be provided directly to SSDs over a dedicated connection or may be passed through other components of the information handling system (such as power loss warning logic, a platform controller hub, or a CPU) to a storage controller. The pre-warning signal may be provided to the storage controller as a power loss warning interrupt. This interrupt may cause the storage system controller to issue an in-band message/command to the SSDs or to provide a signal on a dedicated connection to the SSDs in order to trigger power loss protection actions on the SSDs, including switching their power sources and flushing write queues before available hold-up energy is depleted.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 24, 2020
    Assignee: Dell Products L.P.
    Inventors: Amir Rahmanian, John E. Jenne
  • Patent number: 10573354
    Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 25, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Satyanarayan Shivkumar Iyer, Robert S. Pauley, Jr.
  • Patent number: 10496546
    Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Tetsufumi Tanamoto, Kazutaka Ikegami, Shinobu Fujita
  • Patent number: 10481958
    Abstract: An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel IP Corporation
    Inventors: Thomas Willhalm, Karthik Kumar
  • Patent number: 10430262
    Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, Jr., Yun Li, Kishore Kumar Muchherla
  • Patent number: 10430882
    Abstract: A computer system includes a front end interface configured for data communications over a network with data producer terminals, multiple distributed data processors coupled to the front end interface by a data messaging infrastructure, the multiple distributed data processors including a first distributed data processor and a second distributed data processor, and an information bus coupled to the multiple distributed data processors and to multiple independent consumer modules. The first processor receives and processes data order messages for the first security, and maintains a first order book that stores outstanding orders for the first security. The second processor receives and processes received data order messages for the second security, and maintains a second order book that stores outstanding orders for the second security.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 1, 2019
    Assignee: Nasdaq, Inc.
    Inventors: John T. Hughes, Jr., Bruce E. Friedman
  • Patent number: 10423783
    Abstract: Methods and apparatus to recover a processor state during a system failure or security event are disclosed. An example apparatus to recover data includes a processor including a local memory and a system monitor in communication with the processor. The system monitor is to copy processor backup data to a non-volatile memory in response to a processor backup event. The processor backup data includes contents of the local memory.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Chris Pavlas, James R. Hearn, Scott P. Dubal, Patrick Connor
  • Patent number: 10394310
    Abstract: Sleep modes use non-volatile dual inline memory modules (NVDIMMs) to reduce electrical power and execution times. An S3 suspend-to-RAM, for example, may store a system state to NVDIMM via a high-speed memory bus. Likewise, an S4 suspend-to-disk may store a restoration file to the NVDIMM via the high-speed memory bus. When a server or other information handling system is then awakened, execution resumes in less time due to the NVDIMM.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 27, 2019
    Assignee: Dell Products, LP
    Inventors: Randall E. Juenger, Mark L. Rehmann
  • Patent number: 10360143
    Abstract: A mobile device having parallel use of non-volatile memory and main memory is presented. The mobile device includes a volatile memory, a non-volatile memory, a memory controller functionally coupled to the non-volatile memory and the volatile memory, and a processor coupled to the memory controller. The processor addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map. Alternatively, a mobile device may include a volatile memory, a non-volatile memory, a memory controller coupled to the volatile memory, a processor coupled to the memory controller. The processor may address the volatile memory during normal operation. The mobile device may further include a shadow copy controller coupled to the non-volatile memory and the memory controller, where the shadow copy controller copies information stored in a designated portion of the volatile memory into the non-volatile memory.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Christopher Kong Yee Chun
  • Patent number: 10236062
    Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Ikegami, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Hiroki Noguchi
  • Patent number: 10152393
    Abstract: Embodiments of recovering data in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving a failure notification indicating that a core of a main processor is experiencing a catastrophic failure causing the core unable to execute instructions. In response, a flush command can be issued to an uncore of the processor via a debug port instructing the uncore to copy any data currently residing in a processor cache of the main processor to a volatile memory. The method further includes issuing a self-refresh command causing the volatile memory to enter a self-refresh mode in which the data copied from the processor cache is maintained and unmodifiable by the main processor during a reset of the main processor.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: December 11, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Ali Hassan Larijani
  • Patent number: 10127968
    Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Shanker R. Nagesh, K L Siva Prasad Gadey N V, Blaine R. Monson, Pankaj Kumar
  • Patent number: 10061369
    Abstract: A system enables personal information manager (PIM) applications to continue to provide alerts and other time sensitive information even when the system upon which the PIM is stored is turned off. Automatically data may be transferred from a first processor-based system to a second processor-based system to implement time sensitive activities. The second processor-based system may provide a user notification at a predetermined time preset on the first processor-based system.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventor: Randy P. Stanley
  • Patent number: 10007579
    Abstract: Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 26, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mark A. Shaw, Scott Chao-Chueh Lee, Sriram Govindan, Bryan Kelly
  • Patent number: 10001947
    Abstract: An example computer-implemented method for performing efficient patrol read operations in a storage system including a plurality of disks organized in a RAID array can include determining an I/O load on the storage system, identifying at least one portion of an available storage capacity containing valid data and reading the portion of the available storage capacity containing the valid data. Optionally, the portion of the available storage capacity containing the valid data is the only portion read during the patrol read operations. The method can also include determining whether a medium error exists in the portion of the available storage capacity containing the valid data. If a medium error exists, the method can include fixing the medium error. Additionally, the above operations can optionally be performed only when the I/O load on the storage system is less than a predetermined threshold.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 19, 2018
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Loganathan Ranganathan, Venugopalreddy Mallavaram, Sankarji Gopalakrishnan
  • Patent number: 9904818
    Abstract: Provided are RFID systems, methods and RFID tags according to various aspects. An infrared (IR) beam, from an IR transmitter, is outputted in a first direction so that an RFID tag with an IR sensor adds a flag to stored data in the RFID tag in response to the RFID tag's IR sensor detecting the IR beam. An RF interrogation signal is outputted by an RFID reader, and a response is received from the RFID tag to the RF interrogation signal. It is determined whether the flag is contained in the RFID tag's response to the RF interrogation signal, and if so, the RFID tag is determined to be in the first direction relative to the IR transmitter.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 27, 2018
    Assignee: INTERMEC IP CORP.
    Inventors: Pavel Nikitin, Stephen J. Kelly
  • Patent number: 9891695
    Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Ariel Berkovits, Michael Mishaeli, Nadav Shulman, Sameer Desai, Shani Rehana, Ittai Anati, Hisham Shafi
  • Patent number: 9880783
    Abstract: Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the host data buffer that had been storing the subset identified in the message rather than waiting to release data associated with the host write command until all the data associated with the command is stored in the memory. The memory in which each subset is stored may be non-volatile memory in the storage device or a shadow buffer on the host or an external memory device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Rotem Sela, Alon Marcu, Nir Perry, Miki Sapir, Hadas Oshinsky, Julian Vlaiko
  • Patent number: 9883067
    Abstract: A control apparatus includes a first control unit, a second control unit including a memory for storing information for performing startup processing, and a power supply unit configured to supply electric power to the first control unit and the second control unit, and in a case where electric power is supplied from the power supply unit to the second control unit, whether a startup state of the second control unit is normal is determined. In a case where the startup state of the second control unit is determined to be normal, the power supply unit supplies electric power to the first control unit. In a case where the startup state of the second control unit is determined to be not normal, to power supply to the memory from a backup power supply for the memory is stopped so as to clear the memory of the second control unit.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 30, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuhiro Kozuka
  • Patent number: 9870281
    Abstract: A Data Storage Device (DSD) includes a disk for storing data, a volatile memory for temporarily storing data to be written on the disk, and a Non-Volatile Solid-State Memory (NVSM) for storing data. Data is stored in the volatile memory in preparation for writing the data on the disk. The data is written from the volatile memory onto the disk, and it is determined whether the data written on the disk is qualified as written. In the event of an unexpected power loss, a portion of unqualified data that has not been qualified as written is transferred from the volatile memory to the NVSM.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: January 16, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Asif F. Gosla, Scott E. Burton, Chiranjeb Mondal
  • Patent number: 9837166
    Abstract: A data storage device includes a controller configured to control data to be written in a first page; and a nonvolatile memory device configured to perform a write operation for writing the data, according to whether the first page is written or not, wherein the nonvolatile memory device provides a state information including an overwrite information meaning whether the write operation has caused an overwrite, to the controller.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hyun Jun Kim, Byeong Gyu Park, Joong Seob Yang
  • Patent number: 9824734
    Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stored in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the second channel.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjin Cho, Younggeun Lee, Han-Ju Lee, Hyo-Deok Shin
  • Patent number: 9811456
    Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 7, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David A. Roberts
  • Patent number: 9753828
    Abstract: Maintaining failure survivability in a storage system includes determining a save time corresponding to an amount of time needed to transfer system data from volatile memory to non-volatile memory, determining a threshold corresponding to time for batteries to run while transferring data from volatile memory to non-volatile memory after a power loss, and providing an indication in response to the save time being greater than the threshold. The system may include a plurality of directors and the save time and the threshold may be determined for each of the directors. Determining a threshold may include determining an amount of battery time provided by battery power following power loss and multiplying the amount of battery time by a factor less than one, such as 0.8.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 5, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Preston F. Crow, Preethi Natarajan, Steven T. McClure
  • Patent number: 9727111
    Abstract: A control device for current switching includes: a universal serial bus on-the-go (USB OTG) interface for connecting to a first device; a universal serial bus (USB) interface for connecting to a second device; a booster current-limiting circuit connected between the USB OTG interface and the USB interface, where the booster current-limiting circuit, the USB OTG interface, and the USB interface form a line for the device to supply power to a device; and a measuring and controlling unit connected to the booster current-limiting circuit, where the measuring and controlling unit is configured to change, after a current switching request is received, a resistance value of a current-limiting circuit in the booster current-limiting circuit, so that the first device supplies a corresponding current to the second device. The control device for current switching and the electronic device can improve universality of the control device for current switching.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 8, 2017
    Assignee: Huawei Device Co., Ltd.
    Inventor: Shunhai Xu
  • Patent number: 9690664
    Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 27, 2017
    Assignee: HITACHI, LTD.
    Inventors: Kyohei Ide, Naoki Moritoki, Sumihiro Miura
  • Patent number: 9665750
    Abstract: Provided are RFID systems, methods and RFID tags according to various aspects. An infrared (IR) beam, from an IR transmitter, is outputted in a first direction so that an RFID tag with an IR sensor adds a flag to stored data in the RFID tag in response to the RFID tag's IR sensor detecting the IR beam. An RF interrogation signal is outputted by an RFID reader, and a response is received from the RFID tag to the RF interrogation signal. It is determined whether the flag is contained in the RFID tag's response to the RF interrogation signal, and if so, the RFID tag is determined to be in the first direction relative to the IR transmitter.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERMEC IP CORP
    Inventors: Pavel Nikitin, Stephen J. Kelly
  • Patent number: 9651398
    Abstract: A method for checking a total distance travelled by a motor vehicle and displaying the total distance in the motor vehicle includes: detecting a change in a component of a control device of the motor vehicle, change in the component being irreversible and taking place over a time period; assigning the magnitude and/or type of the change in the component to a comparison distance, related to the time period, travelled by the motor vehicle; comparing a distance detected by an odometer of the motor vehicle during the time period with the comparison distance; and an operator of the motor vehicle retrieving a result of the comparison or the operator receiving an automatic transmission of the result of the comparison.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: May 16, 2017
    Assignee: Continental Automotive GmbH
    Inventors: Ulrich Deml, Ralf Lenninger
  • Patent number: 9645829
    Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 9, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Adam J. Brooks, George Vergis
  • Patent number: 9645894
    Abstract: A data storage device and a flash memory control method with a power recovery design. A microcontroller is configured to allocate a flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data. During a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: May 9, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Chia-Chi Liang, Chang-Chieh Huang, Jie-Hao Lee
  • Patent number: 9632935
    Abstract: In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: April 25, 2017
    Assignee: Dell Products L.P.
    Inventors: Jacob Cherian, Marcelo Saraiva, Shane Chiasson, Gary Kotzur, Douglas Huang, Anand Nunna, William Lynn
  • Patent number: 9607664
    Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
  • Patent number: 9600283
    Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Ethan Schuchman, Hong Wang, Chris Weaver, Belliappa M. Kuttanna, Asit Mallick, Vivek K. De, Per Hammarlund
  • Patent number: 9547589
    Abstract: A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 17, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 9548108
    Abstract: A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. Ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 17, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yi Syu Yan
  • Patent number: 9530461
    Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Jason B. Akers, Knut S. Grimsrud, Robert J. Royer, Jr., Richard P. Mangold, Sanjeev Trika
  • Patent number: 9437252
    Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: September 6, 2016
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Kwak, Sang Hoon Shin, Keun Soo Song
  • Patent number: RE47621
    Abstract: A high security microcontroller (such as in a point of sale terminal) includes tamper control circuitry for detecting vulnerability conditions: a write to program memory before the sensitive financial information has been erased, a tamper detect condition, the enabling of a debugger, a power-up condition, an illegal temperature condition, an illegal supply voltage condition, an oscillator fail condition, and a battery removal condition. If the tamper control circuitry detects a vulnerability condition, then the memory where the sensitive financial information could be stored is erased before boot loader operation or debugger operation can be enabled. Upon power-up if a valid image is detected in program memory, then the boot loader is not executed and secure memory is not erased but rather the image is executed. The tamper control circuitry is a hardware state machine that is outside control of user-loaded software and is outside control of the debugger.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Peter C. Hsiang, Raymond O. Chock, Mark Hess