Data Preservation Patents (Class 365/228)
  • Patent number: 12014800
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: June 18, 2024
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 12007821
    Abstract: A power management integrated circuit (PMIC) chip provides power loss protection to an application device. The PMIC chip has several storage pins that each receives a set of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 11, 2024
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ming Lu, Pengjie Lai
  • Patent number: 11990199
    Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Taeksang Song, Saira Samar Malik, Hyunyoo Lee, Chinnakrishnan Ballapuram, Kang-Yong Kim
  • Patent number: 11954361
    Abstract: A storage device including a non-volatile memory device which receives an operating command and performs an operation corresponding to the operating command, a voltage generating circuit which generates an operating voltage according to the operating command, and a flag generating circuit which receives a busy signal indicative of the non-volatile memory device performing the operation and a pump enable signal instructing pumping of the operating voltage, and outputs a flag signal based on the busy signal and the pump enable signal. The busy signal has a first level when the non-volatile memory device performs the operation, and the flag signal transitions from a second level to the first level in response to the operating voltage becoming equal to or higher than a first reference voltage while the busy signal is at the first level.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Jin Shin, Do Hui Kim, Han Byul Choi
  • Patent number: 11853158
    Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: December 26, 2023
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11853163
    Abstract: Systems and methods for selective rebuild of interrupted data storage devices in storage arrays are described. A controller determines an operating interruption of a data storage device in a redundant array of independent disks (RAID) configuration. In response to the interruption, the controller determines a last block time value for the last successfully stored RAID block in the interrupted storage device and one or more incomplete RAID stripes that the interrupted storage device did not complete. The controller then selectively rebuilds the incomplete RAID stripes from the other storage devices in the RAID configuration.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kushal Hosmani
  • Patent number: 11823755
    Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 11797225
    Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: October 24, 2023
    Inventors: George Pax, Jonathan Scott Parry
  • Patent number: 11798599
    Abstract: An electronic apparatus includes a circuit board, a memory chip mounted on the circuit board, a memory controller to control an operation of the memory chip, a conductive pattern including a first control line to connect from a first terminal of the memory chip to a first terminal of the memory chip and a second control line to connect from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element to provide a termination voltage. The first control line is connected to the capacitive element and the second control line is not connected to the capacitive element.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 24, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jung Soo Park
  • Patent number: 11775218
    Abstract: A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jonathan Parry
  • Patent number: 11762460
    Abstract: The invention provides a method for dynamically adjusting user interface, an electronic device and a computer-readable storage medium. The method includes: displaying a user interface, wherein the user interface partially displays a first block, and the first block includes at least one layer; monitoring a first moving direction of a first specific object; in response to determining that the first specific object moves toward the first block, moving at least one of the at least one layer in the first block toward a reference point in the user interface.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 19, 2023
    Assignee: HTC Corporation
    Inventors: Jing-Lung Wu, Ya-Chih Hsiao, Ching-Yang Chen
  • Patent number: 11762553
    Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Reshmi Basu, Richard C. Murphy
  • Patent number: 11694015
    Abstract: An integrated circuit (IC) layout includes various memory blocks arranged in rows and columns, and a memory controller arranged in parallel to one of the rows and the columns. The IC layout further includes metal routes that are created over the memory blocks for coupling the memory and the memory controller and facilitating signal routing therebetween. Each memory block is coupled with the memory controller by way of one or more metal routes. When the memory controller is arranged in parallel to the rows, the one or more metal routes are created over memory blocks that are included in a column, whereas when the memory controller is arranged in parallel to the columns, the one or more metal routes are created over memory blocks that are included in a row.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 4, 2023
    Assignee: NXP B.V.
    Inventors: Himanshu Mangal, Pankaj Mudgil, Siddhartha Jain
  • Patent number: 11675664
    Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: June 13, 2023
    Assignee: Dell Products, L.P.
    Inventors: James Guyer, Richard Boyle, John Burroughs, Clifford Lim, Michael Salerno, Jr
  • Patent number: 11656669
    Abstract: A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: May 23, 2023
    Inventors: Sompong Paul Olarig, Ramdas P. Kachare, Wentao Wu
  • Patent number: 11630784
    Abstract: An integrated circuit, comprising: a volatile memory module configured to store a cryptographic key; a capacitor array for providing power to the volatile memory module; and a power switching logic arranged to connect and disconnect the memory module from the capacitor array, the power switching logic being configured to operate in at least one of a first operating mode and a second operating mode, wherein, when the power switching logic operates in the first operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting a change of state of a break line, and, when the power switching logic operates in the second operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting that a voltage at a connection terminal of the integrated circuit exceeds a threshold.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: April 18, 2023
    Assignee: Raytheon Company
    Inventor: Nathan T. Palmer
  • Patent number: 11600663
    Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 7, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 11579651
    Abstract: Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 14, 2023
    Assignee: Cummins Inc.
    Inventors: Abhik Giri, Mark Swain, Ashish Raj Jain, Ming Feng, Astha Ganjoo, Shreya Ghatge
  • Patent number: 11581023
    Abstract: A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Shaun Alan Stickel
  • Patent number: 11581029
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 14, 2023
    Assignee: LONGITUDE ELASH MEMORY SOLUTIONS LTD
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 11561739
    Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 24, 2023
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Kelvin Alberto Marino
  • Patent number: 11513971
    Abstract: An address mapping method of a storage device which includes a plurality of sub-storage devices each including an over-provision area includes detecting mapping information of a received logical address from a mapping table, selecting a hash function corresponding to the received logical address depending on the mapping information, selecting any one, which is to be mapped onto the received logical address, of the plurality of sub-storage devices by using the selected hash function, and mapping the received logical address onto the over-provision area of the selected sub-storage device. The selected hash function is selected from a default hash function and a plurality of hash functions to provide a rule for selecting the any one of the plurality of sub-storage devices.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 29, 2022
    Inventors: Keonsoo Ha, Minseok Ko, Hyunjoo Maeng, Jihyung Park
  • Patent number: 11488668
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Patent number: 11449229
    Abstract: A region of a volatile memory can be dynamically resized based on a charge level of a backup battery supply. For example, a computing device can have a volatile memory with a memory region for storing data. The computing device can also have an attached backup battery supply. The computing device can determine a charge level of the backup battery supply and adjust a size of the memory region based on the determined charge level. Adjusting the size of the memory region can involve changing an amount of the volatile memory that is allocated to the memory region.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 20, 2022
    Assignee: RED HAT, INC.
    Inventors: Gabriel Zvi BenHanokh, Joshua Durgin
  • Patent number: 11423954
    Abstract: According to an embodiment of the present disclosure, a semiconductor memory device includes a first buffer circuit suitable for receiving a command/address signal to output a first buffered signal according to a first control signal; a first setup/hold circuit suitable for delaying the first buffered signal to output an internal command/address signal according to a second control signal; a command decoder suitable for generating a plurality of internal signals by decoding the internal command/address signal according to a third control signal and an internal dock signal; and a timing controller suitable for delaying a dock enable signal to generate the first to third control signals, and controlling the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from is the first sequence when exiting the power-down mode.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Noh Hyup Kwak
  • Patent number: 11418194
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 11398270
    Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 26, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Kai Tian
  • Patent number: 11385709
    Abstract: A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: July 12, 2022
    Assignee: GOWIN SEMICONDUCTOR CORPORATION, Ltd.
    Inventor: Jinghui Zhu
  • Patent number: 11381235
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 5, 2022
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11360444
    Abstract: A method for operating an automation device having a CPU module for processing a control program and a source module that is connected via a bus and is intended to supply sink modules of the automation device with electrical energy, wherein variables that are available to the automation device and which influence the operation of the automation device are recorded so as to make it possible to relieve the load on the CPU module when preprocessing the influencing variables.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: June 14, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventor: Norbert Rottmann
  • Patent number: 11355214
    Abstract: Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Junam Kim
  • Patent number: 11342784
    Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 24, 2022
    Assignee: Woven Planet North America, Inc.
    Inventors: Chen-yu Hsieh, Catalin Popovici
  • Patent number: 11314917
    Abstract: A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R1. The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R1 and the pull-up resistor or the pull-down resistor, and the resistor R1 is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 26, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Peng Wang
  • Patent number: 11257527
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park, Kyoung Lae Cho
  • Patent number: 11233390
    Abstract: An electronic device can include a battery bus, a load having a transient power requirement, and a transient power management circuit coupled between the battery bus and the load and configured to meet the transient instantaneous power requirement of the load while maintaining a minimum voltage on the battery bus. The transient power management circuit can include a boost converter coupled between the battery bus and a capacitor bank, and the load may be coupled to the capacitor bank. A control circuit may be configured to operate the boost converter to charge the capacitor bank. A control switch may be coupled between the boost converter and the capacitor bank, and the control circuit may be further configured to limit inrush current into the capacitor bank. Additionally, a state of charge of the battery may be estimated from a time required to charge the capacitor bank.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 25, 2022
    Assignee: Apple Inc.
    Inventors: Samuel B. Schaevitz, Nicholas D. Shourounis, Justin D. Schunick
  • Patent number: 11157999
    Abstract: A computer system includes a front end interface configured for data communications over a network with data producer terminals, multiple distributed data processors coupled to the front end interface by a data messaging infrastructure, the multiple distributed data processors including a first distributed data processor and a second distributed data processor, and an information bus coupled to the multiple distributed data processors and to multiple independent consumer modules. The first processor receives and processes data order messages for the first security, and maintains a first order book that stores outstanding orders for the first security. The second processor receives and processes received data order messages for the second security, and maintains a second order book that stores outstanding orders for the second security.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 26, 2021
    Assignee: Nasdaq, Inc.
    Inventors: John T. Hughes, Jr., Bruce E. Friedman
  • Patent number: 11063587
    Abstract: A voltage on-off detector includes an inverter between a first voltage source and a first node and having an input terminal that receives a third voltage, a first transistor having a first gate, and a first source and a first drain between the first node and a second voltage source, a second transistor having a second source connected to the second voltage source, and a second gate and a second drain connected to the first node, and an amplifier having an input terminal connected to an output terminal of the inverter and configured to output a first voltage from the first voltage or a second voltage from the second voltage source based on or in response to an output of the inverter.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 13, 2021
    Assignee: DB HiTek Co., Ltd.
    Inventors: Sang Mok Lee, Joon Tae Jang, Seung Hoo Kim
  • Patent number: 11048389
    Abstract: A multi-function display system is configured to allow customization of inputs, outputs, and a display to an aircraft or other vehicle. The multi-function display provides custom outputs and a custom display by utilizing a configuration file, while maintaining the initial certification basis of the product hardware and software. The multi-function display is configured to receive a configuration file from a user via the communications element, wherein the configuration file includes information that defines the custom outputs; receive, during flight mode and from a sensor, a first parameter; access, during flight mode, the configuration file; perform, during flight mode, a data function on the first parameter; calculate, during flight mode, an output function based upon the data function and the configuration file; and provide, during flight mode, the output on the display or to another computing device.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 29, 2021
    Assignee: Mid-Continent Instrument Co., Inc.
    Inventors: Brett Alan Williams, Cary Allen Shoup
  • Patent number: 10992166
    Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Lyft, Inc.
    Inventors: Chen-yu Hsieh, Catalin Popovici
  • Patent number: 10970219
    Abstract: A storage system may maintain a purge counter for one or more logical storage units. When an instruction is received to perform an operation that will modify data across the one or more logical storage units, the purge counter may be incremented. One or more host systems implementing host caching may periodically poll the storage system to determine the purge counter value. When the current value of the purge counter value is different than a previously polled purge counter value recorded on a host system, the host system may purge from its host cache any entries for logical storage units associated with the purge counter. The data storage system may not execute the data modification instruction until it receives acknowledgement from all host systems caching data affected by the modification instruction that the host system has purged any host cache entries corresponding to the LSUs affected by the modification operation.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael J. Scharland, Ian Wigmore, Arieh Don
  • Patent number: 10892882
    Abstract: Systems and methods presented herein provide for improved duplex communications in an RF cable network comprising a plurality of CMs. In one embodiment, a system includes a CMTS operable to transmit downstream communications to the CMs and to process upstream communications from the CMs. The system also includes a duplex RF communication path between the CMTS and the CMs. The CMTS is further operable to transmit a control signal that directs a first of the CMs to transmit, to direct the remaining CMs to receive the transmission from the first CM, to direct the CMs to report received power levels of the transmission from the first CM, and to calculate RF isolations of the remaining CMs with respect to the first CM based on the reported power levels.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Belal Hamzeh, Thomas H. Williams, Daniel Rice, Luis Alberto Campos
  • Patent number: 10831381
    Abstract: A method includes detecting a change to one or more of: a credential of set of storage units supporting a logical storage vault and access control information for a user group affiliated with the logical storage vault. The method further includes, in response to the detecting, determining, whether the logical storage vault is in a relationship with another logical storage vault. When the logical storage vault is in the relationship, determining whether the logical storage vault is an originating vault or a subservient vault. When the logical storage vault is the originating vault, sending updated access control information to the second set of storage units regarding a change to the access control information. When the logical storage vault is the subservient vault, sending an updated credential of the set of storage units to the computing device regarding a change to the credential of the set of storage units.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10824344
    Abstract: A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Abhijeet Gole, Philip A. Kufeldt
  • Patent number: 10804631
    Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Timothy Wig, Manisha M. Nilange, Thane M. Larson, Horthense Delphine Tamdem
  • Patent number: 10802917
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuji Nishikubo, Jun Kano
  • Patent number: 10789163
    Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Wen-Sheng Lin
  • Patent number: 10783034
    Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Chihoko Shigeta, Kazuya Kitsunai
  • Patent number: 10762971
    Abstract: Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Bonitz
  • Patent number: 10725532
    Abstract: Data storage system power shedding for vaulting and/or backup is provided herein. A data storage system can include a processor that executes computer-executable components, at least one memory, and a basic input/output system device that stores respective ones of the computer-executable components executed by the processor. The computer-executable components comprise a power monitor component that monitors an input alternating current power level of the data storage system, a processor management component that causes the processor to transition from a multiple-core operating mode to a single-core operating mode in response to an indication from the power monitor component that the input AC power level has decreased below a threshold, and a backup component that initiates a transfer of data stored by the at least one memory to at least one backup storage device in response to the processor being configured to operate in the single-core operating mode.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: July 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: James C. Tryhubczak, Wuck Foo Wong
  • Patent number: 10640086
    Abstract: A motorcycle (1) including: an electronic system of authorization control (100,200); wherein: a first electronic control unit (200) is adapted and configured to determine whether the motorcycle (1) is in an authorized or non-authorized usage state and is adapted to interrogate a portable transponder, which can have a master identification electronic code or a slave identification electronic code, in order to acquire said electronic code and to verify if said electronic code is correct; and wherein: if the first control unit (200) acquires the master identification electronic code, starting the traction engine is allowed independently from the second electronic control unit; if the first control unit (200) acquires the slave identification electronic code, it is determined that the motorcycle (1) is in the authorized usage state and starting the traction engine is allowed if it receives consent information from the second electronic control unit (100).
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 5, 2020
    Assignee: PIAGGIO & C. SPA
    Inventor: Luigi Baracchino