Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.

Abstract: A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: A method for operating an automation device having a CPU module for processing a control program and a source module that is connected via a bus and is intended to supply sink modules of the automation device with electrical energy, wherein variables that are available to the automation device and which influence the operation of the automation device are recorded so as to make it possible to relieve the load on the CPU module when preprocessing the influencing variables.

Abstract: Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.

Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.

Abstract: A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R1. The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R1 and the pull-up resistor or the pull-down resistor, and the resistor R1 is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: An electronic device can include a battery bus, a load having a transient power requirement, and a transient power management circuit coupled between the battery bus and the load and configured to meet the transient instantaneous power requirement of the load while maintaining a minimum voltage on the battery bus. The transient power management circuit can include a boost converter coupled between the battery bus and a capacitor bank, and the load may be coupled to the capacitor bank. A control circuit may be configured to operate the boost converter to charge the capacitor bank. A control switch may be coupled between the boost converter and the capacitor bank, and the control circuit may be further configured to limit inrush current into the capacitor bank. Additionally, a state of charge of the battery may be estimated from a time required to charge the capacitor bank.

Abstract: A computer system includes a front end interface configured for data communications over a network with data producer terminals, multiple distributed data processors coupled to the front end interface by a data messaging infrastructure, the multiple distributed data processors including a first distributed data processor and a second distributed data processor, and an information bus coupled to the multiple distributed data processors and to multiple independent consumer modules. The first processor receives and processes data order messages for the first security, and maintains a first order book that stores outstanding orders for the first security. The second processor receives and processes received data order messages for the second security, and maintains a second order book that stores outstanding orders for the second security.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a first node and having an input terminal that receives a third voltage, a first transistor having a first gate, and a first source and a first drain between the first node and a second voltage source, a second transistor having a second source connected to the second voltage source, and a second gate and a second drain connected to the first node, and an amplifier having an input terminal connected to an output terminal of the inverter and configured to output a first voltage from the first voltage or a second voltage from the second voltage source based on or in response to an output of the inverter.

Abstract: A multi-function display system is configured to allow customization of inputs, outputs, and a display to an aircraft or other vehicle. The multi-function display provides custom outputs and a custom display by utilizing a configuration file, while maintaining the initial certification basis of the product hardware and software. The multi-function display is configured to receive a configuration file from a user via the communications element, wherein the configuration file includes information that defines the custom outputs; receive, during flight mode and from a sensor, a first parameter; access, during flight mode, the configuration file; perform, during flight mode, a data function on the first parameter; calculate, during flight mode, an output function based upon the data function and the configuration file; and provide, during flight mode, the output on the display or to another computing device.

Abstract: In general, one or more loads on a vehicle can be connected to both a first voltage source on the vehicle and a backup vehicle power system on the vehicle. If the voltage provided by the first voltage source to the one or more loads satisfies a voltage threshold, the backup vehicle power system does not provide power to the one or more loads. However, if the voltage provided by the first voltage source to the one or more loads falls below the voltage threshold, the backup vehicle power system provides power to the one or more loads.

Abstract: A storage system may maintain a purge counter for one or more logical storage units. When an instruction is received to perform an operation that will modify data across the one or more logical storage units, the purge counter may be incremented. One or more host systems implementing host caching may periodically poll the storage system to determine the purge counter value. When the current value of the purge counter value is different than a previously polled purge counter value recorded on a host system, the host system may purge from its host cache any entries for logical storage units associated with the purge counter. The data storage system may not execute the data modification instruction until it receives acknowledgement from all host systems caching data affected by the modification instruction that the host system has purged any host cache entries corresponding to the LSUs affected by the modification operation.

Abstract: Systems and methods presented herein provide for improved duplex communications in an RF cable network comprising a plurality of CMs. In one embodiment, a system includes a CMTS operable to transmit downstream communications to the CMs and to process upstream communications from the CMs. The system also includes a duplex RF communication path between the CMTS and the CMs. The CMTS is further operable to transmit a control signal that directs a first of the CMs to transmit, to direct the remaining CMs to receive the transmission from the first CM, to direct the CMs to report received power levels of the transmission from the first CM, and to calculate RF isolations of the remaining CMs with respect to the first CM based on the reported power levels.

Abstract: A method includes detecting a change to one or more of: a credential of set of storage units supporting a logical storage vault and access control information for a user group affiliated with the logical storage vault. The method further includes, in response to the detecting, determining, whether the logical storage vault is in a relationship with another logical storage vault. When the logical storage vault is in the relationship, determining whether the logical storage vault is an originating vault or a subservient vault. When the logical storage vault is the originating vault, sending updated access control information to the second set of storage units regarding a change to the access control information. When the logical storage vault is the subservient vault, sending an updated credential of the set of storage units to the computing device regarding a change to the credential of the set of storage units.

Abstract: A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive.

Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.

Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.

Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.

Abstract: Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.

Abstract: Data storage system power shedding for vaulting and/or backup is provided herein. A data storage system can include a processor that executes computer-executable components, at least one memory, and a basic input/output system device that stores respective ones of the computer-executable components executed by the processor. The computer-executable components comprise a power monitor component that monitors an input alternating current power level of the data storage system, a processor management component that causes the processor to transition from a multiple-core operating mode to a single-core operating mode in response to an indication from the power monitor component that the input AC power level has decreased below a threshold, and a backup component that initiates a transfer of data stored by the at least one memory to at least one backup storage device in response to the processor being configured to operate in the single-core operating mode.

Abstract: A motorcycle (1) including: an electronic system of authorization control (100,200); wherein: a first electronic control unit (200) is adapted and configured to determine whether the motorcycle (1) is in an authorized or non-authorized usage state and is adapted to interrogate a portable transponder, which can have a master identification electronic code or a slave identification electronic code, in order to acquire said electronic code and to verify if said electronic code is correct; and wherein: if the first control unit (200) acquires the master identification electronic code, starting the traction engine is allowed independently from the second electronic control unit; if the first control unit (200) acquires the slave identification electronic code, it is determined that the motorcycle (1) is in the authorized usage state and starting the traction engine is allowed if it receives consent information from the second electronic control unit (100).

Abstract: Systems, methods, and/or devices are used to manage open blocks within non-volatile storage devices, in order to improve the reliability of non-volatile storage devices. In some embodiments, when a shut-down request is received from a host device, the storage device fetches information about open blocks and their boundary regions susceptible to data reliability issues, and for each identified boundary region, the storage device programs a region contiguous to the identified boundary region. In some embodiments, the device updates an XOR parity table used for XOR parity management with the information that the region contiguous to the identified boundary is programmed. Subsequently, in some embodiments, the storage device can use the information, stored in the contiguous region and/or the XOR parity table, for data recovery in the event of a data loss. As a result, the reliability of the non-volatile storage device is improved.

Abstract: An information handling system may implement techniques for triggering power loss protection on solid-state storage devices (SSDs) based on PSU pre-warning signals (such as de-asserted POK or VIN_GOOD signals) indicating that power loss is imminent. The pre-warning signals may be provided directly to SSDs over a dedicated connection or may be passed through other components of the information handling system (such as power loss warning logic, a platform controller hub, or a CPU) to a storage controller. The pre-warning signal may be provided to the storage controller as a power loss warning interrupt. This interrupt may cause the storage system controller to issue an in-band message/command to the SSDs or to provide a signal on a dedicated connection to the SSDs in order to trigger power loss protection actions on the SSDs, including switching their power sources and flushing write queues before available hold-up energy is depleted.

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract: An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

Abstract: A computer system includes a front end interface configured for data communications over a network with data producer terminals, multiple distributed data processors coupled to the front end interface by a data messaging infrastructure, the multiple distributed data processors including a first distributed data processor and a second distributed data processor, and an information bus coupled to the multiple distributed data processors and to multiple independent consumer modules. The first processor receives and processes data order messages for the first security, and maintains a first order book that stores outstanding orders for the first security. The second processor receives and processes received data order messages for the second security, and maintains a second order book that stores outstanding orders for the second security.

Abstract: Methods and apparatus to recover a processor state during a system failure or security event are disclosed. An example apparatus to recover data includes a processor including a local memory and a system monitor in communication with the processor. The system monitor is to copy processor backup data to a non-volatile memory in response to a processor backup event. The processor backup data includes contents of the local memory.

Abstract: Sleep modes use non-volatile dual inline memory modules (NVDIMMs) to reduce electrical power and execution times. An S3 suspend-to-RAM, for example, may store a system state to NVDIMM via a high-speed memory bus. Likewise, an S4 suspend-to-disk may store a restoration file to the NVDIMM via the high-speed memory bus. When a server or other information handling system is then awakened, execution resumes in less time due to the NVDIMM.

Abstract: A mobile device having parallel use of non-volatile memory and main memory is presented. The mobile device includes a volatile memory, a non-volatile memory, a memory controller functionally coupled to the non-volatile memory and the volatile memory, and a processor coupled to the memory controller. The processor addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map. Alternatively, a mobile device may include a volatile memory, a non-volatile memory, a memory controller coupled to the volatile memory, a processor coupled to the memory controller. The processor may address the volatile memory during normal operation. The mobile device may further include a shadow copy controller coupled to the non-volatile memory and the memory controller, where the shadow copy controller copies information stored in a designated portion of the volatile memory into the non-volatile memory.

Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.

Abstract: Embodiments of recovering data in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving a failure notification indicating that a core of a main processor is experiencing a catastrophic failure causing the core unable to execute instructions. In response, a flush command can be issued to an uncore of the processor via a debug port instructing the uncore to copy any data currently residing in a processor cache of the main processor to a volatile memory. The method further includes issuing a self-refresh command causing the volatile memory to enter a self-refresh mode in which the data copied from the processor cache is maintained and unmodifiable by the main processor during a reset of the main processor.

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

Abstract: A system enables personal information manager (PIM) applications to continue to provide alerts and other time sensitive information even when the system upon which the PIM is stored is turned off. Automatically data may be transferred from a first processor-based system to a second processor-based system to implement time sensitive activities. The second processor-based system may provide a user notification at a predetermined time preset on the first processor-based system.

Abstract: Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.

Abstract: An example computer-implemented method for performing efficient patrol read operations in a storage system including a plurality of disks organized in a RAID array can include determining an I/O load on the storage system, identifying at least one portion of an available storage capacity containing valid data and reading the portion of the available storage capacity containing the valid data. Optionally, the portion of the available storage capacity containing the valid data is the only portion read during the patrol read operations. The method can also include determining whether a medium error exists in the portion of the available storage capacity containing the valid data. If a medium error exists, the method can include fixing the medium error. Additionally, the above operations can optionally be performed only when the I/O load on the storage system is less than a predetermined threshold.

Abstract: Provided are RFID systems, methods and RFID tags according to various aspects. An infrared (IR) beam, from an IR transmitter, is outputted in a first direction so that an RFID tag with an IR sensor adds a flag to stored data in the RFID tag in response to the RFID tag's IR sensor detecting the IR beam. An RF interrogation signal is outputted by an RFID reader, and a response is received from the RFID tag to the RF interrogation signal. It is determined whether the flag is contained in the RFID tag's response to the RF interrogation signal, and if so, the RFID tag is determined to be in the first direction relative to the IR transmitter.

Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

Abstract: Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the host data buffer that had been storing the subset identified in the message rather than waiting to release data associated with the host write command until all the data associated with the command is stored in the memory. The memory in which each subset is stored may be non-volatile memory in the storage device or a shadow buffer on the host or an external memory device.

Abstract: A control apparatus includes a first control unit, a second control unit including a memory for storing information for performing startup processing, and a power supply unit configured to supply electric power to the first control unit and the second control unit, and in a case where electric power is supplied from the power supply unit to the second control unit, whether a startup state of the second control unit is normal is determined. In a case where the startup state of the second control unit is determined to be normal, the power supply unit supplies electric power to the first control unit. In a case where the startup state of the second control unit is determined to be not normal, to power supply to the memory from a backup power supply for the memory is stopped so as to clear the memory of the second control unit.

Abstract: A Data Storage Device (DSD) includes a disk for storing data, a volatile memory for temporarily storing data to be written on the disk, and a Non-Volatile Solid-State Memory (NVSM) for storing data. Data is stored in the volatile memory in preparation for writing the data on the disk. The data is written from the volatile memory onto the disk, and it is determined whether the data written on the disk is qualified as written. In the event of an unexpected power loss, a portion of unqualified data that has not been qualified as written is transferred from the volatile memory to the NVSM.

Abstract: A data storage device includes a controller configured to control data to be written in a first page; and a nonvolatile memory device configured to perform a write operation for writing the data, according to whether the first page is written or not, wherein the nonvolatile memory device provides a state information including an overwrite information meaning whether the write operation has caused an overwrite, to the controller.

Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stored in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the second channel.

Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.

Abstract: Maintaining failure survivability in a storage system includes determining a save time corresponding to an amount of time needed to transfer system data from volatile memory to non-volatile memory, determining a threshold corresponding to time for batteries to run while transferring data from volatile memory to non-volatile memory after a power loss, and providing an indication in response to the save time being greater than the threshold. The system may include a plurality of directors and the save time and the threshold may be determined for each of the directors. Determining a threshold may include determining an amount of battery time provided by battery power following power loss and multiplying the amount of battery time by a factor less than one, such as 0.8.

Abstract: A high security microcontroller (such as in a point of sale terminal) includes tamper control circuitry for detecting vulnerability conditions: a write to program memory before the sensitive financial information has been erased, a tamper detect condition, the enabling of a debugger, a power-up condition, an illegal temperature condition, an illegal supply voltage condition, an oscillator fail condition, and a battery removal condition. If the tamper control circuitry detects a vulnerability condition, then the memory where the sensitive financial information could be stored is erased before boot loader operation or debugger operation can be enabled. Upon power-up if a valid image is detected in program memory, then the boot loader is not executed and secure memory is not erased but rather the image is executed. The tamper control circuitry is a hardware state machine that is outside control of user-loaded software and is outside control of the debugger.