Abstract: RFID tag ICs employ tunneling-voltage profile calibration during IC manufacturing to determine and store, typically in nonvolatile memory, a tunneling-voltage profile for writing data to the IC's nonvolatile memory. The IC may subsequently read the profile at power-up, prior to writing the memory, or at other times as determined by the IC or by an interrogating reader. By using the stored profile when writing to the nonvolatile memory the IC may reduce nonvolatile memory write time and oxide stress.

Abstract: Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device (200) that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit (230) to delay a drop in voltage of an input/output line, a power shutdown sensor (210) to sense power shutdown of a system, and a controller (220) to control the signal delay unit in response to whether the system is shut down.

Abstract: This disclosure describes techniques for using a non-volatile-memory device such as flash memory to store memory data during hibernation or suspend. By so doing, hard drives and/or data are safer, and less power may be used.

Abstract: To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that prohibits a refresh operation of the memory bank or the segment not designated by at least one of the bank address register and the segment address register. This semiconductor device is capable of designating whether to perform a refresh operation not only in a memory bank unit but also in a segment unit within the memory bank, and thus it achieves a further reduction of the power consumption.

Abstract: A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls below a predetermined value. And a circuit responsive to the voltage fault signal maintains the FRAM operating voltage above a voltage required to assure data integrity of the FRAM for a sufficient time required to perform an FRAM read operation.

Abstract: A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

Abstract: The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract: A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.

Abstract: A storage device includes a volatile memory, an auxiliary power source, a nonvolatile memory, a write module, and an inhibition module. The volatile memory stores user data. The auxiliary power source supplies power to the volatile memory when power from a main power source is cut off. The nonvolatile memory is written with the user data, write incomplete information indicating the user data, and power off information indicating that power from the main power source is cut off. While supplied with power from the auxiliary power source when power from the main power source is cut off, the write module writes the write incomplete information, the user data, and the power off information to the nonvolatile memory. The inhibition module inhibits reading of the user data if the power off information is not written in the nonvolatile memory when the volatile memory is supplied with power.

Abstract: Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device.

Abstract: An integrated circuit employing a percolation tamper protection device includes a circuit housing with a die disposed in circuit housing. The die includes a volatile memory. A percolation tamper protection device that is connected to the volatile memory and also disposed in the circuit housing. The percolation tamper protection device includes a percolation gate which is biased in a conductive state. The percolation gate includes a first terminal that is connected to the volatile memory and a second terminal configured to be connected to a power supply. The percolation gate has a conductivity that varies proportional to pressure.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.

Abstract: An apparatus, system, and method are disclosed for power reduction management. The method includes determining that a power source has failed to supply electric power above a predefined threshold. The method includes terminating one or more non-essential in-process operations on a nonvolatile memory device during a power hold-up time. The method includes executing one or more essential in-process operations on the nonvolatile memory device within the power hold-up time.

Abstract: A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied to an external interface of the non-volatile memory module through an isolation circuit. A control circuit coupled to the isolation interface and to a circuit which is adapted to detect when the non-volatile memory module no longer draws power from an external source.

Abstract: A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits.

Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

Abstract: An integrated circuit and method includes retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage. Functional circuitry is connected between the retention voltage node and a reference voltage node and is held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node. Each of the circuits includes at least one p-type threshold device and at least one n-type threshold device, both having a characteristic threshold voltage. The p-type and n-type threshold devices are connected in parallel between the supply voltage node and the retention voltage node. A variation in the characteristic threshold voltage of either of the at least one p-type or the at least one n-type device maintains at least the minimum voltage between the retention voltage node and the reference voltage node.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.

Abstract: A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit controls the standby mode of the charge pump circuit using the time value.

Abstract: A dynamic memory module is fitted with a tamper detection circuit and a memory clear circuit responsive to a detected tampering signal for clearing the memory. A power retention circuit powers the memory, the tamper detection circuit, and the clearing circuit in the event that the main power fails. Failure of the main power or a System Reset may also initiate memory clearing.

Abstract: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros.

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.

Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.

Abstract: A memory power supply circuit includes a memory module, a micro control unit (MCU), a phase switch circuit, and a multi-phase pulse-width modulation (PWM) controller. The MCU is operable to determine required current to be supplied to the memory module and output corresponding phase switch signals to the phase switch circuit. The PWM controller includes a number of phase pins connected to the phase switch circuit. The phase switch circuit controls enable states of the phase pins of the PWM controller.

Abstract: An apparatus, system, and method are disclosed for power loss management in a nonvolatile data storage device. A monitor module initiates a power loss mode in the nonvolatile data storage device in response to a primary power source failing to supply electric power above a predefined threshold to the nonvolatile data storage device. A secondary power source supplies electric power to the nonvolatile data storage device for at least a power hold-up time during the power loss mode. A power loss module adjusts execution of in-process operations on the nonvolatile data storage device during the power loss mode so that essential in-process operations execute within the power hold-up time.

Abstract: A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage.

Abstract: A multi-port memory is operated according to a method. Data is written, in a first mode, to a storage node of a memory cell from a first port through a first conductance. The first mode is characterized by a power supply voltage being applied at a power node at a first level. Data is written, in a second mode, to the storage node of the memory cell simultaneously from the first port through the first conductance and a second port through a second conductance. The second mode is characterized by the power supply voltage being applied at the power node at a second level different from the first level.

Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.

Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: A system, method, and computer program product are provided for driving a memory circuit. In one embodiment, the memory circuit is driven utilizing a first resistance value in a first mode of operation. Further, in a second mode of operation, the memory circuit is driven utilizing a second resistance value. In another embodiment, a device is provided for driving a memory circuit without active termination utilizing a resistor.

Abstract: A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.

Abstract: There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

Abstract: Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The time interval during which the refresh device can be subsequently maintained in the refresh mode is next determined in relation to an energy requirement value obtained during the self-refresh mode and an energy capacity value from the associated energy source. The energy capacity value is preferably obtained by fully discharging the associated energy source. Preferably, the refresh device is characterized as a dynamic random access memory (DRAM), and the associated energy source is characterized as a rechargeable backup battery. A selected test pattern is preferably written to the refresh device and maintained thereby during the self-refresh mode.