Abstract: A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.

Abstract: Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions.

Abstract: RFID tag circuits, tags, and methods are provided for using alternative memory lock bits. A pointer in tag memory is configured to point to one or the other of the alternative lock bits associated with a section of the memory for performing a function in response to a reader command. Upon receiving the reader command, the tag first checks the pointer and performs the function based on which lock bit(s) is selected.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Abstract: A system and method for implementing a “lossless” transition from an idle state to an active or awake state in a mobile station. When a mobile station informs a serving base transceiver station that it is switching to an idle state, a virtual handover is executed, with the mobile station receiving a new Care of Address (CoA). The CoA is taken from an address space that is solely reserved for idle mobile station in a particular access network. The CoA is used to store data packets that are to be transmitted to the mobile station. Once the mobile station reenters an active state, the buffered packets can be forwarded to the mobile station without packet loss.

Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage device such as a capacitive storage circuit is powered relative to the powering of one or more additional circuits from a common power supply to limit the draw upon the power supply. Certain applications involve delaying or otherwise modifying the powering of the capacitive storage circuit, which may involve an initial startup of the capacitive storage circuit.

Abstract: An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode.

Abstract: A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount of incorrect data stored in the volatile memory after a period of time during which the device was without power. The amount of incorrect data is used to determine the period of time during which the device was without power. A method of controlling a device based on the amount of incorrect data stored in a volatile memory after the device was without power is also disclosed. For example, the device can be controlled by altering a start-up sequence of one or more elements of the device.

Abstract: In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of the power input terminal. When the power voltage of the power input terminal is charged/discharged to the common voltage, the power low signal SRC_LOSS outputted from the data latch may be changed from the logical high voltage to the logical low voltage or from the original logical low voltage to the logical high voltage. Since the mention above is design of selectiveness, the detailed description is omitted. When the determination is positive, the step S509 is performed. When the determination is negative, the step S511 is performed to re-detect.

Abstract: A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: An electronic device is capable of monitoring internal components to predict changes in processing power needs. When a prediction is made, a clock control circuit can be instructed to increase the clock signal frequency in response to a predicted increase in processing power needs, or decrease the clock signal frequency in response to a predicted decrease in processing power needs. The control circuit can further balance other clock signal frequencies in order to satisfy constraints such as a power supply constraint.

Abstract: A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in case where the cell power supply voltage in supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation.

Abstract: A system, method, and computer program product are provided for hardening data stored on a solid state disk. In operation, it is determined whether a solid state disk is to be powered off. Furthermore, data stored on the solid state disk is hardened if it is determined that the solid state disk is to be powered off.

Abstract: A system, method, and computer program product are provided for converting logical block address de-allocation information in a first format to a second format. In use, logical block address de-allocation information is received in a first format associated with a first protocol. Additionally, the logical block address de-allocation information in the first format is converted to a second format associated with a second protocol.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured to selectively power a first subset of the plurality of memory cells at the normal-operation voltage during operation of the host apparatus while concurrently powering a second subset of the plurality of memory cells at the power-saving voltage. The first and second subsets being different subsets of the memory cells.

Abstract: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.

Abstract: A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.

Abstract: A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.

Abstract: A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to the NAND-type flash memory includes a dynamic random access memory and an internal power. The memory controller is used for controlling at least one of both the NAND-type flash memory and the dynamic random access memory unit. When the memory module is disconnected with the external electronic device, the internal power of the dynamic random access memory unit powers the dynamic random access memory, actively. Accordingly, data stored in the dynamic random access memory will be retained.

Abstract: A method, system, and computer program product for safeguarding nonvolatile storage (NVS) data by a processor in communication with a memory device following a power loss event is provided. A first portion of the NVS data is encrypted using a first buffer module. Subsequently the first portion of the NVS data is transferred to at least one shared storage device, while a second portion of the NVS data is simultaneously encrypted using a second buffer module. The second portion of the NVS data is subsequently transferred to the at least one shared storage device.

Abstract: A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, including: a capacitor bank with an output terminal; a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank.

Abstract: A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.

Abstract: A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, each of which is for communicating through a different corresponding one of the plurality of ports with any non-volatile memory connected to that port; a controller that is programmed to activate a selectable set of the plurality of interfaces depending on which ports are to receive non-volatile memory chips, wherein said controller is also programmed to react to a loss of power from the primary power source by moving data from the volatile memory through the selected interfaces to whatever non-volatile memory is connected to the selectable set of interfaces.

Abstract: A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Abstract: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.

Abstract: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

Abstract: A semiconductor memory device is capable of maintaining a predetermined back-bias voltage level regardless of operation modes of the semiconductor memory device, by generating a back-bias voltage with driving force changed according to the operation modes. The semiconductor memory device includes an active pumping control signal generating unit for generating an active pumping control signal in response to a plurality of active signals, a voltage detecting unit for detecting a voltage level of a back-bias voltage terminal to output a detection signal, an oscillator for generating an oscillation signal oscillating at a predetermined frequency in response to the detection signal, and a charge pumping unit for performing a charge pumping operation in response to the oscillation signal by controlling a force of driving the back-bias voltage terminal in response to the active pumping control signal.

Abstract: A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

Abstract: A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal.

Abstract: A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.

Abstract: A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines.

Abstract: A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.

Abstract: A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.

Abstract: A storage subsystem includes a charge pump that receives a power signal from a host system, and generates a regulated power signal that is provided to the storage subsystem's controller. When the power signal from the host is interrupted, the charge pump additionally acts as a backup power supply to enable the storage subsystem to continue to operate temporarily, and power isolation circuitry in the storage subsystem prevents power from flowing back to the host system. The storage subsystem further includes a digitally programmable voltage detection circuit that accepts various supply voltages and asserts a busy signal to the controller when an anomaly in the power signal is detected. The controller includes logic circuitry that will block the host system from performing write operations to the storage subsystem either when the voltage detection circuit asserts a busy signal or when the controller is busy executing memory operation commands.

Abstract: A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply voltage of the data holding circuit to the specified voltage or greater, regardless of the data state that is stored beforehand in the data holding circuit.

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.