Abstract: A method of controlling volatile memory (VM) and VM controller operatively connectable to VM. The method includes: intercepting reset signal intended to cause reset of, at least, VM; assessing transfer-related (TR) state related to the VM; blocking the intercepted reset signal from reaching VM if the assessed TR state does not meet predefined criterion, and transferring the reset signal to VM if the assessed TR state meets the predefined criterion. The VM controller is configured to: receive a reset signal originating in computer system and intended to cause reset of, at least, the VM; detect if the VM has been powered-up during a predetermined timeframe prior to the receipt of the reset signal; and block the received reset signal from reaching the VM if the VM powering-up has not been detected and transfer the reset signal to the VM if the VM powering-up has been detected.

Abstract: A memory device comprising a memory controller and a homogeneous memory accessible by the memory controller, wherein the homogeneous memory is divided by the memory controller in a first memory partition and a second memory partition, wherein the first memory partition is allocated to a first type of information comprising user data and ECC data that are arranged interleaved with the user data, and wherein the second memory partition is allocated to a second type of information comprising further user data.

Abstract: A memory module includes an emergency power supply block, a volatile memory, a nonvolatile memory, and a control block configured to control data of the volatile memory to be backed up in the nonvolatile memory, by using a power supplied from the emergency power supply block, upon a power failure, and control the data of the volatile memory to be recovered, by using data backed up in the nonvolatile memory, upon a power recovery, wherein the control block controls the data of the volatile memory not to be backed up while controlling the data of the volatile memory to be recovered, even upon the power failure.

Abstract: An infusion pump assembly includes a reservoir assembly configured to contain an infusible fluid. A motor assembly is configured to act upon the reservoir assembly and dispense at least a portion of the infusible fluid contained within the reservoir assembly. Processing logic is configured to control the motor assembly. A primary power supply is configured to provide primary electrical energy to at least a portion of the processing logic. A backup power supply is configured to provide backup electrical energy to the at least a portion of the processing logic in the event that the primary power supply fails to provide the primary electrical energy to the at least a portion of the processing logic.

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.

Abstract: A vehicle mount computer having a configurable behavior controlled by a vehicle's ignition switch. A user can configure the computer to perform an action, switch modes, or execute a software application in response to the ignition switch being pressed or the position of the ignition switch being adjusted. For example, the computer can be configured to switch to a standby mode or hibernation mode, shutdown, prompt the user to select an action, or do nothing in response to the ignition switch being placed in an off position. The ignition switch can be electrically coupled to an input of the computer so that the computer's operating system or another application can monitor the status of the ignition switch. The operating system or application can cause the computer to perform the configured response upon detecting a change in the ignition switch's position or an actuation of the ignition switch.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: The present invention provides a volatile memory backup system including an all-solid-state battery. The backup system includes a volatile memory, a nonvolatile memory connected to the volatile memory so as to transfer data therebetween, an all-solid-state battery connected to the volatile memory and the nonvolatile memory, the battery continuously or intermittently supplying a current to the volatile memory during a power failure to retain data in the volatile memory, and a controller connected in parallel with the battery, the controller intermittently supplying a peak current to the volatile memory during the power failure and intermittently transferring divided volumes of data in the volatile memory to the nonvolatile memory by the peak current and a current from the battery temporarily increased in association with the peak current to store the data in the nonvolatile memory, thereby gradually accumulating the data in the volatile memory into the nonvolatile memory.

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract: A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract: A data storage device (DSD) includes a power supply from a host and a charge storage element. A current transient is detected on the power supply from the host and it is determined whether the current transient exceeds a current threshold. When the current transient exceeds the current threshold, power is drawn from the charge storage element to reduce power drawn from the host.

Abstract: A microprocessor reset control operates in one of two reset states and transitions from the first state to the second state when a first signal falls below a first threshold and from the second state to the first state when a second signal exceeds a second threshold.

Abstract: When a communication control unit (14) in this charging control device (1) receives an inhibition command sent by a power monitoring device (2), the communication control unit instructs a signal processing unit (10) to lower a current capacity (an upper limit for a charging current). The signal processing unit (10) reduces the duty ratio of a pilot signal. As a result, the charging power supplied to an electric vehicle (200) decreases, thus making it possible to prevent the supplied power from exceeding a contract demand and minimize problems stemming from the charging of a rechargeable battery.

Abstract: On-die variability noise or other variations in the power supply voltage to a storage circuit may cause the ability to perform memory access operations to be marginal. A control circuit may be coupled to the storage circuit and the power distribution network and monitor the actual power supply voltage. The control circuit may include a reference voltage generator that generates a nominal voltage. The control circuit may further include a comparator that generates a status signal based on a comparison between the actual power supply voltage and a nominal voltage. Based on the status signal, the control circuit may control memory access operations performed by the storage circuit. For example, the control circuit may enable and disable the execution of read and write operations on the storage circuit. If desired, the control circuit may also control the operation of predetermined portions of the integrated circuit.

Abstract: A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes first memory blocks configured to store m-bit data per cell and second memory blocks configured to store n-bit data per cell. The memory controller is configured to control the nonvolatile memory device to close an open word line generated in a second memory block of the second memory blocks when a program operation is performed on the second memory block.

Abstract: Methods and systems for providing lime information in intermittently powered devices that are batteryless and operate purely on harvested energy (also referred to as zero power devices). The method of these teachings for improving security of zero power devices includes determining an estimate of time using a decay of data in a volatile device, and deciding whether to respond to a query based on the estimate of time.

Abstract: Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. The charge controller controls an amount of electric charges on a first node to output a drive signal through the first node. The delay unit includes a capacitor coupled to the first node and retards the drive signal to generate an output signal. A delay time of the drive signal is controlled according to an amount of electric charges of the first node. The discharger discharges the electric charges of the first node when the amount of electric charges of the first node is equal to a predetermined value.

Abstract: The semiconductor device includes a control signal driver, a control signal latch unit, an internal driver and a buffer. The control signal driver drives a control signal in response to a fuse reset signal, a fuse set signal and a fuse data. The control signal latch unit is suitable for latching the control signal. The internal driver drives an internal node in response to the control signal, an address signal and a write strobe signal. The buffer buffers a signal of the internal node to generate the redundancy signal.

Abstract: A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.

Abstract: A data saving period control circuit; a power gating control circuit; and a data processing circuit including a general-purpose register, an error correction code storage register, and an error correction code circuit are included. The general-purpose register and the error correction code storage register each include a volatile memory unit and a nonvolatile memory unit. The data saving period control circuit is a circuit for changing a length of a data saving period in which data output from the power gating control circuit is saved from the volatile memory unit to the nonvolatile memory unit included in the general-purpose register, depending on whether an error in an error correction code stored in the error correction code storage register is detected by the error correction code circuit.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises an internal circuit coupled between a power line and ground and an output buffer coupled to the internal circuit; wherein the output buffer provides an output signal. The ASIC includes a fault detection circuit coupled between the power line and ground; and a first protection block configured to receive a first control signal from the fault detection circuit. The first switch is coupled to the power line, the output buffer and the internal circuit. The first protection block prevents current from flowing between the power line and ground when a fault condition is detected. The ASIC further includes a second protection block configured to receive a second control signal from the fault detection circuit, wherein the second protection block is coupled to the output signal, the power line and ground.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event.

Abstract: A self powered memory system is disclosed. The system includes a volatile supply component, a battery component, a switch component, and a volatile memory component. The volatile supply component is configured to provide a time varying supply. The battery component is configured to generate a non-volatile supply. The switch component is configured to generate a persistent supply from the time varying supply and the non-volatile supply. The volatile memory component is configured to maintain data by using the persistent supply.

Abstract: A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

Abstract: The semiconductor device includes a power source signal generator and a redundancy signal generator. The power source signal generator generates a fuse power source signal driven to have a target level of an internal voltage signal. The fuse power source signal is generated to have a lower level than the target level of the internal voltage signal by a certain level during a period from a moment that a deep power-down mode starts till a moment that a level of the internal voltage signal reaches a predetermined level after termination of the deep power-down mode. The redundancy signal generator latches a fuse data in response to a fuse reset signal and a fuse set signal to generate a redundancy signal while the fuse power source signal is supplied.

Abstract: Method and system are provided for handling data when power failure from a primary power source of a storage system is detected. The system provides a first memory and a second memory. The first memory is primarily used to store data when the primary power source is operating. If a power failure is detected, a first indicator is set to indicate that data is stored or being transferred to the second memory. Thereafter, data is transferred from the first memory to the second memory. Any errors during the transfer are logged. Once power is restored, data is transferred back to the first memory. A second indicator is set to indicate that there is no data at the second memory.

Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP?VddM>VddMlower.

Abstract: A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with a time at which a power-down mode is ended, and discharge charges of a first node from which the bulk voltage is outputted, in response to the exit signal; and an internal circuit including a MOS transistor which is supplied with the bulk voltage.

Abstract: A data storage device includes a non-volatile memory. A method includes programming a first page at a word line of the non-volatile memory. While programming a second page at the word line, first storage elements of the word line are selectively programmed in response to a power drop at the data storage device to increase a state separation that separates data values of the first page.

Abstract: The semiconductor device includes a fuse data storage unit, a power source signal generator and a redundancy signal generator. The fuse data storage unit generates a section signal, a fuse clock signal, a fuse reset signal and a fuse data in response to a first power-up signal generated from a power supply voltage signal. The redundancy signal generator generates a fuse set signal that is counted in response to the fuse clock signal, generates an input reset signal and an input set signal from the fuse set signal and the fuse reset signal in response to the section signal, and latches the fuse data in response to the input reset signal and the input set signal to generate a redundancy signal.

Abstract: An information processing apparatus capable of suppressing a secondary battery from being charged with an amount of charge current that can apply excessive load on the secondary battery, without a backup power source function of the secondary battery being impaired. When determining that a predetermined type of data is stored in a DRAM to be backed up by the secondary battery, the information processing apparatus selects a first constant current circuit and quickly charges the secondary battery with a large charge current output from the first constant current circuit. When determining that the predetermined type of data is not stored in the DRAM, the information processing apparatus selects a second constant current circuit and normally charges the secondary battery with a small charge current output from the second constant current circuit.

Abstract: A user system is provided which includes a storage device and an auxiliary power device configured to supply a power to the storage device, wherein the auxiliary power device includes a first one direction device configured to supply a supply voltage from an external power supply to the storage device, a charging unit configured to be charged by the external power supply, a second one direction device configured to selectively supply an output voltage of the charging unit to the storage device, a voltage detector configured to detect a level of the output voltage of the charging unit and to output a first control signal to the storage device, and a switching unit connected between the charging unit and the second one direction device and configured to operate in response to a second control signal from the storage device.

Abstract: Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit.

Abstract: Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

Abstract: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Abstract: In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is determined that a write-back cycle or a write cycle will occur in the ferroelectric memory, the power supply is electrically disconnected from the ferroelectric memory before a write-back cycle or a write cycle occurs. Energy during the write-back cycle or the write cycle is provided to the ferroelectric memory by one or more capacitors in this embodiment. After the write-back cycle or the write cycle has ended, the power supply is electrically connected to the ferroelectric memory and the capacitors.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements.

Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.

Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising: a first supply voltage distribution line arrangement and a second supply voltage distribution line arrangement, said first supply voltage distribution line arrangement and said second supply voltage distribution line arrangement being adapted to receive from outside the semiconductor device a semiconductor device supply voltage and to distribute a supply voltage to respective first and second portions of the semiconductor device; and a voltage-to-voltage conversion circuit connected to the first supply voltage distribution line arrangement, wherein the voltage-to-voltage conversion circuit is adapted to either transfer onto the first supply voltage distribution line arrangement the semiconductor device supply voltage received from outside the semiconductor device, or to put on the first supply voltage distribution line a converted supply voltage having a