Abstract: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: An apparatus for securely protecting data in a flash memory upon power off is disclosed. In the apparatus, a power detector monitors a voltage output from a power supply unit, and outputs a power fail signal when the voltage drops by a predetermined reference voltage or more. A Programmable Logic Device (PLD) outputs a Write Protect (WP) signal for performing write protection on the flash memory upon receiving the power fail signal from the power detector. A WP controller outputs the WP signal output from the PLD to the flash memory, according to a Ready/Busy (R/B) state of the flash memory.

Abstract: A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.

Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.

Abstract: A memory array including at least one cross-latched pair of transistors for storing data. The memory array further includes a first power line for supplying a first reference voltage and a second power line for supplying a second reference voltage. The memory array further includes a first switch having a first output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the first power line. The memory array further includes a second switch having a second output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the second power line. The first output is coupled to the second output.

Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

Abstract: A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode.

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract: A voltage regulator circuit for providing power management for a memory device is disclosed. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device.

Abstract: Devices, systems, and methods are disclosed which relate to devices utilizing time-sensitive memory storage. The time-sensitive memory storage acts as normal device memory, allowing the user of the device to store files or other data to it; however the information stored on the time-sensitive memory storage is automatically erased, based on some storage time period. A limited amount of persistent storage is used for names and message headers.

Abstract: A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”).

Abstract: A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.

Abstract: Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First logic circuit is disposed between first sub power supply line and second power supply line and comprises first input node and second input node receiving second signal and third signal respectively, and output node. First logic circuit outputs an active voltage associated with a logical level of second signal to output node in active state, and outputs a standby voltage associated with a voltage of second power supply line to output node regardless of the logical level of second signal in non-active state.

Abstract: Multi-channel semiconductor integrated circuit devices are provided including a plurality of memory devices that are independently accessible, each of the plurality of memory devices including at least one power generation unit and a control unit for controlling an operation of the at least one power generation unit, a detection unit for detecting an operation state of the plurality of memory devices, and a common control unit for commonly controlling an operation of the at least one power generation unit of the plurality of memory devices, according to the operation state of the plurality of memory devices detected by the detection unit. The control unit of each of the plurality of memory devices controls the operation of the at least one power generation unit of a corresponding one of the plurality of memory devices.

Abstract: A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.

Abstract: Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Abstract: A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.

Abstract: According to an embodiment, a semiconductor device includes a power supply switch and a first regulator. One end of the power supply switch is connected to an input terminal. The other end of the power supply switch is connected to an output terminal. The first regulator includes a power supply terminal connected to the one end of the power supply switch, and a voltage output terminal connected to the other end of the power supply switch. The first regulator is configured to control a voltage of the voltage output terminal to approach a target voltage based on a voltage of the power supply terminal. The target voltage is switched to a first voltage or a second voltage. The first voltage is equal to or more than the voltage of the power supply terminal. The second voltage is lower than the voltage of the power supply terminal.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.

Abstract: Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

Abstract: A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”).

Abstract: A secondary memory unit and a system including the same, the secondary memory unit including: a first substrate on which one or more non-volatile memory units to which power is supplied from an external device, are mounted; a second substrate on which one or more energy storage and supply mediums are mounted; and an energy transfer medium for electrically connecting the first substrate and the second substrate, wherein, when power from the external device to the one or more non-volatile memory units is cut off, the one or more energy storage and supply mediums are configured to supply power to the one or more non-volatile memory units. The secondary memory unit and the system including the same have high reliability and improved stability, and their product development and maintenance are convenient.

Abstract: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors.

Abstract: A memory device is provided comprising: a volatile memory device, a non-volatile memory device, a memory control circuit volatile memory controller coupled to the volatile memory device and non-volatile memory device, and a backup power source. The backup power source may be arranged to temporarily power the volatile memory devices and the memory control circuit upon a loss of power from the external power source. Additionally, a switch may serve to selectively couple: (a) a host memory bus to either the volatile memory device or non-volatile memory device; and (b) the volatile memory device to the non-volatile memory device. Upon reestablishment of power by an external power source from a power loss event, the memory control circuit is configured to restore data from the non-volatile memory device to the volatile memory device prior to a host system, to which the memory device is coupled, completes boot-up.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract: An electronic device includes a memory storage device, a storing unit, and a voltage increasing unit. The storing unit is used for receiving the supply voltage to store energy and releasing energy to generate an standby voltage when the power supply stops providing the supply voltage. The voltage increasing unit is used for receiving the standby voltage, increasing the standby voltage, and providing the increased standby voltage to the memory storage device for preventing data loss in the memory storage device. A related method for preventing data loss in a memory storage device and an electronic device assembly are also provided.

Abstract: RFID tag ICs employ tunneling-voltage profile calibration during IC manufacturing to determine and store, typically in nonvolatile memory, a tunneling-voltage profile for writing data to the IC's nonvolatile memory. The IC may subsequently read the profile at power-up, prior to writing the memory, or at other times as determined by the IC or by an interrogating reader. By using the stored profile when writing to the nonvolatile memory the IC may reduce nonvolatile memory write time and oxide stress.

Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

Abstract: To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that prohibits a refresh operation of the memory bank or the segment not designated by at least one of the bank address register and the segment address register. This semiconductor device is capable of designating whether to perform a refresh operation not only in a memory bank unit but also in a segment unit within the memory bank, and thus it achieves a further reduction of the power consumption.

Abstract: A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls below a predetermined value. And a circuit responsive to the voltage fault signal maintains the FRAM operating voltage above a voltage required to assure data integrity of the FRAM for a sufficient time required to perform an FRAM read operation.

Abstract: An image processing apparatus for eliminating the necessity of providing a first control board with a power supply unit beforehand for backing up data stored in an image memory, and reducing the cost of the apparatus as a whole. To accomplish this, in an image processing apparatus including a system control board configured to perform image processing, a memory backup function is enabled for an image memory storing data to be processed by the system control board, when a facsimile communication board is connected.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract: In a memory device, an array of memory cells is coupled between a virtual ground node and a supply node. First and second transistors are coupled in source-drain parallel between the virtual ground node and a ground bus. The first transistor is substantially larger than the second transistor. A control circuit provides a first gate signal to a gate of the first transistor and a second gate signal to a gate of the second transistor. The control circuit includes: a configuration memory cell providing a first control signal; an interconnect providing a second control signal; and control logic receiving the first and second control signals and providing the first gate signal. The array of memory cells has three modes responsive to the first and second gate signals, where the three modes include an active mode, a first sleep mode, and a second sleep mode.

Abstract: A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.

Abstract: An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.

Abstract: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a higher impedance than the second switch. When a wake up signal is received, the first switch may be turned on first and the second switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by a control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

Abstract: A Subscriber Identification Module (SIM) card for a portable wireless terminal is provided. The SIM card includes a SIM contact pad group which is exposed to an outer surface of the SIM card, and is electrically connected when the SIM card is placed in the portable terminal so as to identify subscriber information; a battery cell which is embedded in the SIM card, and is electrically connected when the SIM card is placed in the portable terminal so as to be used as an auxiliary power source; and a battery contact pad group which is electrically connected to the battery cell and is exposed to the outer surface of the SIM card; and a mode change element which is disposed to a lateral side of the SIM card and by which either an auxiliary battery function or a SIM function is selected by a user's manipulation.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A memory device includes a plurality of banks, a first generator generating standby current in response to a standby signal, and a switching circuit supplying the standby current to at least one of the plurality of banks in response to a plurality of active signals.

Abstract: Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The time interval during which the refresh device can be subsequently maintained in the refresh mode is next determined in relation to an energy requirement value obtained during the self-refresh mode and an energy capacity value from the associated energy source. The energy capacity value is preferably obtained by fully discharging the associated energy source. Preferably, the refresh device is characterized as a dynamic random access memory (DRAM), and the associated energy source is characterized as a rechargeable backup battery. A selected test pattern is preferably written to the refresh device and maintained thereby during the self-refresh mode.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.