Abstract: Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.

Abstract: A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders. Each of the row decoders receives a pre-charge signal, and includes an inverter, a selecting transistor and at least one switch transistors. The inverter receives the corresponding pre-charge signal, and outputs a first control signal. The first source/drain of the selecting transistor is coupled to a system high voltage, the gate receives the first control signal, and the second source/drain outputs a corresponding row selecting signal to a memory array of a memory device. The switch transistors are coupled between the second source/drain of the selecting transistor and a corresponding first reference signal in series. When the selecting transistor is controlled by the first control signal and turned on, the first reference signal is set to a high voltage level.

Abstract: An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed.

Abstract: There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Abstract: A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time.

Abstract: A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample.

Abstract: A semiconductor memory device includes a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal, a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group, the first switching group configured to transmit first operating voltages to the first memory block in response to a first block selection signal among the block selection signals, and a first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group.

Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.

Abstract: A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.

Abstract: A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors. Each of the even clamp transistors has a control terminal coupled to an even clamp line, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to a ground voltage. Each of the odd clamp transistors has a control terminal coupled to an odd clamp line, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to the ground voltage.

Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

Abstract: A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (SRAM) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (SRAM) column architecture; a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells.

Abstract: A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at first node; third and fourth transistors of second conductivity type coupled in series between first and second lines and coupled to each other at second node; power supply node coupled in common to first and second nodes; fifth transistor of first conductivity type coupled between first and second signal lines; and sixth transistor of second conductivity type coupled between first and second signal lines, wherein each of first, second and fifth transistors is configured to receive first control signal at gate electrode thereof, each of the third and fourth transistors is configured to receive second control signal at gate electrode thereof, and sixth transistor is configured to receive third control signal at gate electrode thereof.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract: A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.

Abstract: A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.

Abstract: A memory includes a plurality of word lines each coupled with at least one memory cell, an address storing unit that may store at least one target address corresponding to at least one of the word lines, and a control unit that may sequentially activate the plurality of word lines in response to a refresh command that is inputted at a set interval, and may activate the word line selected based on the target address whenever the refresh command is inputted a set number of times that is equal to or more than two times.

Abstract: A semiconductor apparatus having a data bit inversion function and, the semiconductor apparatus including a first semiconductor chip and a second semiconductor chip electrically coupled to the first semiconductor chip, wherein the first semiconductor chip may be configured to receive data and a data bit inversion flag, and transfer the data to the second semiconductor chip, and the second semiconductor chip may be configured to invert and store the data, which is transferred from the first semiconductor chip, according to to the data bit inversion flag.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.

Abstract: According to embodiments of the present invention, a memory device with soft decision decoding is provided. The memory device includes a memory cell configured to store an input data bit; a memory sensor configured to read out a parameter associated with a state of the memory cell; a detector configured to determine, based on the parameter read out from the memory cell, a soft information indicating the likelihood that the input data bit stored in the memory cell is a “0” or the likelihood that the input data bit stored in the memory cell is a “1”; and a decoder configured to generate a decoded bit based on the soft information. Further embodiments relate to a method of performing soft-decision decoding on a data bit stored in a memory cell of a memory device.

Abstract: A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. Further, the selection signal generator generates a complementary selection signal which is enabled when an equalization signal is inputted in a pre-charge mode after the active mode. The word line driver receives the main word line signal to drive a word line to have a first level when the selection signal is enabled, to drive the word line to have a second level when the selection signal is disabled, and to drive the word line to have a third level when the complementary selection signal is enabled.

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract: Column decoders are provided. The column decoder includes a power supplier and a column selection signal generator. The power supplier generates a supply voltage signal from a power voltage in response to a control signal enabled from a start point of time of a write mode or a read mode till an end point of time of a burst length. A level of the supply voltage signal is controlled according to the control signal. The column selection signal generator operates while the supply voltage signal is supplied. The column selection signal generator generates one of column selection signals, which is selectively enabled according to a logic combination of a high-order address signal, a mid-order address signal and a low-order address signal which are generated by decoding column address signals.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: Structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. Individual voltage regulators are employed on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.

Abstract: A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array. Each memory cell of the array is coupled to a word line. The memory includes a row decoder that controls a voltage on each of the word lines and controls a voltage on each of the voltage supply lines. The row decoder provides a low voltage state voltage on one of the voltage supply lines during a write operation to a subset of memory cells coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.

Abstract: A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.

Abstract: A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.

Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.

Abstract: A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A dynamic random access memory device may include DRAM memory cells including several lines of memory cells, and line selection circuitry associated with each line. The line selection circuitry may include a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state, and to deliver two intermediate control logic signals each having an intermediate voltage level above the initial level and corresponding to the first logic state. The line selection circuitry may also include a control circuit to be supplied by PMOS transistors with a supply voltage having a second voltage level greater than the intermediate voltage level, and configured to, in the presence of the two intermediate control logic signals have their first logic state deliver to the gates of the memory cell transistors, a selection logic signal having the second voltage level.

Abstract: A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.

Abstract: A nonvolatile memory device including memory blocks, a pre-decoder, and a row decoder is disclosed. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

Abstract: A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.