Using Shift Register Patents (Class 365/240)
  • Patent number: 10210196
    Abstract: An all-in-one data storage device includes a secondary memory providing read data in response to a read command, an internal hardware filter that filters the first read data according to filtering condition data in order to output filtered data, a primary memory, a host controller, and a memory controller that stores the filtered data in the primary memory and thereafter communicates the filtered data to the host controller.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Hoon Kim, Man Keun Seo, Sang Kyoo Jeong
  • Patent number: 9946475
    Abstract: Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 17, 2018
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Anxiao Jiang, Yue Li, Eyal En Gad, Michael Langberg, Jehoshua Bruck
  • Patent number: 9465853
    Abstract: Techniques are disclosed for implementing custom object-in-memory formats in a data grid network appliance. The techniques include maintaining a record of format definitions on a client device of the data grid and a corresponding record of format definitions on a server device of the data grid. Each format definition may indicate one or more attributes of an object class and data types and byte ranges of the attributes. The client device may serialize one or more objects for storage in the data grid based on respective format definitions associated with the one or more objects and retrieved from the record of format definitions maintained on the client device. Further, the server device may perform one or more data grid operations using format definitions retrieved from the record of format definitions maintained on the server device.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared H. Anderson, Chris D. Johnson, Fred A. Kulack, William T. Newport
  • Patent number: 9454588
    Abstract: Techniques are disclosed for implementing custom object-in-memory formats in a data grid network appliance. The techniques include maintaining a record of format definitions on a client device of the data grid and a corresponding record of format definitions on a server device of the data grid. Each format definition may indicate one or more attributes of an object class and data types and byte ranges of the attributes. The client device may serialize one or more objects for storage in the data grid based on respective format definitions associated with the one or more objects and retrieved from the record of format definitions maintained on the client device. Further, the server device may perform one or more data grid operations using format definitions retrieved from the record of format definitions maintained on the server device.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared H. Anderson, Chris D. Johnson, Fred A. Kulack, William T. Newport
  • Patent number: 9030898
    Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Patent number: 8937839
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eric Lee
  • Patent number: 8760947
    Abstract: A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Johann Zipperer
  • Patent number: 8711639
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Lee Eric
  • Patent number: 8687459
    Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Victor Wong, Alan Wilson, Christopher K. Morzano
  • Patent number: 8654557
    Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: February 18, 2014
    Inventors: Yasushi Takahashi, Toru Ishikawa
  • Patent number: 8477521
    Abstract: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwi-Dong Kim, Jun-Gi Choi
  • Patent number: 8432716
    Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Seiji Miura, Kazushige Ayukawa
  • Patent number: 8363508
    Abstract: To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic value of the first ODT signal at a time of shifting from an asynchronous mode to a synchronous mode is output during a period until when at least the clock signal is input by an additive latency after the shifting. With this configuration, an interruption of an CDT operation can be prevented without separately providing a CKE counter. Therefore, the circuit scale can be reduced and the power consumption can be also reduced.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 29, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Patent number: 8310854
    Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 13, 2012
    Assignee: Intel Corporation
    Inventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
  • Patent number: 8254205
    Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Chern Lee
  • Patent number: 8218377
    Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: July 10, 2012
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Amit Tandon, Promod Kumar, Abhishek Lal
  • Patent number: 8171258
    Abstract: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: May 1, 2012
    Assignee: Apple Inc.
    Inventors: Rajat Goel, Chen-Ju Hsieh
  • Patent number: 8102710
    Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Theodore T. Pekny, Victor Y. Tsai
  • Patent number: 8064237
    Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
  • Patent number: 8000164
    Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
  • Patent number: 8000163
    Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
  • Patent number: 7995365
    Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Elio D'Ambrosio, Ciro Chiacchio, Dionisio Minopoli
  • Patent number: 7986577
    Abstract: A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byeong Cheol Lee, Sang Il Park
  • Patent number: 7978534
    Abstract: A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: July 12, 2011
    Assignee: Round Rock Research, LLC
    Inventor: J. Thomas Pawlowski
  • Patent number: 7978558
    Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: July 12, 2011
    Assignee: Active-Semi, Inc.
    Inventor: David J. Kunst
  • Publication number: 20110161581
    Abstract: A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank.
    Type: Application
    Filed: July 9, 2010
    Publication date: June 30, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sang Hoon SHIN
  • Patent number: 7944773
    Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Victor Wong, Alan Wilson, Christopher K. Morzano
  • Patent number: 7898883
    Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 1, 2011
    Assignee: Nanya Technology Corporation
    Inventors: Shu-Liang Nin, Wei-Li Liu
  • Patent number: 7885141
    Abstract: Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eun-suk Kang
  • Patent number: 7872892
    Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 18, 2011
    Assignee: Intel Corporation
    Inventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
  • Patent number: 7859934
    Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Masayoshi Taniguchi, Isamu Mashima, Jun Usami
  • Publication number: 20100290306
    Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.
    Type: Application
    Filed: June 29, 2009
    Publication date: November 18, 2010
    Inventor: Jong Chern Lee
  • Patent number: 7834663
    Abstract: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: November 16, 2010
    Assignee: Oracle America, Inc.
    Inventor: Dennis Wendell
  • Patent number: 7836273
    Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 16, 2010
    Inventor: Robert Norman
  • Publication number: 20100278004
    Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyoung-Nam Kim, Ho-Youb Cho
  • Patent number: 7821861
    Abstract: A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 26, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Hong Lin, Tzu-Fang Lee, Chi-Lung Wang
  • Patent number: 7782682
    Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasurou Matsuzaki, Masao Taguchi
  • Patent number: 7768828
    Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 3, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Yub Lee
  • Patent number: 7765380
    Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: July 27, 2010
    Inventor: Robert Norman
  • Patent number: 7747020
    Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventor: Wajdi K. Feghali
  • Patent number: 7733739
    Abstract: A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: June 8, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung-Nam Kim, Sang-Hee Kang
  • Patent number: 7733713
    Abstract: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: June 8, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Nakano, Toshimasa Namekawa, Hiroshi Ito, Osamu Wada, Atsushi Nakayama
  • Patent number: 7646647
    Abstract: An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 12, 2010
    Assignees: Qimonda AG, Qimonda Flash GmbH & Co. KG
    Inventors: Thomas Kern, Thomas Mikolajick, Jan-Malte Schley
  • Patent number: 7567471
    Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Sean S. Eilert, Rodney R. Rozman, Shekoufeh Qawami, Glenn Hinton
  • Patent number: 7567482
    Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: July 28, 2009
    Assignee: Broadcom Corporation
    Inventors: Esin Terzioglu, Gil I. Winograd, Cyrus Afghahi
  • Publication number: 20090154286
    Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: ProMOS Technologies PTE.LTD.
    Inventor: Christopher M. Mnich
  • Patent number: 7525871
    Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Nagai, Ryo Haga
  • Patent number: 7495993
    Abstract: A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circuit to realize savings in power and silicon area. Because random access to the semiconductor device is not required, the interface from external to the semiconductor device is also simplified by eliminating at least the address port that is used to specify the memory locations accessed. The method is applicable not only to non-volatile memory technologies (e.g., flash memory), it is also applicable to volatile memory technologies, such as transient charge storage-based memory circuits (e.g., DRAMs) and metastable states-based memory circuits (e.g., SRAMs).
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: February 24, 2009
    Assignee: Capso Vision, Inc.
    Inventor: Kang-Huai Wang
  • Patent number: 7492623
    Abstract: An option circuit of a semiconductor chip includes a first option circuit that is set before packaging the semiconductor chip to generate a first option signal; a second option circuit that is set after packaging the semiconductor chip to generate a second option signal; and a selection circuit configured to: select one of the first option signal, the second option signal, and a mode register set signal in response to at least one first control signal; and output a first selected signal as a final option signal. An option method of a semiconductor chip includes setting a first option mode of the semiconductor chip by use of the first option circuit; setting a second option mode of the semiconductor chip by use of the second option circuit; and determining a final option mode of the semiconductor chip by selection of the first option mode or the second option mode.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hyung Lee
  • Patent number: RE44590
    Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: November 12, 2013
    Assignee: 658868 N.B. Inc.
    Inventor: Chang-Ho Do