Abstract: The fuse device includes a plurality of fuse circuits, a global latch circuit and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is used to sense the blown states of the fuse circuits at different times, so as to output the fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuits. Each of these local latch circuits latches the fuse information output by the global latch circuit at the different times.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

Abstract: A semiconductor device includes a pre-pulse generation circuit configured to generate a pre-pulse, based on a write shifting pulse and a write leveling activation signal; a write control signal generation circuit configured to generate a write control signal, based on the pre-pulse and a division clock; and a write leveling control circuit configured to generate detection data including information on a phase difference between a data clock and a system clock, based on the pre-pulse and the division clock.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

Abstract: A semiconductor device according to the present invention is formed by a plurality of semiconductor chips laminated on a substrate which are connected via a through electrode penetrating in a lamination direction, in which the plurality of semiconductor chips include first semiconductor chips 104 each having memory blocks and a decoder and a second semiconductor chip having a logic circuit, the logic circuit includes one selection circuit connected to the decoder of all the first semiconductor chips 104 and configured to select addresses of a first memory block 106A that stops input/output and a second memory block 106B that performs input/output instead among the plurality of memory blocks, and the addresses of the selected first memory block 106A and the selected second memory block 106B are each common to all the first semiconductor chips.

Abstract: The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

Abstract: A method is disclosed to identify a port that is associated with a faulty cable. In one embodiment, such a method identifies a cable to replace. The cable provides a path between a first port, residing on a first component, and a second port, residing on a second component. The method further identifies whether an alternative path, bypassing the first cable, exists between the first component and the second component. In the event the alternative path exists, the method sends, over the alternative path, from the first component to the second component, a command to activate an indicator on the second port. This command is received and executed by the second component to activate the indicator. A corresponding apparatus and computer program product are also disclosed.

Abstract: The invention provides efficient searching with fuzzy criteria in very large information systems. The technique of the present invention uses the Pigeonhole Principle approach. This approach can be utilized with different embodiments, but the most effective realization would be to amplify some already given intrinsic approximate matching capabilities, like those in the FuzzyFind method [1][2]. Considering the following problem, data to be searched is presented as a bit-attribute vector. The searching operation includes finding a subset of this bit-attribute vector that is within particular Hamming distance. Normally, this search with approximate matching criteria requires sequential lookup for the whole collection of the attribute vector. This process can be easily parallelized, but in very large information systems this still would be slow and energy consuming.

Abstract: An all-in-one data storage device includes a secondary memory providing read data in response to a read command, an internal hardware filter that filters the first read data according to filtering condition data in order to output filtered data, a primary memory, a host controller, and a memory controller that stores the filtered data in the primary memory and thereafter communicates the filtered data to the host controller.

Abstract: Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.

Abstract: Techniques are disclosed for implementing custom object-in-memory formats in a data grid network appliance. The techniques include maintaining a record of format definitions on a client device of the data grid and a corresponding record of format definitions on a server device of the data grid. Each format definition may indicate one or more attributes of an object class and data types and byte ranges of the attributes. The client device may serialize one or more objects for storage in the data grid based on respective format definitions associated with the one or more objects and retrieved from the record of format definitions maintained on the client device. Further, the server device may perform one or more data grid operations using format definitions retrieved from the record of format definitions maintained on the server device.

Abstract: Techniques are disclosed for implementing custom object-in-memory formats in a data grid network appliance. The techniques include maintaining a record of format definitions on a client device of the data grid and a corresponding record of format definitions on a server device of the data grid. Each format definition may indicate one or more attributes of an object class and data types and byte ranges of the attributes. The client device may serialize one or more objects for storage in the data grid based on respective format definitions associated with the one or more objects and retrieved from the record of format definitions maintained on the client device. Further, the server device may perform one or more data grid operations using format definitions retrieved from the record of format definitions maintained on the server device.

Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

Abstract: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract: To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic value of the first ODT signal at a time of shifting from an asynchronous mode to a synchronous mode is output during a period until when at least the clock signal is input by an additive latency after the shifting. With this configuration, an interruption of an CDT operation can be prevented without separately providing a CKE counter. Therefore, the circuit scale can be reduced and the power consumption can be also reduced.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.

Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Abstract: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.

Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.

Abstract: A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large.

Abstract: A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.

Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.

Abstract: A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank.

Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.

Abstract: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed.

Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.