Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.

Abstract: A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.

Abstract: An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.

Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.

Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Abstract: A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circuit to realize savings in power and silicon area. Because random access to the semiconductor device is not required, the interface from external to the semiconductor device is also simplified by eliminating at least the address port that is used to specify the memory locations accessed. The method is applicable not only to non-volatile memory technologies (e.g., flash memory), it is also applicable to volatile memory technologies, such as transient charge storage-based memory circuits (e.g., DRAMs) and metastable states-based memory circuits (e.g., SRAMs).

Abstract: An option circuit of a semiconductor chip includes a first option circuit that is set before packaging the semiconductor chip to generate a first option signal; a second option circuit that is set after packaging the semiconductor chip to generate a second option signal; and a selection circuit configured to: select one of the first option signal, the second option signal, and a mode register set signal in response to at least one first control signal; and output a first selected signal as a final option signal. An option method of a semiconductor chip includes setting a first option mode of the semiconductor chip by use of the first option circuit; setting a second option mode of the semiconductor chip by use of the second option circuit; and determining a final option mode of the semiconductor chip by selection of the first option mode or the second option mode.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.

Abstract: Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level.

Abstract: A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree.

Abstract: A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjacent memory elements such that with each control pulse of a row control signal the data words of the memory elements of all rows are shifted in a shift direction into the memory elements of the respectively adjacent row, with the data words of the last row being shifted into the first row, and such that with each control pulse of a column control signal the data words of the memory elements of all columns are shifted in a shift direction into the memory elements of the respectively adjacent column, with the data words of the last column being shifted into the first column, and which are designed such that an external write access is possible only in respect of at least one predefined row and at least one predefined column and such that an external read acc

Abstract: A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.

Abstract: An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the registers for storage of an operating parameter as a function of a first or second state of a configuration signal that is applied to an address connection. Any subsequent write and read access to one of the registers for storage of an operating parameter takes place analogously to a write and read access to a memory cell in a memory cell array. The integrated semiconductor memory device is thus operated to allow writing and reading of operating parameters using a standard interface and a standard protocol for inputting and outputting data to and from the memory cell array.

Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system util

Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.

Abstract: Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addresses are used to intercept a mode register set command signal that enables the MRS operation at a time point at which the memory device exits from the self-refresh mode.

Abstract: Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control circuitry and is also associated with other circuitry that is capable of acting as control circuitry that can be used as an alternative to at least part of the dedicated control circuitry. For example, the dedicated control circuitry may be set up to support one or several industry-standard protocols. The other circuitry (which may be, for example, programmable logic circuitry) is available to support any of a wide range of other protocols, whether industry-standard or custom.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.

Abstract: A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes the device to output selected memory pages.

Abstract: A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end data bit addresses in a bit range of the data to be read or written. Therefore, the data access method is applicable to various platforms with various byte endians.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A device for verifying hardware in a circuit arrangement that includes one or more configuration elements (106) operable to configure hardware elements (108) that are electrically coupled by one or more electrically-conductive pathways (110). The device includes a hardware-verification register (202) coupled to at least one of the electrically-conductive pathways (110). The register (202) is operable to sample a voltage level on at least one of the electrically-conductive pathways (110) at a first time point; store in a memory one or more bits, each bit representing the voltage level on at least one of the electrically-conductive pathways (110) at the first time point; sample a voltage level on at least one of the electrically-conductive pathways (110) at a second time point; and compare, for at least one of the electrically-conductive pathways, the voltage level at the first time point and the voltage level at the second time point.

Abstract: A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lines upon every refresh request. An activation circuit activates any of the normal word lines and redundancy word line according to an output of the shift register. A first storing circuit stores in advance a defect address indicating a defective normal memory cell row. A first activation control circuit prohibits activation of a normal word line corresponding to the defect address stored in the first storing circuit when the output of the shift register indicates the normal word line.

Abstract: A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip select signals for selecting the SDRAM devices. The logic gate generates an enable signal if a memory access is being directed to any of the SDRAM devices in the module. In one embodiment, the flip-flops include an enable input coupled to receive the enable signal from the logic gate. In another embodiment, the input signals are coupled to the data inputs of the flip-flops through logic gates that are selectively enabled by the enable signal from the logic gate. As a result, the input signals are not latched by transitions of the clock signal when a memory access is not directed to any of the SDRAM devices in the module.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip select signals for selecting the SDRAM devices. The logic gate generates an enable signal if a memory access is being directed to any of the SDRAM devices in the module. In one embodiment, the flip-flops include an enable input coupled to receive the enable signal from the logic gate. In another embodiment, the input signals are coupled to the data inputs of the flip-flops through logic gates that are selectively enabled by the enable signal from the logic gate. As a result, the input signals are not latched by transitions of the clock signal when a memory access is not directed to any of the SDRAM devices in the module.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.

Abstract: A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of pulses to the series of decoders in accordance with a difference in a stored previous address and a received current address.

Abstract: An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit.

Abstract: In a memory unit provided by the present invention, unit blocks are laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells arranged to form a cell matrix and a redundant line including a redundant memory cell. A plurality of unit blocks in the block matrix forms a one-dimensional group oriented in a first or second direction so that unit blocks pertaining to each one-dimensional group share a redundant line. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs required for determining a redundant line to be used for repairing an abnormal memory cell for each unit block in storage means. The address of the redundant line to be used for repairing an abnormal memory is then found for each unit block on the basis of the minimum number of address pairs stored in the storage means. By storing only minimum required address information as such, a small size of the storage means and, hence, small circuit scales are sufficient.

Abstract: An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command.

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: A package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same. In order to improve the reliability of package map data and easily output a greater amount of package map data, package map data is stored to package map data registers at the wafer level and then output through the test circuit at the package level.