Abstract: Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers (2), each comprising series-connected data holding elements (3), each data holding element (3) being connected to a data input line (5), each shift register (2), upon receiving an input control signal (INP) for the shift register (2), loading the data present on the data input lines (5) into the data holding elements (3) connected thereto; each shift register (2), upon receiving an output control signal (OUTP) for the shift register (2), outputting the datum buffer-stored in the last data holding element of the shift register (2), in which case there is connected downstream of each shift register (2) a further data holding element (10), which, upon receiving an input control signal (INP) for loading the preceding shift register (2), is preloaded with the datum for the first data holding element (3-3) of the shift register (2) and, upon reception of the output control signal (OUTP) for the shift register

Abstract: In each of the memory cell arrays in the memory banks, a memory cell row corresponding to each of the word lines extending in a column direction of each of the memory cell arrays store pixel data of each pixel block of first and second rows set in a horizontal way in a search area within a search frame of picture signal. The pixel data of a predetermined pixel block is selectively captured into each of the data buffer through the sense amplifiers and the switches. Selector sequentially extracts pixel data as candidate blocks based on the pixel data of two pixel blocks held in each of the data buffers. The matching circuit matches the pixel data as the extracted candidate blocks against the pixel data as the input reference block using the block-matching process to obtain a motion vector relative to the reference block.

Abstract: A package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same are provided. To improve the reliability of package map data and easily output a greater amount of the package map data, the package map data is stored to package map data registers at the wafer level and then output through the test circuit at the package level.

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with reference to the register, counts up an address while skipping an address requiring no refresh operation, to thereby generate an address of the memory space to be refreshed, and a refresh cycle generating circuit that with reference to the register 15, generates a refresh cycle with a cycle which varies according to the number of the memory space requiring the refresh operation.

Abstract: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

Abstract: A device for generating memory addresses is provided that is suitable for generating memory addresses transposed in row/column directions with reference to a data successively stored therein along with a mobile station by using the same, and a method for writing/reading a data. The device includes a counter that generates 22n successive addresses in 2n bitstreams to provide row direction addresses, and a barrel shifter that shifts the generated 2n bitstreams by ‘n’ bits to provide column direction addresses. Thus, circuitry of a picture encoder of the mobile station or of an interleaver in a mobile communication system is reduced, and a faster operation speed is obtained.

Abstract: An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The access controller accesses the memory cell array in a first double data rate operating mode of the memory in such a manner that a first data item (which is to be written) of an access cycle is written to the memory cell array with a write latency. In a second single data rate operating mode of the memory, the access controller, in contrast, accesses the memory cell array in such a manner that a first data item of an access cycle is, in contrast, written to the memory cell array in an accelerated manner without the write latency of the first operating mode. This makes it possible to read in data values in an accelerated manner in the second operating mode, in particular a test operating mode.

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

Abstract: A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip select signals for selecting the SDRAM devices. The logic gate generates an enable signal if a memory access is being directed to any of the SDRAM devices in the module. In one embodiment, the flip-flops include an enable input coupled to receive the enable signal from the logic gate. In another embodiment, the input signals are coupled to the data inputs of the flip-flops through logic gates that are selectively enabled by the enable signal from the logic gate. As a result, the input signals are not latched by transitions of the clock signal when a memory access is not directed to any of the SDRAM devices in the module.

Abstract: A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

Abstract: A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving FIFO. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Abstract: The present invention discloses a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor. When data of the memory cell selected by a received address in a read operation according to a first command signal are outputted through a data output pad, if a second command signal is inputted, address and data are stored in registers, an operation is performed according to the second command signal, and then the read operation is carried out by using the address and data stored in the registers.

Abstract: A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.

Abstract: A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Abstract: A memory including a plurality of memory word lines and a sequential addressing circuit is provided. The sequential addressing circuit comprises at least one sequential shift register including at least one logic gate and at least one word flag cell for each of the word lines. Enablement of each memory word line depends upon the state of the word flag cell. An enable or access bit is shifted sequentially through the sequential. addressing circuit to select each of the word lines. The enable or access bit selectively bypasses or skips a word line depending on the state of its corresponding word flag cell. A method for accessing a nonvolatile writeable memory is also described. The method comprises determining at least one non-operational or defective memory bit cell of a nonvolatile writeable memory. At least one word line of the nonvolatile writeable memory is masked out, wherein the at least one word line is coupled to the at least one non-operational operational memory bit cell.

Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: The present invention generally provides a system and method for writing data to a register file. In architecture, the system of the present invention utilizes a plurality of registers and a write port coupled to each of the registers. The write port receives a register identifier identifying one of the registers and receives a first signal, such as a bit of predicate data, a set signal, or a reset signal. The write port transmits the first signal and a decode signal to each of the registers. The write port is configured to assert the decode signal transmitted to the one register identified by the register identifier and to deassert the decode signal transmitted to the other registers. Each of the registers includes a set/reset latch and is configured to receive the first signal and the decode signal transmitted to it from the write port.

Abstract: A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a data memory space. The data memory space includes a plurality of message buffers associated with respective ones of the message objects, and a dedicated RAM memory space that contains a plurality of memory-mapped registers associated with each of the message objects. The plurality of memory-mapped registers associated with each message object correspond to respective command/control fields for facilitating configuration and setup of that message object. Each of the memory-mapped registers is mapped to a respective storage location within the dedicated RAM memory space. In one embodiment, the dedicated RAM memory space encompasses a plurality of separate RAM modules, each RAM module being dedicated to a respective one of the command/control fields.

Abstract: A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: A semiconductor memory circuit capable of conducting an efficient test by using a memory tester is provided. A semiconductor memory circuit includes a memory cell array; a plurality of main data lines for conducting reading and writing every plural bits in parallel; and a shift register for converting parallel data read from memory cell array to the main data lines into serial data and supplying the converted data to data input/output terminals, and for converting write data supplied from the data input/output terminals in series into parallel data and supplying the converted data to the main data lines, and at least a portion of a plurality of the main data lines are arranged so as to be across each other between the memory cell array and the shift register. As a result, data compression is enabled during a test by a memory tester.

Abstract: A FIFO memory device includes a write address generating circuit generating a write address in response to a write clock signal and a read address generating circuit generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating circuit compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.

Abstract: A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

Abstract: A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Abstract: A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.

Abstract: An interface circuit providing serial access to a non-volatile memory in an integrated circuit has at least two memory-access scan registers and at least one selection scan register coupled in common to a data input terminal of the integrated circuit. These registers are also coupled through a multiplexer to a data output terminal of the integrated circuit. The memory-access scan registers receive serial data such as address data and data to be written in the non-volatile memory at the specified addresses. The selection scan register receives a code for selecting the memory-access scan registers. Serial access to the non-volatile memory is speeded up because the memory-access scan registers can be accessed individually.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.

Abstract: An apparatus for determining a state of a plurality of clock signals, comprising a circuit configured to store a state of each of said plurality of clock signals upon an edge of a data signal.

Abstract: In a memory module having a plurality of memory chips and a plurality of data switchers on one board, wherein each data switcher is selectively turned on or off in response to a switcher control signal to connect corresponding memory chip with a common data bus line, an apparatus for generating the switcher control signal includes: a plurality of shift counting units for shift counting a write command signal in response to an internal clock signal and a reset signal, to generate a plurality of shift counting signals; a switcher enable control signal generator for receiving the shift counting signals to generate a switcher enable control signal for enabling the switcher control signal during a predetermined time corresponding to a burst length; a pull down driver for pulling down the switcher control enable signal to generate a pull-down signal; and an output unit for outputting the switcher control signal in response to the pull-down signal.

Abstract: A non-volatile memory device having a main memory that operates synchronously with the system clock and an asynchronous boot block. The boot block can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

Abstract: A reconfigurable chip includes data registers which can be loaded from off-chip or on-chip. The data register comprises a register block produced from a number of register block units. The register bock units include an active plane store storing the current value of the register bit, at least one off-chip data background store storing a data bit which can be loaded from off-chip, and at least one on-chip data background store storing a value which can be loaded from on-chip.

Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn+1=0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory.

Abstract: A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a “2-hot” encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

Abstract: A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundant memory cells each of which is coupled to one of the word lines and to the redundant bit line. The device further includes a coincidence circuit that receives a first address signal, indicating an address of one of the normal bit lines, and a second address signal, indicating an address of one of the normal bit lines to which a defective memory cell is coupled, and which selects the redundant bit line when the first address signal coincides with the second address signal.

Abstract: This invention discloses a memory cell threshold voltage shift method effective for the erase or write sequence of a nonvolatile semiconductor memory. First, the threshold voltages VTH of a plurality of memory cells are shifted at once to a range whose upper limit is set to an erase verify voltage VEV. After this, the lower limit of the threshold voltages VTH shifted at once to the range is shifted to a first overerase verify voltage VOEV1 close to the erase verify voltage VEV. Then, the lower limit of the threshold voltages VTH shifted to the first overerase verify voltage VOEV1 to a second overerase verify voltage VOEV2 closer to the erase verify voltage VEV.

Abstract: The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the burst operating mode and on an address bit A1 of the external column address. Moreover, the memory has a transformation unit C2; SR2, which forwards partial addresses A2 . . . 1′; PA3 . . . 0′ generated by the address counting unit C1; S either unchanged or incremented by the value 1 to the second column decoder CDEC2, in a manner dependent on the burst operating mode and a further address bit A0 of the external column address A7 . . . 0.

Abstract: A semiconductor memory device comprises: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array configured to relieve a defective column of the memory cell array; a decoder circuit configured to decode an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a data line, to which data read out from the redundant column cell array or data to be written in the redundant column cell array is transferred; a data line shift circuit configured to shift, one by one, data line and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data line and the spare data lines to data input/output lines; a selecting circui

Abstract: A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: A serial access memory reduces a chip size and saves a process development.