Abstract: A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data input bus is coupled to each of the M rows. The mode input bus and the data input bus can uniquely identify as a match a single subword or a plurality of subwords in one of the M rows during a search operation. The disclosed embodiment further comprises a row address encoder/generator coupled to each of the M rows, and an address output bus coupled to each of the row address encoder/generators. The mode input bus is also coupled to each of the row address encoder/generators. A uniquely identified single subword address may be outputted on the address output bus.

Abstract: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.

Abstract: A Content Addressable Memory (CAM) architecture is disclosed wherein at least part of an access key is unconditionally written to a CAM memory location. This unconditional writing is performed while accessing a set of CAM memory locations for the purposes of matching the access key. This writing is performed regardless of whether a match to the access key is found.

Abstract: In a packet switching device or system, such as a router, switch, combination router/switch, or component thereof, a method of and system for performing a table lookup operation using a lookup table index that exceeds a CAM key size is provided. Multiple CAM accesses are performed, each using a CAM key derived from a subset of lookup table index, resulting in one or more CAM entries. One or more matching table entries are derived from the one or more CAM entries resulting from the multiple CAM accesses.

Abstract: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an entry is valid and based on a type selection.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: Controlling a searchable range within a network search engine. A CAM array is provided within the network search engine to store data values in entries having respective addresses and to compare the data values with a search key. First address and a second addresses that define a range of the addresses are received at an interface of the network search engine, and range-control circuitry is provided within the network search engine to generate a hit signal having either a first state or a second state according to whether any of the entries having addresses within the range of addresses match the search key.

Abstract: A ternary content addressable memory (TCAM) system and method of operating the same can enable a user to configure the system to operate as either a pseudo TCAM or full TCAM system. Control logic (206) can have an address modification circuit (250) coupled between multiple inputs and row decoders (206-0 and 206-1) for simultaneously writing the same mask value to mask fields of a predetermined number of memory locations in a full TCAM array.

Abstract: A mixed serial-parallel content addressable memory (CAM) includes serial CAM cells and parallel CAM cells that are arranged in multiple (N) columns and multiple (M) rows. Each row includes at least one serial CAM cell and at least two parallel CAM cells. The M rows are searched in parallel. For each row, the serial CAM cells are searched sequentially, and the parallel CAM cells are selectively searched in parallel. The CAM further includes a driver that generates search lines for the N columns of CAM cells, one search line per column. The driver sets the search lines to an N-bit value to search for in the CAM. Prior to each search operation, the driver presets at least one search line for at least one column of serial CAM cells to precharge a match line for each row.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A method for identifying memory bit cells and connections for analysis of a circuit block. The method includes defining a bit pattern for each bit cell node in a bit cell. The method also includes defining a node pattern for each node in the circuit block; and matching the node patterns with the bit patterns. The bit cells and corresponding bit line connections and word line connections in the circuit block are determined based on matches found during the matching.

Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and, according to the rules used for generating the feature vectors corresponding to the stored documents such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more, additional result columns coding for a similarity measure bet

Abstract: A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes a FLOating gate Tunnel OXide (FLOTOX) element. The FLOTOX element includes a single floating gate transistor and a high voltage select transistor and can store at least a portion of a data word. Each CAM cell also preferably includes at least one low voltage transistor capable of comparing the portion of data word stored in the FLOTOX element with the portion of searched word. The search line(s) provide search word(s). The comparator(s) are connected with the search line(s) and the memory cells. The comparator(s) compare the data word stored by the portion of the plurality of memory cells and the search word. The match line(s) indicate whether the search word matches the data word stored by the portion of the plurality of memory cells.

Abstract: A content addressable memory (CAM) device (200) can provide for suppression of hit indications. Prioritized match indications (212) can be applied in parallel to both an encoding read-only-memory (ROM) (204-1) and suppression data store (206). A suppression data store (206) can output suppression bits (SH0 and SH1) that correspond to each CAM entry. Hit indications can be selectively suppressed according the values of suppression bits (SH0 and SH1). Hit suppression methods for a CAM device are also disclosed.

Abstract: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Abstract: A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1 or PDA2) on the basis of the enable signal (ES) According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.

Abstract: In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and fewer encoded bits per entry than conventional encoding schemes.

Abstract: A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.

Abstract: A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.

Abstract: A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory.

Abstract: In a packet switching device or system, such as a router, switch, combination router/switch, or component thereof, a method of and system for performing a table lookup operation using a lookup table index that exceeds a CAM key size is provided. Multiple CAM accesses are performed, each using a CAM key derived from a subset of lookup table index, resulting in one or more CAM entries. One or more matching table entries are derived from the one or more CAM entries resulting from the multiple CAM accesses.

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of the CAM cells, each pair of data lines including at least one data line that is formed by conductive segments disposed in two different conductivity layers of the CAM device.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

Abstract: A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address. A memory system according to yet another embodiment includes a word decoder having more than sixteen address line inputs. A memory system according to a further embodiment includes a word decoder array having fewer word decoders than combinations of memory addresses. Methods are also provided.

Abstract: A search circuit for determining whether an input string including a plurality of input characters matches an inexact pattern including a number of pattern characters that are members of a specified character set, the search circuit including an input for receiving a bitcheck command, the bitcheck command containing a bitmap including a plurality of compliance bits each indicating whether a corresponding one of a plurality of reference characters of a general character set is a member of the specified character set, and a circuit for referencing each of the input characters to a corresponding compliance bit in the bitmap to determine whether the input character are members of the specified character set.

Abstract: A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.

Abstract: In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.

Abstract: A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

Abstract: A low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized CAM cell groups, each CAM cell group having one or more CAM cells; a valid entry tag bit associated with each said content addressable memory cell; a match output generator connected to the output of each CAM cell and an enabling means having its first input connected to the valid entry tag bit, its second input connected to a match control signal and its output connected to the corresponding match output generator such that said match output generator is enabled only if said valid entry tag bit indicates a valid entry.

Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.

Abstract: A content addressable memory (CAM) device having a multi-row write function. The CAM device includes a CAM array and an address circuit. The CAM array includes a plurality of CAM cells and word lines coupled to respective rows of the CAM cells. The address circuit is coupled to the CAM array and configured to activate a plurality of the word lines simultaneously to enable a write value to be stored within a selected plurality of the rows of CAM cells.

Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

Abstract: A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.

Abstract: A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and configurable switches between the key nanowires and the value nanowires. The combination further includes a key microwire-nanowire grid (key MNG) electrically connected to the spaced-apart key nanowires, and a value microwire-nanowire grid (value MNG) electrically connected to the spaced-apart value nanowires. A key or value MNGs selects multiple nanowires for a given key or value.

Abstract: A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

Abstract: A content addressable memory (CAM) system that includes a row of NAND-type CAM cells divided into a plurality of segments. Each segment includes a plurality of series-connected switching transistors, wherein each of the switching transistors is part of a corresponding NAND-type CAM cell. The series-connected switching transistors of each segment are coupled to the series-connected switching transistors in an adjacent segment by a repeater circuit, thereby forming a chain of series-connected switching transistors and repeater circuits. A match line driver circuit is coupled to one end of the chain, and a match line is connected to the other end of the chain. If a match condition exists for the entire row, then a signal driven by the match line driver is propagated to the match line, through the chain of series-connected switching transistors and repeater circuits.

Abstract: A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.

Abstract: A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

Abstract: A content addressable memory (CAM) device can include a plurality of CAM super-blocks each comprising a plurality of sub-blocks. Each sub-block can include a plurality of CAM entries that generate match results in response to a key value. For each sub-block there can be storage for a programmable local priority value that establishes priority of match results of the sub-block with respect to match results of the other sub-blocks of the same CAM super-block. In addition, for each sub-block there can be a programmable global priority value, different from the programmable local priority value, that establishes priority of match indications of the sub-block with respect to match results of sub-blocks of the plurality of CAM super-blocks.

Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

Abstract: A configurable memory system and method is wherein an integrated circuit coupled to a memory device includes application logic and memory interface logic in communication with the application logic, the memory interface logic configured to access a memory array within the memory device. The memory interface logic provides logic functions and/or signals that would have been provided by logic on a prior art memory device. The interface logic may access the memory device synchronously or asynchronously. The integrated circuit may communicate to the memory device using multiplexed or non-multiplexed signals.

Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

Abstract: A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.