Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A network recognition system for identifying a storage unit of a plurality of network storage subsystems of a machine (1) including at least one local coupler (11) for exchanging data with the storage subsystems (5, 6, 7) of the network recognition system, each storage subsystem (5, 6, 7) having at least one storage unit identifiable by means of a logical unit number (LUN). An object (100) corresponding to the machine (1) has an object (101) corresponding to the local coupler (11) of the machine (1). Object (101) includes an object (111) corresponding to a remote coupler (51, 52) of one of the storage subsystems (5). Object (101) includes a method (116) for obtaining the object (111) and a list of objects (118, 119) each corresponding to a logical unit number (LUN) identifying a storage unit of the subsystem (5) accessible through the local coupler (11).

Abstract: A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

Abstract: A memory module includes a first group of integrated-circuit memory units each having a control pin terminal, and a second group of integrated-circuit memory units. Each memory unit of the second group includes a control pin terminal and at least one memory unit of the second group further includes at least one vacant pin terminal. First connections are provided for receiving a control signal from an external source and supplying it to the control pin terminal of each of the first group of memory units. Second connections are provided for receiving and supplying the control signal to the control pin terminal of each of the second group of memory units and to at least one vacant pin terminal of the second group of memory units. Preferably, the vacant pin terminal is connected to a circuit equivalent in operating characteristics to a circuit connected to the control pin terminal.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuitry board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A multichip semiconductor package provides redundancy mapping from one semiconductor chip to another. The semiconductor device can be salvaged, where normally it normally would be considered scrap. This is particularly important where multiple semiconductor chips are physically connected as a common unit. One multichip integrated circuit package has semiconductor chips integrally formed on a unitary substrate, and each semiconductor chip includes redundant circuitry adapted to selectively replace primary circuitry. Electrical interconnects couple the redundant circuitry from a one semiconductor chip to a second semiconductor chip.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after complet assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A memory system for use in a computer system, includes a plurality of volatile solid state memory devices that retain information when an electrical power source is applied to the memory devices within a predetermined voltage range, and are capable of being placed in a self refresh mode. The memory devices have respective address and control lines, and a control device for selectively electrically isolating the memory devices from respective address lines and respective control lines so that when the memory devices are electrically isolated, any signals received on the respective address lines and respective control lines do not reach the memory devices.

Abstract: A semiconductor dynamic random access memory device has a memory cell array divided into columns of memory cell blocks equal to a natural number except powers of two such as, for example, six and arranged in rows and columns, redundant memory cells are formed in two columns of memory cell blocks so as to equalize the loads driven by decoder units of a column address decoder, and the memory cell blocks are respectively formed in areas equal in width to one another so as to equalize sub-word lines connected between row address sub-decoders and the regular/redundant memory cells regardless of the number of regular/redundant memory cells incorporated in each memory cell block.

Abstract: A flash memory card includes one or a plurality of flash memories and a controller having an interface connected to a host computer to store card attribute information to be presented to the host computer at a predetermined storage position in the flash memory.

Abstract: The reliability of data read out from a flash EPROM is improved. The flash EPROM increases the reliability of stored data. A plurality of memory areas (1, 2, 3) includes a first memory (1) and a second memory area (2). Sense amplifiers (5-1, 5-2) are provided for the first and second memory areas (1, 2). A comparing device (6) is for comparing the data read out from the first and second memory areas (1, 2). A controlling device (9) selects either of the normal mode for independent utilization of the first and second memory areas (1, 2) and the high reliability mode for simultaneous utilization of the first and second memory areas (1, 2). In the high reliability mode, the controlling device (9) controls the first and second memory areas (1, 2) to store identical data, and controls the comparing device (6) a) to compare the data read out from the first and second memory areas (1, 2), and b) to output the data to the outer circuit, when the read out data are identical to each other.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).

Abstract: A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

Abstract: In a flash memory, flash cells are paired off so each pair includes a memory cell for storing data and a query cell for storing a characteristic analog value representative of the erase or programming speed of the memory cell. To erase a memory cell, the value stored in the query cell with which it is associated is retrieved, the current state of the memory cell is read, and an erase pulse having a pulse width (or amplitude) that is a function of the value retrieved from the query cell and the current state of the memory cell is then sent to the memory cell to erase it. To program a data bit into a memory cell, the value stored in the query cell with which it is associated is retrieved, and a programming pulse having a pulse width that is a function of the data bit and the value retrieved from the query cell is then to the memory cell to program it.

Abstract: A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.

Abstract: There is a memory module for use in conjunction with high speed, impedance-controlled buses. Each memory card may be a conventional printed circuit card with memory chips attached directly to the card. Alternately, high density memory modules assembled from pluggable sub-modules may be used. These sub-modules may be temporarily assembled for testing and/or burn-in. Bus terminations mounted directly on the memory card or the memory module eliminate the need for bus exit connections, allowing the freed up connection capacity to be used to address additional memory capacity on the module. An innovative pin-in-hole contact system is used both to connect sub-modules to the memory module and, optionally, to connect the memory module to a mother board or similar structure. A thermal control structure may be placed in the memory module to cool the increased number of memory chips to prevent excess heat build-up and ensure reliable memory operation.

Abstract: A cartridge comprising a substrate, at least a first set of dies, at least a first thermally conductive cover and at least a first compliant thermally conductive pad. The substrate has first and second opposed sides and electrical contacts along an edge thereof. The dies of the first set have first and second opposed faces. The dies of the first set are mounted to the first side of the substrate with the first face of each die facing towards the first side of the substrate. The first thermally conductive cover has first and second opposed surfaces and is mounted over the dies with the first surface of the first thermally conductive cover facing towards the dies. The thermally conductive pad is located between the first set of dies and the thermally conductive cover thermally couples the second faces of at least two of the dies of the first set and the first surface of the first cover with one another.

Abstract: An updater device for flash read-only memory is provided. The updater device may be constructed using a power input interface that transfers battery from either a battery or an electrical adapter to the updater device. The updater device has a body containing circuitry that controls the operations of the device. Located in the body is an input, or first, port and an output, or second, port for engaging flash read-only memories. A source flash read-only memory is inserted into the input port and the updater is then placed over the target flash read-only memory so that the updater device engages the target flash memory. A button that is located on the body activates the updating process. First the microprocessor reads data from the source flash read-only memory via a first read-only memory interface located in the input port. Then the microprocessor uses a second read-only memory interface in the second port to erase the target read-only memory.

Abstract: An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.

Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.

Abstract: A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted.

Abstract: A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively.

Abstract: A DRAM architecture configures memory cells into a predetermined number of arrays. Each array has its own row decoders and sense amplifiers. A data path circuit containing local drivers and data read and write lines is associated with each of the arrays in a first direction. The respective connections between the array and data path circuit utilize IO lines that are considerably shorter than the IO lines used in prior art architectures. Using this unique arrangement of data path circuits and memory arrays as a building block, a DRAM architecture of increased capacity can be constructed by simply placing additional data paths and memory arrays on to the semiconductor device in a second direction orthogonal to the first direction.

Abstract: A battery assembly is provided for holding a battery and for supplying power to an integrated circuit. When the battery is removed from the battery assembly, the battery assembly provides a LOW level signal to either the high voltage input (Vdd) of the integrated circuit or the reset port of the integrated circuit. The battery assembly includes a battery holder, a negative electrode attached to the battery holder and electrically connected to the a negative power line related to the integrated circuit, and a positive electrode also attached to the battery holder and connected to a positive power line to provide power to the integrated circuit. The positive and negative electrodes are disposed such that the battery may be held between the positive and negative electrodes, with positive and negative terminals of the battery in electrical contact with the positive and negative electrodes. The negative electrode includes an electrically conductive extension.

Abstract: A connecting apparatus, which can be used in combination with a plurality of IC, cards. The connecting apparatus holds an inserted smart card (first IC card) having a first flat type connecting terminal on a first face thereof and holds a memory card (second IC card) having a second flat type connecting terminal on a first face thereof and smaller than the first IC card. The connecting apparatus comprises a first connecting device having a slot into which the smart card is inserted and a connecting electrode which is so formed as to contact the flat type connecting terminal when the smart card is inserted into the slot; a second connecting device having a slot into which the memory card is inserted and a connecting electrode which is so formed as to contact the flat type connecting terminal when the memory card is inserted into the slot.

Abstract: A multi-chip sensing device package and a method for forming such package are disclosed. The multi-chip sensing device package is built on an electrically insulative substrate such as a ceramic material, by using a thick film printing technique to print a multiplicity of bonding pads including interconnection pads and output pads on the surface of the rigid, insulated substrate. After a plurality of sensing elements are bonded by solder to the plurality of bonding pads, the sensing device may be connected to either lead fingers of a lead frame, or to J-leads formed integral with the device for providing electrical communication with an external circuit. The device may further be packaged in a plastic housing with a top surface of the device exposing to the environment for performing its detection function.

Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Abstract: Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

Abstract: System modules are described which include a stack of interconnected semiconductor dies. The semiconductor dies are interconnected by micro bump bonding of coaxial lines that extend through the thickness of the various dies. The coaxial lines also are selectively connected to integrated circuits housed within the dies. In one embodiment, a number of memory dies are interconnected in this manner to provide a memory module.

Abstract: A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: A quad in-line memory module (QIMM) includes a circuit board having top and bottom edge connectors and a number of memory devices mounted on each side of the circuit board. Generally, half of the memory devices are electrically connected to the bottom edge's connector and half are electrically connected to the bottom edge's connector. One edge of the QIMM can be connect directly to a computer system's memory bus. The other edge can be connected to operated as a cache memory or a video memory.

Abstract: Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal lines (20) are located on the memory module substrate (14) and the memory chips (15) are electrically coupled to the memory chip signal lines at spaced apart chip coupling points (23). Digital signals are driven to the memory chip signal lines (20) through signal lines (21) having a first level impedance. The memory chip signal lines (20) have a second level impedance greater that the first level impedance. The spacing between the chip coupling points (23) is chosen such that the effective impedance level of the memory chip signal lines (20) substantially matches the lower, first level impedance.

Abstract: Non-volatile write-once memory, is used for storage of variable data. In an example embodiment, segmented flash memory is used, in which individual segments can be erased. At least two segments are used. When a segment is nearly full, or when the segment is corrupted, the latest values are written to a new segment. During initialization, all variables of interest are written into RAM with default values. The flash segment being used is read sequentially from oldest entry to newest entry, and values from flash memory are used to overwrite values (or pointers to values) in RAM. RAM then contains (or points to) the most recent value for every variable. When a new segment is written, the new segment is written using the values from RAM. The method provides for identification of the latest (current) value for each stored item of information, provides for adding new types of data and deleting old types of data, provides for action when a memory segment is full, and provides for recovery from power-failure.

Abstract: A memory storage system includes a motherboard, a first memory card, and second memory card. The motherboard has a first and second electrical connector. The first memory card has a plurality of electrical connections coupled to the first electrical connector on the motherboard. The first memory card is adapted to receive a plurality of data signals over the first electrical connector and store the data signals in a first preselected pattern. A second memory card has a plurality of electrical connections coupled to the second electrical connector on the motherboard. The second memory card is adapted to receive a plurality of data signals over the second electrical connector and store the data signals in a second preselected pattern, different from the first preselected pattern.

Abstract: An architecture for data correction that may be used in non-volatile random access memories. In one embodiment, a circuit configured to be responsive to a control signal and to provide bitline outputs in response to bitline inputs is provided. The states of the bitline outputs depend upon the states of the bitline inputs and the control signal. The control signal may be provided by a non-volatile static random access memory (SRAM) cell. The circuit may include inverting and non-inverting paths or may include crossing and passing circuitry. The crossing and passing circuitry connects a first input of the circuit to a second output of the circuit in response to a first state of the control signal and further connects the first input to a first output of the circuit in response to a second state of the control signal. The control signal may be generated by a control device such as a non-volatile random access memory cell.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.

Abstract: A memory package for storing data and capable of being added to or replaced while being provided with a battery backup in computer systems which can be mounted with a plurality of said memory packages. A memory package also has a function to reduce power consumption of the battery backup to a minimum, when the memory package with battery backup is inserted into the computer system without the main power being applied. Consequently, even if additional memory packages are inserted in computer systems installable with memory packages having battery backups, only a weak current need be supplied from the backup power supply so that the battery will not run down after a short time. The memory packages can therefore be added and replaced while still storing data internally and the memory capacity can be changed.

Abstract: According to the present invention, the main word lines arranged in a row direction have a linear pattern shape, and in the region where sub word decoder circuits are formed, the pattern of the main word lines has a shape whereby the pattern branches and splits into a plurality of lines and then reconverges, in the direction of the row. In the region where the line splits, relatively small island-shaped patterns of the conducting layer are located, forming nodes which have a difference electric potential from the main word lines. The main word lines are constituted by a first metal conducting layer, similarly to the prior art. In other words, small island-shaped metal layer patterns, which are electrically different from the main word lines are formed inside the conducting metal layer pattern constituting the main word lines, similarly to island formed in the middle of a river, for example.

Abstract: A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Abstract: A nonvolatile semiconductor memory device capable of improving a reliability of a spare region, capable of improving the reliability of a data region in accordance with a method of use, and capable of realizing a function of an additional writing as a multi-level memory, and an IC memory card using the same, provided with a data region capable of storing 4-level and binary data; a spare region capable of storing binary data; data region use decoders for supplying a drive voltage to the data region; spare region use decoders and for supplying the drive voltage to the spare region; a latch circuit for transferring data with the data region in accordance with the number of levels of the multi-level data to be stored in the data region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally completed; and a latch circuit for transferring data with the spare region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally com

Abstract: A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

Abstract: An installation inside a memory slot for providing a constant loading to an external signaling line with or without the insertion of a memory module into a memory slot. The installation operates by supplying a load element whose loading effect is roughly equivalent to the loading effect of a memory module when no memory module is plugged, and disconnecting the load element internally when a memory module is plugged into the memory slot. Hence, a constant loading is provided to the external signaling line no matter a memory module is plugged or not, and so signal quality and integrity of the signaling line can be maintained.

Abstract: According to one aspect of the present invention, a selectable integrated circuit assembly (10) is disclosed. The assembly includes a first plurality of terminals (20) for communicating information to and from an integrated circuit device and a second plurality of terminals (22) for receiving an assembly address. The assembly (10) also includes select logic (14) connected to receive the assembly address and operable to generate select signals based upon the assembly address. The select signals have a selected state and a not-selected state. A plurality of switches (18) are connected between the first plurality of terminals (20) and the integrated circuit device. The plurality of switches (18) are connected to receive the select signals. The switches (18) operate, when the select signals are in the selected state, to connect the first plurality of terminals (20) to the integrated circuit device.

Abstract: An electronic memory device, in particular for use in implantable medical appliances, is provided with one or more electronic read/write memory chips, a carrier for the mechanical fixing of the RAM chip or chips, address inputs, a read/write input and a data bus connection, the RAM chip or chips in the memory device each being provided with two interfaces which are arranged on the input side and output side relative to the respective RAM chip and each comprise address bus, data bus and read/write connection, the address bus, data bus and read/write connection of the input-side interface being connected internally directly to the respectively allocated address bus, data bus and read/write connection of the output-side interface for signal transmission by the RAM chip.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.