Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A connecting apparatus, which can be used in combination with a plurality of IC, cards. The connecting apparatus holds an inserted smart card (first IC card) having a first flat type connecting terminal on a first face thereof and holds a memory card (second IC card) having a second flat type connecting terminal on a first face thereof and smaller than the first IC card. The connecting apparatus comprises a first connecting device having a slot into which the smart card is inserted and a connecting electrode which is so formed as to contact the flat type connecting terminal when the smart card is inserted into the slot; a second connecting device having a slot into which the memory card is inserted and a connecting electrode which is so formed as to contact the flat type connecting terminal when the memory card is inserted into the slot.

Abstract: A shared interface to a non-volatile memory including a first storage area for BIOS and a second storage area (e.g., for multimedia data) provides an integrated configuration which saves the cost and space of duplicating memory elements to support multiple data and program types in personal computers. The BIOS information is shadowed from the non-volatile memory to a second memory (e.g., a PC main memory). Thereafter, the BIOS information is accessed in the second memory and the information of the second storage area is accessed via the shared interface. The storage may be integrated upon personal computer system boards without a degradation in performance or an increase in pin count of the board memory because the same pins are used at different times for different memory portions. Accordingly, a storage system is provided to meet the demands of increasing storage requirements without a corresponding increase in cost, space or performance.

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.

Abstract: A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

Abstract: A single in-line memory module (SIMM) for memory expansion in a computer system. The SIMM includes a plurality of memory chips surface-mounted on a printed circuit board. The printed circuit board includes a dual read-out connector edge adapted for insertion within a socket of the computer system. One or more driver chips may further be mounted on the printed circuit board and connected to distribute control signals to the memory chips. A full-width data path may further be connected between the dual read-out connector edge and the plurality of memory chips.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A memory card design which allows for stackable memory cards so that a computer system's memory capabilities can be expanded by connecting a first memory card to sockets of the computer system's motherboard and then stacking subsequent memory cards on top of this first memory card. The memory card design includes connector sockets on a top surface of the card which allow for another card to be plugged into these sockets. Also, a presence detect serial EPROM and steer and encode logic are provided to assign a unique system address to each presence detect. The serial presence detect address select wiring are offset within the stack as are RAS lines so that all lines do not have to be hard-wired through each card of a stack of the present invention.

Abstract: A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Abstract: A memory card consisting of volatile memory that is used connected to a host system apparatus and operated by a power supplied from said host system apparatus, comprises a main memory consisting of volatile memory and a submemory consisting of flash memory wherein when the power is tuned off, the host system apparatus copies data stored in the main memory into the submemory at addresses, corresponding to addresses of the main memory, and when the power is turned on, the host system apparatus writes data stored in the submemory into the main memory at the original addresses.

Abstract: A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

Abstract: An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.

Abstract: Provided is a PC card and peripheral device having a non-volatile memory device that can perform erasing and re-writing at a relatively high operational voltage, and an internal circuit that is driven at a relatively low voltage, and is accomplished by a typical PC card that comprises: (a) an EEPROM serving as a non-volatile memory device; (b) a built-in battery having a low voltage output that supports the reading of the EEPROM but does not support erasing and re-writing; (c) a power line for conveying from a host computer system the high voltage required for erasing and re-writing the EEPROM; (d) an MPU that can be driven by a voltage supplied by the built-in battery; (e) an interface circuit that can be driven at a voltage supplied by the built-in battery; and (f) a switching circuit for selecting either the built-in battery or the power line as the power supply for the EEPROM.

Abstract: For reducing the area for read/write bus lines to a half and shortening the length of the read/write bus lines so as to speed up the operation, the locating positions of input/output circuits for the corresponding bits, of memory blocks MB1 and MB3a located to oppose to each other and to interpose therebetween an active circuit area ACA and of memory blocks MB2a and MB4 located to oppose to each other and to interpose therebetween the active circuit area ACA, are made different from each other. Read/write bus lines RWB1 to RWB4 of the same length are formed and located to interconnect between the inputs/outputs for the corresponding bits, of the opposing memory blocks, by traversing an empty region between circuit blocks CB in the active circuit area ACA, and in such a manner that each two read/write bus lines extend between the memory blocks MB1 and MB2a and between the memory blocks MB3a and MB4.

Abstract: A storage medium designed to simulate a standard information storage medium such as a floppy disk, video tape, or compact disc. A toy playback system accesses information stored on a printed circuit board, integrated circuit or other storage area, disposed on the storage medium. The storage medium comprises a plurality of memory locations each of which stores a sequence of analog or digital signals representative of a different block of stored information. Upon insertion into the toy playback system based upon user input, the printed circuit board or integrated circuit comes into selective contact with a contact plate, which activates the contacted memory location or locations to provide the selected information as sounds image, or video via a speaker, display screen, or combination thereof. The sound or audio information may be stored in a plurality of voice chips on the printed circuit board.

Abstract: An apparatus and method for loading software changes into a currency discrimination machine. In one embodiment, a flash card having a memory remotely programmed with a second software code is adapted to be removably electrically coupled to the currency discrimination machine. Insertion of the flash card causes the initial code in the resident memory of the machine to become erased and replaced with the second software code. The flash card may thereafter be removed from the machine and used to load software changes into other machines. In another embodiment, the flash card is adapted to be inserted and remain electrically coupled to the currency discrimination machine. Insertion of the flash card causes the machine to execute the second software code, but the initial code is not erased or replaced. Upon removal of the flash card, the machine does not retain the second software code but will revert to execution of the initial code.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.

Abstract: A circuit comprising a generation circuit for providing a clock signal. A number of compensation circuits may receive the clock signal and may present essentially simultaneously a compensated clock signal at their outputs. The compensated clock signals are generally presented to a plurality of synchronous external devices.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

Abstract: A receptacle for completing an electrical circuit between first and second devices, such as an electronic button and an interface circuit. The receptacle comprises a column moveable within a structure defining a channel having first and second ends, the column includes an electrically conductive contact engageable by the first device at the first channel end. An electrical terminal is spaced from the column at a second channel end, the electrical terminal being electrically connectable to the second device. A connector is electrically connected to the contact and extends within the channel toward the terminal, such that upon engagement of the contact by the first device, the connector electrically engages the terminal, thereby completing the electrical circuit between the devices. A second electrically conductive contact is located within the channel adjacent the column which is engageable by the first device.

Abstract: Each read line in a memory array containing a plurality of alternating bit lines and read lines with columns of memory cells therebetween, is broken into a plurality of electrically isolatable segments. As a result, the capacitance associated with each read line is significantly reduced and the speed of reading information from or writing information into a memory cell is significantly increased while at the same time not decreasing the density of the array.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.

Abstract: A PC card is provided through which data can be read and written at a high speed. When a system main unit reads data of one sector from a flash memory of the PC card, the relevant data of one sector from among the data of one block including the relevant data is written in a first RAM, and data of the other sectors is written in a second RAM. Since the system main unit can perform data input/output between it and the high-speed first RAM, the reading and writing speed of data is increased. If the first RAM is contained in a control apparatus and the data is allocated to the first RAM and the second RAM on the basis of the value of the register, it is possible to perform data input/output with ease.

Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.

Abstract: A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source.

Abstract: A game programming system uses rewritable cartridges that are compatible with commercially available game systems to produce game cartridges at a point-of-sale location so that retailers only need to stock sufficient uniquely designed game blanks to meet consumer demand. A game programmer or programming device loads digital content from computer storage to a rewritable game cartridge incorporating reprogrammable flash memory. The system includes flash rewritable cartridge identification hardware that allows verification of the cartridge to identify it as proprietary to a particular manufacturer or authorized dealer. The system provides for game content to be erased from the cartridge and new game content to be programmed so that the cartridge can be reused time after time to house any number of programs. During a cartridge write operation, a game programmer interface accepts data stored in a personal computer (PC) and fills first in first out (FIFO) memory.

Abstract: A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

Abstract: A memory module, such as a Single In Line Memory Module (SIMM), is provided which utilizes defective, substandard and/or unconventional memory devices to provide functionality that is equivalent to a memory module constructed with fully operational standard memory devices.

Abstract: A method and circuit for routing data to registers in an integrated circuit is disclosed. The circuit comprises an I/O port (100) for receiving data and address signals, and a plurality of distributed memory modules (200-900) having registers (210-217). Each memory module is associated with and located adjacent to a circuit functional block. All of the memory modules (200-900) are connected to the I/O port (100) via a single data bus (40).

Abstract: A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Abstract: A control apparatus and associated method for controlling an internal combustion engine of an automobile. A single chip microcomputer has a memory, which may be a programmable read only memory (PROM), for storing data and is operable in accordance with program data stored in the memory. The data may be stored in the memory after the microcomputer has been mounted on a circuit board. The control apparatus includes the microcomputer with its memory, a control unit for controlling the storing of program data into the memory, a plurality of input terminals for receiving the program data from an external source, and isolation circuitry for isolating the microcomputer during writing of program data into the memory. The microcomputer receives data from external sensors which sense operating conditions of the automobile and applies signals to external actuators to control operating conditions of the engine.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.

Abstract: A memory module includes a plurality of memory devices, each memory device including a plurality of memory cell arrays, a plurality of data input/output lines, and a memory cell array select input line. The plurality of memory cell arrays are arranged as a plurality of blocks such that data transfer is enabled between a memory cell array in each block of the plurality of blocks and a respective data input/output line of the plurality of data input/output lines when a predetermined voltage is applied to the memory cell array select input line. The module includes a circuit substrate on which the plurality of memory devices is mounted, the circuit substrate including first and second voltage busses.

Abstract: A checking circuit is provided which electrically and selectively connects a pad to which an internal circuit is connected, to a reference potential source node, in accordance with a potential of a special pad, when activated. The checking circuit is activated when a burn-in mode detection signal is activated. By detecting a leak current of a pin terminal to which the pad connected to the circuit is electrically connected, the potential of the special pad, that is, set internal function, can be externally identified. Accordingly, a bonding option function of which internal function is set in accordance with the potential of the bonding pad, can be externally detected in a non-destructive manner.

Abstract: A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal.

Abstract: A memory card has a printed circuit board which is connected to an interface connector, on which a memory device is to be mounted and which has a power line patterned thereon to supply a supply voltage to the memory device. A plurality of lines are directly connected to the power line on the circuit board and provided in association with the value of a supply voltage for the memory device. The individual lines consist of a plurality of lead lines having different layouts. The interface connector is connectable to the individual lines.

Abstract: An IC memory card capable of improving memory storage capacity and data processing speed by including a connector for interfacing with an external apparatus and providing 64-bits of data signals, 30-bits of address signals, and 8-bits of chip selection signals, which further includes a control unit for controlling read and write operations in accordance with control signals inputted via the connector; and a plurality of memory chips for inputting internal chip selection signals outputted from the control unit, being enabled by corresponding chip selection signals, and inputting/outputting data in accordance with the read and write signals outputted from the control unit.

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion.

Abstract: Systems and methods for connecting multiple memory modules to a computer system while controlling address bus and data bus loading and termination effects. In one form, the modules are connected to a printed circuit board carrying the address and data buses using dendrite enhanced bonds between module contacts and printed circuit board pads. The address bus loading which typically characterizes the addition of memory to a computer system is minimized through the inclusion of an address buffer module with each group of memory modules in a module expansion carrier. Data bus termination characteristics are controlled using jumpers within the modules. The invention is particularly suited for use with modules configured with chip edge interconnect technology, allowing the computer system user to expand the system memory without unduly effecting the address bus and data bus line characteristics.

Abstract: A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: An add-in or expansion cartridge is provided for insertion into a cartridge receptacle of an electronic device, such as a laser printer, the electronic device comprising a first plurality of circuit elements. The add-in cartridge comprises a circuit board having a second plurality of circuit elements mounted thereon, the circuit board comprising a plurality of grounding pads and connectors for electrically connecting the second plurality of circuit elements, which may include a processor, to the electronic device. A housing accommodates the circuit board and comprises an opening such that the connector extends through the opening for connecting the circuit board through the electronic device. A conductive shielding layer is arranged on at least one interior surface of the housing and substantially surrounds the circuit board to reduce emission of electromagnetic radiation. First and second grounding pads are arranged at first and seconds ends, respectively of the opening.

Abstract: A serial access, electrically erasable, programmable read-only memory (EEPROM) is used to store user program and data and is disposed in a memory cartridge. The memory cartridge cooperates a base or master Programmable Logic Controller (PLC) and may be used to download a program into one or more master PLC's, or to upload a program from a master PLC to memory cartridge. Each PLC may include at least one input terminal and at least one output terminal for receiving and transmitting signals, at least one microprocessor, at least one memory device, and a connector for accessing the at least one memory device.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.