Abstract: A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.

Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A semiconductor memory device that can be reduced in chip area while preventing degradation in characteristic is obtained. In DRAM, a plurality of memory cell array regions are arranged in matrix, spaced apart from each other in a row direction and in a column direction, on a semiconductor substrate. A sense amplifier region is arranged in a gap between the memory cell array regions in the column direction. An element forming a sense amplifier is arranged in the sense amplifier region. A subdecoder region is arranged in a gap between the memory cell array regions in the row direction. A cross region is arranged at an intersection of the sense amplifier regions in line and the subdecoder regions in line. A sense amplifier driver element is arranged in the subdecoder region and used in a sense amplifier operation.

Abstract: A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the word lines. Each memory cell comprises two first regions of the first conductivity type, each first region comprising the drains or the sources of first and third transistors, and being in contact with a second region of the second conductivity type comprising the drain or the source of a second transistor, the first and second regions being short-circuited by a conductive material, the conductive tracks of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.

Abstract: There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is comprised of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integrated and a lower electrical power as compared with those of the prior art device can be realized.

Abstract: A solid state memory device is fabricated by forming a level of the device; identifying defective areas in the level; and programming address logic of the level to avoid the defective areas in the level.

Abstract: A circuit topology for high-speed memory access. In one embodiment, an electronic circuit includes a memory controller. The memory controller is coupled to a memory module by a first plurality of transmission lines. The memory module may include a second plurality of transmission lines coupled to the first plurality. The memory module further includes a first memory bank coupled to the second plurality of transmission lines and a third plurality of transmission lines. A second memory bank may be coupled to the third plurality of transmission lines. Each of the first, second, and third pluralities of transmission lines may be part of a common bus.

Abstract: A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-multiplexer and pre-charging circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking using tilable strap cells in a first embodiment that provides a combined array, does not require routing and eliminates redundant reference columns.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: A double pitched array includes isolation devices to divide the array into subarrays, using the same space which is used for bit line twists. This addition allows the one-fourth of the bit line pair which will not be used to propagate signals to not be charged during a memory operation.

Abstract: A random access memory device includes a number of memory cells, with word lines, plate lines, and bit lines coupled to the memory cells. A switch, controlled by a word line, couples one end of the plate line to a first global plate line, while another switch, controlled by a second global plate line, couples the one end of the plate line to a reference voltage. The plate lines are charged by the first global plate line, which improves operational speed of the device and reduces loading of the word lines.

Abstract: A memory module socket having a transposed pinout allowing the socket to be mounted on the second, or reverse, surface of a motherboard and connected to circuit traces configured for mounting of a memory socket on the first, or processor, surface of the motherboard to correctly accommodate signals between the motherboard and the memory module is disclosed. A motherboard having at least one memory socket mounted on the second, opposing surface enhancing access to the memory socket or sockets for insertion and removal of memory modules for testing the memory modules in multimotherboard test systems is also described. The invention further includes a method of converting a conventional motherboard and memory socket assembly for such testing.

Abstract: A memory module socket having a transposed pinout allowing the socket to be mounted on the second, or reverse, surface of a motherboard and connected to circuit traces configured for mounting of a memory socket on the first, or processor, surface of the motherboard to correctly accommodate signals between the motherboard and the memory module is disclosed. A motherboard having at least one memory socket mounted on the second, opposing surface enhancing access to the memory socket or sockets for insertion and removal of memory modules for testing the memory modules in multimotherboard test systems is also described. The invention further includes a method of converting a conventional motherboard and memory socket assembly for such testing.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: A semiconductor memory device includes a plurality of first wirings extending in a first direction, a plurality of memory elements connected with the first wirings, a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements, and first transistors or diodes connected between two adjacent of the second wirings.

Abstract: A circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line. In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: A memory cell which provides a diffusion path for hydrogen to the transistor is disclosed. The diffusion path is provided by forming a contact in which the upper section overlaps the lower section, thus creating a gap that serve as a hydrogen diffusion path. The hydrogen diffusion path is necessary for annealing the damage to the gate oxide.

Abstract: Memory systems and methods of making the same are described. In one aspect, a memory system may includes multiple memory layers that may be identical when manufactured and may be readily customized before or after the layers are arranged into a three-dimensional stack so that data may be sent to or retrieved from individual layers (either serially or in parallel) independently of the other layers.

Abstract: A random access memory cell (10) includes a first conductor line (12) and a second conductor line (14). A native device (16) is arranged to store charge. A high voltage threshold transistor (30) couples the native device to the first and second conductors.

Abstract: A double pitched array includes isolation devices to divide the array into subarrays, using the same space which is used for bit line twists. This addition allows the one-fourth of the bit line pair which will not be used to propagate signals to not be charged during a memory operation.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.

Abstract: A non-volatile semiconductor memory capable of suppressing the occurrence of disturb failure during erase operation is provided by arranging as follows. Bit lines (BL) extend in the row direction of a matrix. Gate electrodes (9) are disposed on a channel region (CH). The non-volatile semiconductor memory comprises plugs (10) for connecting the gate electrodes (9) and word lines. The word lines at each row have two sub-word lines (WL). The first pair of sub-word lines (WL1a, WL1b) and the second pair of sub-word lines (WL2a, WL2b) belong to the same row, respectively. The first sub-word line of the first pair (WL1a) is in contact with first plugs (1012, 1014), the second sub-word line of the first pair (WL1b) is in contact with second plugs (1011, 1013), the first sub-word line of the second pair (WL2a) is in contact with third plugs (1022, 1024), and the second sub-word line of the second pair (WL2b) is in contact with fourth plugs (1021, 1023).

Abstract: The semiconductor device has a plurality of basic units, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element having second and third gate electrodes, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor and the third gate electrode. A semiconductor device having a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration is provided.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.

Abstract: A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided, in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides of the sense amplifier array are connected to one another by wiring using the common electrodes.

Abstract: A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.

Abstract: An apparatus and method of operating an open digit line and a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell, in one embodiment, has an area of 6F2. One method comprises, storing a first bit in a first memory cell and storing a second bit that is complementary to the first bit in a second memory cell. The first bit and the second bit form a data bit. The data bit is read by comparing a voltage difference between the first memory cell and the second memory cell.

Abstract: A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure.

Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A semiconductor device includes a plurality of bitlines arranged in an array, the plurality of bitlines being grouped in pairs and at least some of the bitlines include a twist. A twist region is disposed along the plurality of bitlines wherein the twist region occupies layout area designated for the twists. An equalizer element is disposed in the twist region for equalizing a pair of bitlines.

Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A two-dimensional memory comprises a matrix of multi-valued resonant tunneling diodes (RTD). Each memory cell has two series RTDs with hysteretic folding V-I characteristics. The memory state is determined by the node voltage between the two RTDs and the series current. Each memory cell has two terminals connected to two bit lines through word line switches. The two bit lines are fed with two sets of multi-valued data and are written into the cell by two consecutive pulses to set the operating point. The two sets of multi-valued data are converted by two D/A converters from two sub-words of the binary digital word. The memory state is read by the sensing the voltages at the two terminals, or voltage at one terminal and the current through the other terminal.

Abstract: An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry.

Abstract: CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a way that they block and dissipate the erroneous signal. The added transistor structures are made immune to SEU by placing them in well diffusions that are separate from the rest of the circuit and biasing those wells such that the electric fields surrounding the transistors are very low in comparison to the rest of the circuit. Signal blocking is achieved with an SEU immune transistor that is in an “off” state whenever other circuit transistors that deliver signals through it are potentially sensitive to SEU. Dissipation is achieved with either a resistor or low current drive transistor that spreads the SEU signal out over time thereby reducing its voltage change to an acceptable level.

Abstract: A semiconductor device includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.

Abstract: A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. A first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.