Abstract: Each nonvolatile memory cell transistor has such directivities that a current flows only from the drain to the source and that charge is exchangeable only at the source. The source of one of a pair of memory cell transistors connected to each word line is connected to the drain of the other memory cell transistor, and the drain of the one memory cell transistor is connected to the source of the other. During a data rewrite operation, reverse voltages are applied to the sources and drains of the pair of memory cell transistors. Because of the directivities of each memory cell transistor, charge is exchanged with a charge accumulation layer only in the source region. This makes the data rewritable in only one of the pair of memory cell transistors. As a result, data is rewritable on a memory cell basis without increasing the memory cell size.

Abstract: Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.

Abstract: A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.

Abstract: First active regions and second active regions intersecting the first active regions at a right angle are defined on the surface of a semiconductor substrate, and diffusion regions are formed in the first and second active regions to interpose an intersecting region therebetween. Then, a gate structure is formed linearly to extend over the intersecting region at a non-zero angle with respect to the first and second active regions. Further, terminals to be connected to metal interconnects are provided on the diffusion regions at a non-zero angle with respect to the first and second active regions, respectively. Consequently provided is a nonvolatile semiconductor memory having a simple gate structure capable of storing 4-bits of information in one memory cell.

Abstract: A semiconductor memory device that includes a memory cell array with memory cells arranged in rows and columns. The memory cells can also be formed in blocks. A plurality of word lines are applied voltages received by a plurality of drive lines, the plurality of word lines being classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than the arbitrary word line in the secondary adjacent word lines. A plurality of transfer transistors are utilized to select the plurality of word lines or blocks. Among the plurality of transfer resistors, transfer transistors for the residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for the arbitrary word line.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

Abstract: A multi-port static random access memory for reducing an occupation area of a layout memory cells on a substrate having the improvements from a first plurality of metal electrode layers on a first plurality of active regions included in one unit cell and in other unit cell neighbored to the corresponding one unit cell of the first plurality of metal electrode layers being commonly connected to the power supply source, comprises: a second plurality of the metal electrode layers on second plurality of the active regions and to be independently and separately connected to the power supply source, by every one unit cell in cell array.

Abstract: A memory system includes a first plurality of memory cells, wherein each of the first plurality of memory cells includes a first node and a second node that are configured to have opposite logic values, and a second plurality of memory cells, wherein each of the second plurality of memory cells includes a first node and a second node that are configured to have opposite logic values. Providing a pre-program data value to the first nodes of the first plurality of memory cells, and to the second nodes of the second plurality of memory cells enables the memory system to be pre-programmed.

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: A flash memory can operate by providing a first voltage level from a row decoder to a wordline associated with a cell of a flash memory device. An address provided to the row decoder is decoded during an erase mode operation of the flash memory. The first voltage level is increased to a second voltage level provided from the row decoder to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n?1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read, out from each dummy memory cell, a potential Va is developed on a bit line BL2n?1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n?1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn?1 and SAn as a reference potential.

Abstract: A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.

Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Abstract: A non-volatile memory array structure, comprising a plurality of first transistors, serving for memory function, being arranged to have a plurality of columns and a plurality of first rows. The first transistors in each column are coupled in series, and adjacent two of the columns are grouped into a memory group using a common bit line. The gate electrodes of the first transistors in the same first row are coupled with a first sequence word line. A plurality of second transistors are also included. Each of the second transistors is coupled between two columns of the memory group and is adjacent to each of the first rows. The second transistors form a plurality of second rows, wherein gate electrodes of the second transistors in the same second row are coupled to a second sequence word line.

Abstract: The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.

Abstract: A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.

Abstract: A simply structured, and highly reliable semiconductor apparatus having a large storage capacity. The apparatus has a plurality of memory cells on one semiconductor substrate, each including a capacitor having first and second electrodes, and a switching device having a control terminal connected to a corresponding word line among a plurality of word lines, and a current channel connected between the first electrode and a corresponding bit line among a plurality of bit lines. When the semiconductor apparatus is in a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is in a second mode, an OFF potential of the word lines is set to be a second potential, and a current channel of the switching device is set in a direction vertical to the semiconductor substrate.

Abstract: A circuit topology for high-speed memory access. In one embodiment, an electronic circuit includes a memory controller. The memory controller is coupled to a memory module by a first plurality of transmission lines. The memory module may include a second plurality of transmission lines coupled to the first plurality. The memory module further includes a first memory bank coupled to the second plurality of transmission lines and a third plurality of transmission lines. A second memory bank may be coupled to the third plurality of transmission lines. Each of the first, second, and third pluralities of transmission lines may be part of a common bus.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: A multi-port semiconductor memory device includes a plurality of memory cells, each having a first bitline pair and a second bitline pair, and a plurality of flipped memory cells, each having a first flipped bitline pair and a second flipped bitline pair. The memory cells and the flipped memory cells are alternately arranged in a row direction, and a predetermined preparatory memory cell is arranged between the memory cell and the flipped memory cell that are adjacent to each other at a predetermined position in the row direction. In particular, the preparatory memory cell connects the first bitline pair of the memory cell to the second bitline pair of the flipped memory cell and connects the second bitline pair of the memory cell to the first bitline pair of the flipped memory cell.

Abstract: Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer, and epitaxial layer include voltage contacts that allow for the wells to be biased to a de voltage level. The memory cell includes a transistor which is formed on the epitaxial layer, the transistor including a source and drain region separated by a channel region. The trench bit line is formed within the buried layer, and is coupled to the drain region of the transistor by a bit contact.

Abstract: A NOR array includes a first plurality of word lines, a second plurality of bit lines and a third plurality of common lines. Each word line connects to the gates of a row of nitride read only memory (NROM) cells. Each bit line connects to one diffusion area of each NROM cell in a column of the NROM cells and each common line connects to the other diffusion areas of each NROM cell in a row of the NROM cells.

Abstract: A semiconductor memory device includes a memory cell array in which memory cells each having six transistors 11a, 11b, 12a, 12b, 13a and 13b are arranged two-dimensionally on a semiconductor substrate. The semiconductor memory device also includes a plurality of word lines connected to each of the memory cells, and arranged on a parallel to each other along a first direction, a plurality of bit lines connected to each of the memory cells and arranged on a parallel to each other along a second direction perpendicular to the first direction, and at least two gate electrodes provided on the semiconductor substrate such that each of the gate electrodes is connected to at least one transistor of the six transistors, all of the gate electrodes 3a, 3b, 3c and 3d being arranged on the same straight line parallel to the first direction.

Abstract: This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.

Abstract: A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices or other types of products. The memory device cell can comprise a first conductive line, a second conductive line, a first active area, a second active area, a third active area, and a fourth active area. The first conductive line includes a first gate, a second gate, a first contact and a second contact. The second conductive line includes a third gate, a fourth gate, a third contact and a fourth contact. The first active area is electrically coupled to the first gate and the third contact; the second active area is electrically coupled to the second gate and the fourth contact; the third active area is electrically coupled to the third gate and the first contact; and the fourth active area is electrically coupled to the fourth gate and the second contact. The memory cell device, for example, can be a cell for an SRAM device.

Abstract: There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a data buffer, and a sense amplifier between several segments of an array of FeRAM memory cells associated with a plurality of plate lines and/or word lines of the array. Various combinations of segmented bit lines, segmented plate lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.

Abstract: Briefly, in accordance with one embodiment of the invention, a first integrated circuit having control circuitry is bonded to a second integrated circuit having a memory array. The control circuitry of the first integrated circuit being adapted to access, at least in part, data stored in the memory array of the second integrated circuit.

Abstract: Information processing speed is increased to about two times the speed in the related art. Even defects are partially included, memory cells other than the defective ones effectively used such that memory ICs with an enhanced yield are provided. A memory IC having bit lines through which data can be written and read at pairs of memory cells, is equipped with a pair of N-type MOS transistor N-Tr1 and P-type MOS transistor P-Tr2 that have gates commonly connected to each identical one of the word lines, and either sources thereof or drains thereof commonly connected to each identical one of the bit lines, capacitors that have electrodes on one side thereof respectively connected to the sources or the drains of the transistors that are not connected to the bit line BL and electrodes on the other side thereof commonly connected to a plate electrode of the memory IC, and an operation circuit that freely, selectively writes and reads data in and from either one of the one pair of the memory cells.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of the plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to the plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among the plurality of word lines and the plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than said arbitrary word line and the secondary adjacent word lines, and wherein among the

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A magnetic random access memory (MRAM) cell and a memory array formed from the MRAM cells are disclosed. The MRAM cell includes a magnetic tunneling junction and a transistor. The magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The gate of the transistor is coupled to a first end of the magnetic tunneling junction. The source of the transistor is coupled to a second end the magnetic tunneling junction. The drain of the transistor is coupled with an output for reading the magnetic memory cell. During reading, a read current is applied to the magnetic tunneling junction and the transistor is preferably operated in a saturation region.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.