Abstract: A diagnostic device that may be included in a superior-level application, for example as an ActiveX component with a software interface standardized for this purpose. The superior-level application may be a visualization application of a control application or a visualization at the control level. The diagnostic device receives diagnostic data for a field bus from a field bus switching component. The diagnostic data is transmitted via a PLC I/O bus and interfaces provided in the PLC, without the need to parameterize or program either the control application or the visualization application.

Abstract: The invention relates to a bus system for transmitting data between a processing unit (10) and a memory unit (19) comprising memory cells (17), in which a plurality of logic addresses is available for each memory cell (17). Dependent on the kind of address used, the data transmitted through the data bus (13) are differently manipulated by a data modification unit (16) so that, for protection against abuse of data, the unchanged identical data are not present at the data bus (13).

Abstract: At each node of the data transmission/reception system of the present invention on a bus of an IEEE 1394, the following operations are sequentially performed: necessary initialization at the time of bus resetting; and GUID acquisition, restoration of Broadcast-out connection, restoration of Broadcast-in connection, and restoration of Point-to-point connection according to a restoration connection queue registering an execution order of respective connection restoration operations if there is a PENDING status of each connection before a passage of a predetermined time, after the bus resetting. Moreover, the restoration of each connection is subdivided into a plurality of processing steps when necessary, and controlled to select a proper processing step.

Abstract: An instrumentation system which extends channel-based switched fabric architectures to provide instrumentation signaling functions. The system comprises a chassis including slots for receiving inserted modules. The chassis includes a backplane which provides for inter-module communication, including a channel-based switched fabric bus, such as the InfiniBand bus, and instrumentation signaling lines for instrumentation signaling functions.

Abstract: A communications protocol for a communications bus wherein messages are transmitted to a plurality of devices communicating by means of a bus. Each message includes a unique code indicating the end of the message and that same unique code triggers a transfer of communications control to another device of the plurality of devices.

Abstract: A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency.

Abstract: A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency.

Abstract: Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.

Abstract: A communications system capable of providing enhanced data integrity and reliability through redundant buses, and a network interface controller for use therewith. Redundant conductors conforming to well-known ethernet standards interconnect electronics components. Each component communicates with the conductors through a single network interface card (NIC). Each NIC comprises an ethernet compliant transceiver for each ethernet conductor in communication with the component. Microcontrollers embedded in each NIC synchronously and deterministically place data on the ethernet conductors according to a timing scheme stored in a non-volatile memory means. A heartbeat/power monitor is also provided to ensure that data cannot be transmitted in the event of a microcontroller failure. The communications system provides a high degree of redundancy and fault-tolerance and is therefore well-suited to critical applications in avionics communication.

Abstract: In a system for carrying out communication between a plurality of apparatus connected using an IEEE 1394 serial bus etc., command register addresses are fixed from "FFFF F000 0B00h" to "FFFF F000 0D00h" and response register addresses are fixed from "FFFF F000 0D00h" to "FFFF F000 0DF0h". These addresses are then common to all of the apparatus connected to the bus. Then, while an arbitrary apparatus on the bus is sending a command to all of the remaining apparatus, the address of the command register is included in the command and this command is transmitted as a broadcast communication. This command is then stored at a command register having a common address within the apparatus that received the command. Thus, time setting and state setting etc. of each apparatus can be achieved.

Abstract: A controller circuit (107) between a transceiver (104) and an RS232communication port (103) provides wireless communication to a remote unit and includes a transmitting and receiving mode indicator (503), a first delay circuit (506) for delaying a packet of data (501) before being transmitted, a timer (502) counting a period of time during which delaying termination of transmitting mode following a last data bit of the packet of data (501). Further, a receive signal detector (504) produces a carrier detect signal (521) and its delayed version (525) through a second delay (522) when a data packet (520) is received from the transceiver (104), first and second AND gates (523, 528) and a third delay circuit (526) receive signals (525and 520) to produce a reformatted received data packet (529) compatible to the RS232format for input to the RS232communication port (103).

Abstract: A data bus system is disclosed, including a plurality of nodes coupled together by a daisy chain bus. Each node includes a first and a second bus connection, each having a first and second bidirectional terminal. An arbitration logic is coupled between the first and second bus connection. The node operates in an arbitration mode, during an arbitration time interval, in which the first bidirectional terminal in the first bus connection, and the second bidirectional terminal in the second bus connection are configured to be input terminals, and the second bidirectional terminal in the first bus connection and the first bidirectional terminal in the second bus connection are configured to be output terminals. Then the node operates in a bus access mode in which the first and second bidirectional terminals in the respective first and second bus connections, are both configured to be one of input and output terminals.

Abstract: An improvement to a half duplex multipoint communication environment enables the full duplex communication of information between a control modem and any one of a plurality of remote modems at any given time. This is accomplished by providing a system for echo cancellation in a multipoint communication environment whereby a first modem having a first echo canceler for canceling the echo on a transmission line and a plurality of additional modems each having an echo canceler are connected to the same copper wire pair. The presence of an echo canceler in each modem connected to the transmission path enables the full duplex exchange of information between the control modem and one of the remote modems at any given time.

Abstract: A communication interface 122 for a network having a plurality of nodes 100-108 and a communication link 124,126 (120) connected between predetermined ones of the nodes 100-108 which propagates bus data, includes a first shared communication circuit 128, to be connected in series with the link 124,126, which receives the bus data and passes shared data along the link 124,126, a second shared communication circuit 136,142, connected to one port 129 of the circuit 128, which receives the bus data from the link 124,126 and passes the shared data, and which receives the shared data and couples the shared data onto the link 126, a first unshared communication circuit 144,148, connected to the port 129 of the circuit 128, which receives the bus data from the link 126 and passes the unshared data, and which receives the shared data and couples the unshared data onto the link 126, a second unshared communication circuit 130,134, connected to another port 127 of the circuit 128, which receives the bus data from the li

Abstract: A method and apparatus for viewing a configuration of a computer network by polling a plurality of switches and routers present in the network to obtain copies of information stored in databases on the switches and routers. The present invention determines from this combined database is the status of the links, switches and routers, as well as uses software tools to determine the status of the network and its devices. The devices are then graphically displayed according to physical connectivity and status. Each status being displayed differently.

Abstract: A system, device, and method for sharing contention mini-slots among multiple priority classes determines an aggregate feedback state for each of the priority classes, determines a preferred allocation of contention mini-slots for each of the plurality of priority classes using the aggregate feedback state, and determines an actual allocation of contention mini-slots for each of the plurality of priority classes using the preferred allocation. The actual allocation of contention mini-slots is determined by making a preliminary allocation for each of the priority classes based on the preferred allocation and then allocating any remaining contention mini-slots among the priority classes.

Abstract: A method for communicating information from a first integrated circuit (IC) to a second IC. A sync signal is transmitted between the two IC's to indicate the start of a transmission of a frame of information from the first IC to the second IC. In this case, a frame of information includes a tag slot and a plurality of data slots. The tag slot contains a series of tag bits wherein each tag bit is associated with a data slot. The value of each tag bit indicates whether its corresponding data slot contains valid or invalid data. The first IC sends the tag slot and data slots to the second IC.

Abstract: A number of domestic audio/video apparatuses (10-14) are connected to a serial control bus (D2B, 16). Each apparatus is addressable via the bus as a device and contains functional elements addressable on subdevices. One apparatus (14) includes an on-screen display subdevice (41) and a first control subdevice (24). Subdevice status messages are defined whereby a control subdevice can ask to be informed of the status of a further subdevice (e.g. 26), and in particular to be informed automatically of any change in status without the need for continuous polling of subdevices. The subdevice status messages can be used to obtain early confirmation of a signal path being established through the system.

Abstract: An arbitration switching system and a method of arbitration switching in a high-speed packet switching system uses a subscriber input/output device, an arbitration switching system and a parallel common bus part for the purpose of point-to-point communication point-to-multipoint communication and transferring packets generated in each node. A system bus structure is based on a parallel common bus type. Furthermore, to accommodate high-speed arbitration switching, operations such as polling, arbitration and switching are processed in parallel. Therefore, bus use efficiency is high, and a bus-extension can be easily achieved. A star LAN may be realized because broadcasting and multicasting are supported. An internal high-speed network for interlock in large-scaled communication systems that need high-speed switching can also be provided.

Abstract: A private communication system using bus type transmission path, in which a plurality of communication terminal devices for carrying out communications and a system main device for exchanging communications from the communication terminal devices are connected by upward and downward digital transmission paths for transmitting data in forms of upward and downward transmission frames formed by a plurality of cells in fixed length.

Abstract: An apparatus and method to implement a hybrid contention and polling protocol for a communications or computer network is disclosed.

Abstract: A method for arbitrating for control of a network medium for transmission, combining aspects of the time slots and collision-based arbitration schemes by dynamically modifying the scheme used in accordance with network load. In a preferred embodiment, this is done by assigning time slots to the various nodes and arbitrating using the time slots when the network is free. If there are no requests for use of the network after a predefined number of time slots, any node can immediately access the network using a collision-detection method without being required to wait for a time slot arbitration procedure.

Abstract: A single channel communication bus system has stations which communicate with each other via the bus. Each station must have a unique address which is initialized during a system initialization. In order to facilitate initialization, a manufacturer-determined address is stored in a non-volatile memory. Search for a unique address for each station begins with the address stored in the non-volatile memory.

Abstract: A communication system interconnecting n slave processors (P1, P2, . . . , Pn) and a master processor (Pn+1) includes a first data communication bus, a second serial signalling bus, which acts as a conduit for a synchronous signalling frame, which consists of time intervals (IT) assigned to the processors, and circuitry for synchronizing the time intervals in the processors. In addition, n first comparing circuits, each associated with one of the slave processors, are provided for detecting the cyclic appearance of the IT assigned thereto. A second comparing circuit associated with the master processor indicates the cyclic appearance of a respective IT.

Abstract: A data transmission system for a vehicle includes a plurality of control systems installed on the vehicle, and a network bus connecting the plurality of control systems with each other for circulating a transmission right through the plurality of control systems to thereby perform transmission of a message between the plurality of control systems. According to a first aspect, each of the control systems starts transmitting data when it is detected that the transmission right is not generated or lost from the system, and continues transmitting the data when no collision of data transmitted from the present control system with data transmitted from the rest of the plurality of control systems, or when by mediation for avoiding the collision is detected, it is determined to continue data transmission.

Abstract: A data transmission system for a vehicle includes a plurality of control systems installed on the vehicle, and a network bus connecting the plurality of control systems with each other for circulating a transmission right through the plurality of control systems to thereby perform transmission of a message between the plurality of control systems. According to a first aspect, each of the control systems starts transmitting data when it is detected that the transmission right is not generated or lost from the system, and continues transmitting the data when no collision of data transmitted from the present control system with data transmitted from the rest of the plurality of control systems, or when by mediation for avoiding the collision is detected, it is determined to continue data transmission.