Abstract: A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels is configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunciations interface. A PDH traffic interface receives PDH channel signals from a plurality of PDH channels and a bit-pipe interface receives bit-pipe traffic transported as a packet data stream. A composite signal generation module and interface then creates, outputs and receives a single composite serial data stream including, in a single composite format, information from the received PDH channel signals as well as the packet data stream. The rate of the bit-pipe traffic may be adaptively modulated as a function of the composite rate.

Abstract: A network component comprising a processor configured to implement a method comprising promoting transmission of a first frame comprising a first timestamp associated with a transmission time of the first frame, recognizing a reception of a second frame having a reception time, wherein the second frame comprises a second timestamp comprising a downstream node delay associated with a downstream node, measuring a total delay between the transmission time of the first frame and the reception time of the second frame, and calculating a transport delay using the total delay and the downstream node delay. Also disclosed is a clock synchronization method comprising receiving a first frame comprising a first timestamp associated with an upstream clock at a reception time, sending a second frame at a transmission time, and measuring a downstream node delay between the reception time and the transmission time, wherein the second frame comprises the downstream node delay.

Abstract: A transmitter device that repeatedly transmits an identical frame includes a circuitry that generates the frame and transmits the frame a plurality of times. The frame includes marking areas that divide the frame into a plurality of frame segments having different lengths. The marking area is formed in the frame by part of the frame and is distinguishable from other parts of the frame. The marking area does not change data content transmitted by the frame. The frame segments obtained from the identical frame that is repeatedly transmitted by the circuitry are combined to reconstruct a complete frame identical to the frame transmitted by the transmitter device.

Abstract: A control signal receiver includes a converting circuit and a synchronization detection circuit. The converting circuit generates a complex control symbol stream including transmission configurations by converting an input signal. The synchronization detection circuit generates a first bit stream by applying a first determination criterion to the complex control symbol stream and generates a first synchronization signal by comparing the first bit stream with a reference synchronization word. The synchronization detection circuit generates a second bit stream by applying the first determination criterion and a second determination criterion to the complex control symbol stream in that order and generates a second synchronization signal by comparing the second bit stream with the reference synchronization word. The synchronization detection circuit outputs one of the first synchronization signal and the second synchronization signal as asynchronization enable signal.

Abstract: A barrier synchronization apparatus includes a receiving device which transmits a first synchronization signal to a synchronization device when the first synchronization signal in which a transmission destination is set in advance according to setting conditions including an algorithm of the barrier synchronization and an execution condition is received. A synchronization device synchronizes n first synchronization signals which are set in advance according to the setting conditions, wherein n is a positive integer, and designates transmission of m second synchronization signals in which transmission destinations are set in advance according to the setting conditions after the synchronization is established, wherein m is a positive integer. A transmitting device transmits the second synchronization signals to m transmission destinations set in advance, when a transmission designation information indicating the transmission designation is received from the synchronization device.

Abstract: Methods and systems for integrated transcoding on a plurality of data channels to convert one or more data channels from an incoming encoding format to an outgoing encoding format are disclosed.

Abstract: A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.

Abstract: A detector receives detects a first known signal in a packet signal. An LTF correlation unit performs correlation processing on the packet signal received by a receiving unit. Upon detecting the arrival timing, an update correlation unit terminates a first window and performs correlation processing on the packet signal received by the receiving unit, in a second window. When correction timing is detected and when correction timing is more likely to be accurate than the arrival timing, an estimation unit changes the correction timing to the arrival timing; when the arrival timing is more likely to be accurate than the correction timing, the estimation unit maintains the arrival timing.

Abstract: The present invention relates to an apparatus and method for estimating a channel in a MIMO wireless telecommunication system supporting the 0FDM/0FDMA. The present invention, in estimating a channel by using two or more pilots included in at least one received signal among received signals of a first channel and a second channel received through a first receiving antenna and received signals of a third channel and a fourth channel received through a second receiving antenna, determines a subchannel mapping rule respectively for the received signals of the first channel to the fourth channel, and estimates a channel with a different method according to the determined subchannel mapping rule.

Abstract: There is provided a node device having a plurality of transmission lines, included in a network, the node device including a first clock extracting section configured to extract a clock from a first packet used for synchronization of a clock in the node device, the first packet being received from the network through the transmission line, a second clock extracting section configured to extract a clock from a signal received from the network through the transmission line, and a clock selector to select a clock out of the clock extracted by the first clock extracting section and the clock extracted by the second clock extracting section, wherein the clock selected by the clock selector is used for synchronization of a clock in the node device.

Abstract: Maintaining communication between a mobile terminal and a network in a mobile communication system is achieved by determining a transition to one of a synchronized state and an unsynchronized state with a network while maintaining an active state with the network, and transitions to one of the synchronized state and the unsynchronized state according to the determination.

Abstract: A system and method for accounting for delay to accurately schedule a data packet for transmission between communicating devices. According to an aspect of the invention, a data packet to be scheduled is identified and the packet modified time, reflecting an estimation of the transmission time of the packet, and the scheduled transmission time, reflecting the time the packet should be scheduled to be transmitted, are calculated. A time stamp in the packet is adjusted to reflect the packet modified time and the packet is stored until either the packet modified time or the scheduled transmission time, when the packet is then transmitted.

Abstract: A slave communication device may transmit a packet to the master communication device, with the packet including a transmission time field and a correction field. The transmission time field may contain a value indicative of an approximate time of transmission of the packet by the slave communication device, and the correction field may contain a value indicative of a difference between the approximate time of transmission and an actual time of transmission of the packet by the slave communication device.

Abstract: A communication apparatus includes a data processing unit and a communication unit. The data processing unit performs a clock synchronous process between the communication apparatus and a communication correspondent apparatus. The communication unit performs communication with the communication correspondent apparatus. The data processing unit compares, when the clock synchronous process is performed, an offset window that defines a permissible delay time range of a packet applied to the synchronous process and a network delay time of the synchronous packet, selects the synchronous packet having the network delay time within the offset window, and applies phase offset information calculated from the synchronous packet, to perform phase control, and decreases a width of a current offset window when the network delay time of the synchronous packet is within the current offset window and increases the current offset window width when the network delay time is outside of the current offset window.

Abstract: Various implementations are described herein for providing unified user experiences using data attributes and data models. By referencing structural information of data attributes included in data models, users are able to interact with and/or view related data stored in different databases. Contextual information for the different databases, data attributes, and data models provide a seamless unified user experience when running reports, scripts, web controls and so forth associated with the related data.

Abstract: A transmission system is provided in a synchronous network, for establishing synchronization with a degree of precision and at a speed being comparable levels as a conventional technique, and further decreasing the probability of out-of-synchronization occurrence. In the present invention, a synchronization signal is detected without performing error correction until synchronization is established, and after the synchronization is established, it is monitored whether or not out-of-synchronization occurs, according to the synchronization signal that has been subjected to the error correction.

Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Abstract: Generate a series of digital data according to a pair of differential signals received from a low speed universal serial bus. Calibrate coarsely a frequency of an oscillator according to a width of an end-of-packet of the series of digital data. And calibrate finely the frequency of the oscillator according to a width of a SYNC pattern of the series of digital data.

Abstract: The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.

Abstract: When sending data, an ECU sends time lag information indicating a time lag that is a difference between time of generating time point at which the data is generated and time of sending start time point at which the ECU actually starts sending the data. When transferring the data, a relay apparatus adds time lag information indicating a time lag that is a difference between time of receiving start time point at which the relay apparatus starts receiving the data and time of transferring start time point at which the relay apparatus starts transferring the data, onto the time lag added on the received data. When receiving the data, an ECU determines for the received data the time of the generating time point that is earlier the time lag indicated by the time lag information of the received data than the time at which the ECU starts receiving the data.

Abstract: Devices, systems and methods of selecting a station of a wireless network to perform the role of the wireless network controller or control point. The station may receive a request to check the capabilities of the station in order to select the wireless network controller wherein the request includes sending station capabilities values. The station checks the station capabilities by comparing the station self capabilities values with the sending station capabilities values in descending capabilities priority order and if the station capability value is higher than the sending station capability value then the station may selects the station with the highest capability value as the wireless network controller.

Abstract: Two preamble partition schemes are provided for flexible network deployment and efficient utilization of limited cell identification resources in a wireless network. In a soft partition scheme, the entire preamble sequences are partitioned into several configurable non-overlapping subsets, and each subset is associated with a corresponding cell type. In a hybrid partition scheme, a combination of fixed and configurable subsets is used for preamble partition. The partitioning information is carried in a broadcasting channel broadcasted from base stations to mobile stations. In one embodiment, after a mobile station performs scanning and synchronization with a first base station, it derives the cell type of the first base station from cell identification and partitioning information. The mobile station completes ranging and network entry with the first base station if the cell type is preferred, and starts to perform scanning and synchronization with a second base station if the cell type is non-preferred.

Abstract: A simplified bus arrangement using only three signal lines allows TDM data to be conveyed to or from a number of slave-only devices without the use of separate command line(s) and without any of the slave-only devices having to operate as a bus master or even support a master operating mode.

Abstract: Methods and apparatuses are provided for facilitating distributed transmissions among a plurality of access terminals for a transmission sequence. An access point may assign a predecessor transmitter device for each of a plurality of access terminals, and may transmit to each access terminal an instruction to follow a respective preceding transmission by the predecessor transmitter. An access terminal may receive the transmission including the instruction, and may monitor for and detect the preceding transmission. The access terminal may then transmit a transmission after the completion of an interframe space that may follow the detected preceding transmission.

Abstract: In one embodiment, a battery-operated communication device “quick-samples” a frequency hopping sequence at a periodic rate corresponding to a substantially low duty cycle, and is discovered by (e.g., attached to) a main-powered communication device. During a scheduled sample, the main-powered communication device transmits a control packet to be received by the battery-operated communication device, the control packet containing timing information and transmitted to account for worst-case clock drift error between the two devices. The battery-operated communication device responds to the control packet with a link-layer acknowledgment containing timing information from the battery-operated communication device. Accordingly, the two devices may re-synchronize their timing based on the timing information in the control packet and acknowledgment, respectively.

Abstract: Sub-microsecond time transfer in a GPS/GNSS receiver using a weak GPS/GNSS signal is provided. The digitized complex baseband signal and the generated PN code are cross-correlated for each code period so as to output a complex correlation value at each code epoch of the generated PN code, where a sequence of the output correlation values form a data stream representing the navigation message. Bit synchronization generates bit sync pulses at bit boundaries. The location of a target segment having a known sequence at a known bit location in the navigation message is detected by searching through a plurality of subframes and accumulating search results for the plurality of subframes. Transmission time of the target segment is determined from the detected location of the target segment, with a certain time ambiguity. Accurate local time is determined by solving the time ambiguity using approximate time obtained from an external source.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: A system and method for redundant synchronizing to a reference clock for data communications. A determination is made whether a first data stream and a second data stream are available. The first data stream and the second data stream are received through opposing directions of a communications ring. A first data packet and second data packet are received at a remote node in response to the first data stream and second data stream being available. A timing characteristic of the first data packet and the second data packet correspond to a tick of a reference clock. The tick of the reference clock is extracted utilizing a timing characteristic of the first data packet or second data packet in response to the first data stream or the second data stream being available. A secondary clock is disciplined with the reference clock by adjusting the secondary clock based on a difference between times measured by the reference clock and the secondary clock to generate a clock signal.

Abstract: A method and apparatus for enhancing frame alignment using cyclic redundancy check (“CRC”) corrections are disclosed. In one embodiment, a process of frame alignment searches a predefined bit pattern within a first multi-frame structure and provides an assumed frame boundary after identifying the predefined bit pattern in the first multi-frame structure. While calculating a CRC value in response to the assumed frame boundary, the process further corrects the CRC value in accordance with a saved residue and F-bits identified by the assumed frame boundary. The assumed frame boundary is subsequently verified by comparing the calculated CRC value with embedded CRC value obtained from a second multi-frame structure.

Abstract: A method for synchronizing the direct mode TDMA transmission of a set of radios by following a selected radio as the leader includes: receiving, by a radio, a communication from an other radio; identifying, by the radio, a leader according to a leadership election rule using the received communication from the other radio and a current leader information; setting, by the radio, the identified leader as its leader; and synchronizing, by the radio, a time slot boundary with a time slot boundary defined by the leader.

Abstract: A technique includes determining a first difference between a time that a first network element of a seismic acquisition network receives a first frame pulse from a second network element of the seismic acquisition network and a time that the first network element transmits a second frame pulse to the second network element. The technique includes determining a second difference between a time that the second network element receives the second frame pulse and a time that the second network element transmits the first frame pulse. The technique includes determining a transmission delay between the first and second network elements based on the first and second time differences.

Abstract: Systems, methods, and computer-readable media for propagating a timing signal over a Dense Wave Division Multiplexer fiber optic network by polarity modulation of the Optical Service Channel are provided. The systems, methods, and computer-readable media may make the timing signal available for use by devices that require a reference timing source.

Abstract: A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10 G/40 G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Abstract: A method for determining an overlap and add length estimate comprises determining a plurality of correlation values of a plurality of ordered frequency domain samples obtained from a data frame; comparing the correlation values of a first subset of the samples to a first predetermined threshold to determine a first edge sample; comparing the correlation values of a second subset of the samples to a second predetermined threshold to determine a second edge sample; using the first and second edge samples to determine an overlap and add length estimate; and providing the overlap and add length estimate to an overlap and add circuit.

Abstract: Certain aspects of a method and system for speed negotiation for twisted pair links in fiber channel systems are disclosed. Aspects of a method may include communicating data between fiber channel host devices communicatively coupled via a twisted pair link based on a common speed negotiated between the fiber channel host devices. At least one available speed may be determined for the communication of data between the fiber channel host devices over the twisted pair link. The determined available speeds for each of the fiber channel host devices may be exchanged via at least one fast link pulse signal. The common speed negotiated may be a highest available speed for the communication of data between the fiber channel host devices.

Abstract: A system handles timing information within a packet-switched network. The system classifies packets for processing depending on the packet type. After classification, a new timestamp value may be produced depending on the packet classification. The new timestamp value may use a timestamp value from the received packet, a value from a local clock, and an offset value. The timestamp value may be written into the packet, depending on the packet classification, and checksum-type fields may additionally be updated in the packet. In some embodiments, multiple physical layer circuits are integrated with a local clock circuit.

Abstract: Systems, methods and computer program codes are provided to facilitate error detection and timing synchronization of scalable data transmissions. To this end, checksum error detection is applied to the core layer and enhancement layers of the scalable payload data in such a way that dropping one or several enhancement layers from the payload data does not change the value of the checksum. Only one checksum is transmitted, e.g., in the payload or in the header of the lower-layer protocol. The transmitter modifies the encoded bit stream in such a manner that the entity in the network deploying the scalable payload and removing layers from the packet does not need to recalculate the checksum placed in the payload or packet header, even when the payload size is changed.

Abstract: According to one embodiment, a frequency offset compensation apparatus includes a first estimation unit, a second estimation unit, a setting unit, a synthesis unit and a compensation unit. The first estimation unit estimates a first rotation. The second estimation unit estimates a second rotation. The setting unit sets a weighting factor for the second rotation to a first value if a received power is less than a threshold value, and sets the weighting factor for the rotation to a second value being smaller than the first value if the received power is not less than the threshold value. The synthesis unit calculates a compensation value. The compensation unit compensates for a frequency offset.

Abstract: Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.

Abstract: A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions. The method further includes transforming the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols. The method further includes interpolating the third plurality of symbols, generating a short training field comprising at least one real portion of the third plurality of symbols, generating a long training field comprising at least one real portion of the third plurality of symbols, and transmitting the short training field and long training field in a WPAN.

Abstract: According to a first aspect, the invention proposes a method for processing a transport stream (TS) received as an input transport stream in a processing device (SDR), the transport stream comprising a plurality of elementary streams (ES), each elementary stream (ES) being a set of transport stream packets having the same Packet IDentifier (PID), at least one of these elementary streams being time-sliced so as to be sent in bursts, timing information indicating within a burst the time to the beginning of the next burst, characterized in that it comprises the steps of: applying a filtering operation to the input transport stream so as to filter out from the input transport stream part or all of one or more time-sliced elementary streams; modifying the bursts scheduling of the input transport stream so as to generate a DVB-H compliant output transport stream from the filtered input transport stream.

Abstract: A high-speed security device for network connected industrial controls provides hybrid processing in tandem hardware and software security components. The software security component establishes state-less data identifying each packet that requires high-speed processing and loads a data table in the hardware component. The hardware component may then allow packets matching data of the data table to bypass the software component while passing other non-matching packets to the software component for more sophisticated state analysis.

Abstract: Time synchronization between a control center and transmitters in a single frequency network is provided by generating and receiving a first reference time signal with a high time and frequency accuracy in a short and long time horizon and a second reference time signal supplied to the control center with a low time and frequency accuracy in the short time horizon and a high time and frequency accuracy in the long time horizon. A transport data stream is generated and supplied to the transmitters with a time-variable data rate through the control center corresponding to a frequency of the second reference time signal. Time displacement of the transport data stream received from the control center is performed by a respective transmitter until the data packets of the transport data stream each containing a transmission time are transmitted at a correct transmission time.

Abstract: The invention relates to a method or an arrangement for the clock synchronization of a plurality of distributed modules of an information or communication system, said modules being coupled via a packet-switched network. At least two of said modules are controlled by a local clock generator of the modules using an adjustable frequency, and a clock signal is transmitted via the network in the form of clock signal packets in a synchronous minter with respect to the local clock of the modules.

Abstract: A base station transmits control message(s) to a wireless device configuring secondary cell(s). Each of the secondary cells is assigned to a cell group in a plurality of cell groups comprising a primary cell group and at least one secondary cell group. The control message(s) comprise dedicated parameters. If dedicated parameters comprise a cell group index for the secondary cell, the wireless device assigns the secondary cell to one of the at least one secondary cell group identified by the cell group index. Otherwise, the wireless device assigns the secondary cell to the primary cell group.

Abstract: The present invention relates to a method of generating a downlink frame. The method of generating the downlink frame includes generating a first sequence and a second sequence for identifying cell groups; generating a first scrambling sequence and a second scrambling sequence that are one-to-two mapped to the sequence number of the primary synchronization signal; scrambling the first sequence with the first scrambling sequence and scrambling the second sequence with the second scrambling sequence; and generating a secondary synchronization signal including the scrambled first sequence and second sequence and mapping the secondary synchronization signal to a frequency domain.

Abstract: A network entity and computer program for detecting occurrence of transmission resynchronizations in a network carrying packets subject to variable delays, and adaptively varying the play out time of data packets. The method may include that the packets are received at a network entity and forwarded by delaying them by a jitter protection time, and determining for a predetermined time period a set of arrival time jitter values. A peak to peak value may be determined indicating the largest difference among the values included in the determined set of arrival time jitter values and detecting an out of range condition. The peak to peak value may be compared with the jitter protection time when the out of range condition is detected and detecting that a resynchronization occurred on the basis of the comparing.

Abstract: The disclosure aims to implement an automatic frequency offset compensation of the frequency between emitter and receiver equipments, in radio frequency modules, with a frequency offset that can be larger than that the receiver can allow, without time loss and extra consumption. To solve this problem, the disclosure provides an automatic frequency offset compensation device comprising a reception front end, at least a filter, an I/Q demodulator for obtaining the I (In Phase) and Q (Quadrature) parameter, an automatic frequency control AFC unit for comparison of a received frequency with the real frequency of the equipment, and a microcontroller and a frequency synthesizer. In this device, the frequency offset is calculated by the AFC unit from the information given by the I/Q demodulator.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.