Abstract: Methods and apparatus are disclosed for handling transient anomalies in a communications or computer device or system, such an inverse multiplexing for ATM (“IMA”) device. Such transient anomalies may include out of IMA frame (“OIF”) anomalies. In one implementation, cells comprising a stream of packets are received over multiple links along with indications of OIF conditions for these links. During a period of an inactive OIF condition on a link, cells are received over the link and placed in a buffer at a next location. After an OIF condition is detected, cells are ignored and a write process waits until the OIF condition is no longer active. At which point, a buffer position is determined to place the next valid cell. Typically, this cell should be placed in the same buffer position as it would have been if there had never been an active OIF condition.

Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Abstract: A method is provided for manually synchronizing the playback of a digital audio broadcast on a plurality of network output devices. The method is applicable for use with methods such as those that use a time code, insert a control track pulse, or use an audio waveform sample for synchronization. The manual adjustment method relies on a graphical user interface for adjustment and audible pulses from the devices which are to be synchronized. The digital audio broadcast from multiple receivers does not present to a listener any audible delay or echo effect.

Abstract: In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also includes an interface between the first PRBS generator and a tester. The apparatus further includes an interface between the first PRBS generator and a device under test. The apparatus may further include a second PRBS dedicated to a second tributary. The apparatus may also include a control logic block to control the first PRBS generator and the second PRBS generator, and coupled to the first PRBS generator and the second PRBS generator.

Abstract: In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycle 1T), a delay of 1T is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.

Abstract: A multiplexed data producing apparatus which multiplexes N (integer) pieces of object data in which one of video data, audio data, and digital data is multiplexed to produce one piece of multiplexed data comprises a temporal storage means for temporarily storing the N pieces of object data; a control means for controlling synchronization of time information of each object data for each temporarily stored object data; and a multiplexing means for multiplexing the processed object data to produce multiplexed data.

Abstract: A method and apparatus is described for the automatic delay compensation in space diversity radio transmissions. The method includes the steps of: a) receiving a first analog signal and a second analog signal, a possible delay being between the first and second signals; b) sampling the first and the second analog signals to obtain a first digital signal and a second digital signal, respectively; c) sending the digital signals to respective equalizers, and the steps of d) digitally delaying one of the first digital signal and the second digital signal by a period equal to an integral multiple of the sampling period, and e) recoverying, at the equalization phase, the residual difference between the imposed delay and the actual one.

Abstract: A duplex aware adaptive playout method includes detecting a packet communication mode as either a full-duplex mode or a half-duplex mode, calculating a playout delay for a current packet based on the detected packet communication mode, and delaying playout of the current packet by the calculated playout delay. When the packet communication mode is detected to be the half-duplex mode, the calculated playout delay for the current packet is set longer than when the packet communication mode is detected to be the full-duplex mode. A duplex aware adaptive communications device includes a playout buffer, a playout controller, a network delay estimator, and an active detector that detects a packet communication mode. The playout controller determines playout delays of packets in the playout buffer from estimated network delays and a detected packet communication mode being a full-duplex mode or a half-duplex mode.

Abstract: In some embodiments, a method includes detecting a tone in each data frame of a sequence of telephony signal data frames. A first data frame of the sequence of telephony signal data frames may be transmitted immediately after detecting the tone therein. Transmission of a last one or last ones of the sequence of telephony signal data frames may be deferred. It may then be determined whether the tone is present in a next data frame that immediately follows the sequence of telephony signal data frames. If it is determined that the tone is not present in the next data frame, the last one or ones of the sequence of data frames and the next data frame may be transmitted. If it is determined that the tone is present in the next data frame, a respective replacement data frame may be transmitted in place of each one of the last one or last ones of the sequence of data frames and in place of the next data frame.

Abstract: A codec aware adaptive playout method estimates playout delays for a current packet based on a loss mean opinion score (LMOS), a delay mean opinion score (DMOS), and a mean mean opinion score (MMOS) of packets with reference to the codec used in voice over Internet protocol (VoIP), streaming audio, and streaming video transmissions. The method selects an estimated playout delay having an optimum MMOS, or playout quality, from the plurality of estimated playout delays, and delays the playout of the current packet by the selected estimated playout delay. A codec aware adaptive playout device includes a playout controller for controlling playout of packets in a playout buffer. The playout controller references network delay estimates provided by a network delay estimator, and codec information such as the LMOS, DMOS, and MMOS provided by a codec detector to determine playout delays for the packets of the playout buffer.

Abstract: A communication apparatus and method that includes generating a series of successive spread-spectrum signals formed through the concatenation of a direct sequence spread spectrum code with a Doppler Tolerant Polyphase Code (DTPC) is herein disclosed. By transmitting concatenated codes, it is possible to demodulate received sequences that are very long compared to the inverse of the Doppler frequency and/or the local oscillator drift. The method and apparatus may be applied to implement a wireless telecommunication system that efficiently transfers small quantities of data, such as status/telemetry, identification information and/or establishes device location at a low data rate over long distance in challenging radio environments and with low power consumption.

Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

Abstract: A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Abstract: The invention provides a method and apparatus for providing hitless protection switching in a transmission systems which support a standardized implementation of virtual concatenation. A switching apparatus is arranged to receive data signals on at least two transmission paths and to output data from a selected one of said transmission paths. The apparatus is arranged to align the respective received data signals so that a selector mechanism can select between corresponding elements of the received data signals. This arrangement allows hitless switching to be performed since there is no loss or repetition of signal elements when switching occurs. In a preferred embodiment, data in respect of each frame of each data signal is stored and the selector mechanism selects between paths on a frame-by-frame basis by comparing quality information carried by the data signals. This arrangement offers a very low end to end Bit Error Rate (BER) performance.

Abstract: Method and system for synchronization of base stations in a mobile communications network, in particular for the purpose of a seamless handover, time information is transmitted, possibly on request, to the base stations from a time information server via a local area network. Since base stations which are involved in a seamless handover are generally adjacent, and the respective propagation times and/or propagation time fluctuations of time information differ only slightly in the local area network between the time information server and the base station when the base stations are adjacent, highly accurate synchronization may be achieved, especially for a seamless handover.

Abstract: A multi-module switching system comprising at least two switching modules adapted for receiving data packets from at least one input adapter and transmitting the data packets to at least one output adapter, each of the switching modules including a shared buffer for buffering a portion of a data packet received from an input adapter and transmitting the portion to an output adapter. One of the switching modules is a master module receiving a portion of a data packet containing a packet header and sending control information contained therein serially to each other switching module as a slave module.

Abstract: A system for compensating for timing violations of time restricted data being transmitted over a bursty communication channel. The system includes a retriever, coupled to a buffer, for retrieving the time restricted data from the buffer, at a retrieval rate, a buffer level monitor, coupled to the buffer, for monitoring the level of time restricted data in the buffer at a monitoring rate and a controller coupled to the buffer level monitor and to the retriever, for setting the retrieval rate and the monitoring rate.

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Abstract: A system and method to measure the clock skew between transmitting and receiving devices operating with independent clock sources over a packet network is described. To provide adaptive playout in an IP telephony device without a sequencing scheme in the packets, the clock skew is measured and recorded. Using a PCM resampler that is implemented with an interpolation filter bank of FIR subfilters, the change in depth of the playout buffer during transmission is analyzed, and this change infers the clock rate associated with the transmission.

Abstract: A method, apparatus, and computer-readable media for aligning n data signals received over a parallel bus, each of the n data signals comprising a training pattern, wherein n is at least two, comprises delaying each of the n data signals in accordance with a corresponding analog delay signal, thereby providing n corresponding delayed data signals; providing each of the corresponding analog delay signals based on the training pattern in the respective delayed data signal; delaying each of the delayed data signals by m bit times in accordance with a corresponding digital delay signal, thereby providing n corresponding aligned data signals, wherein m is greater than, or equal to, zero; and providing each of the corresponding digital delay signals based on the training pattern in the corresponding delayed data signal.

Abstract: A frame-interleaving system may transmit the same data in two data streams. Frames may become fragmented switching between two data streams. The reliability of a frame-interleaving system may be improved by aligning data streams that carry the same data so that the corresponding frames in the data streams are synchronized before the data streams are switched.

Abstract: A system and method for reducing jitter in a packet transport system. In one embodiment, the system includes (1) a cell status subsystem that determines whether a cell is a data cell or a control cell; and (2) a cell reader, coupled to the cell status subsystem, that reads the cell if the cell is a data cell and skips the cell if the cell is a control cell.

Abstract: A data processing system comprises a cluster of devices (16) interconnected for the communication of data in streams, particularly digital audio and/or video data. One of the devices (10) is a source device for at least two data streams to be sent to one or more other devices (12, 14) as destination devices of the cluster. To enable synchronization of the stream presentations by the destination devices, some or all of the devices (10, 12, 14) carry respective tables (11, 13, 15) identifying, for that device, an identifier for each type of data stream that the device can process together with the processing delay for that stream. The or each such table is accessible via the cluster connection (18) to whichever of the devices, at source, destination or in between for the signal, is handling application of the necessary offsets.

Abstract: A bearer integration method for integrating a plurality of bearer services into a wireless channel by performing time-division multiplexing/demultiplexing is provided, in which bearer service data is input in synchronization with reference frame timing of a period T in a sending side, the bearer service data is delayed by one frame period by allocating delays A (0?A?T) and A? (=T?A) between the sending side and a receiving side, the bearer service data is output in the receiving side, and the bearer service data is integrated into a wireless channel with another bearer service data in which delays B (A?B?T) and B? (=T?B) are allocated between the sending side and the receiving side.

Abstract: A system for transmitting digital information over a synchronous network includes at least one source node and at least one sink node both coupled with the synchronous network. The source node provides source information sampled at a source sample rate (Fsi) to the synchronous network in the form of digital information. The synchronous network operates on a network master clock rate (Fn) with a frequency that may be higher, lower or equal to the source sample rate (Fsi). The digital information is transmitted over the network to the sink node. The sink node processes the digital information to generate synthesized source information.

Abstract: In real time communication, long interruption of a media data signal caused by underflow or overflow of a buffer is reduced. A monitoring unit 35a monitors a state of the buffer 34 periodically. When the number of encoded data in the buffer 34 shows tendency of increasing from a standard data storage number, successively a predetermined number of times, then, it is judged that the buffer tends to overflow. And, the decoding unit 35 is made to skip at least one encoded data to be read and processed this time from the buffer 34. Further, when the number of encoded data in the buffer 34 shows tendency of decreasing from the mentioned standard data storage number, successively the predetermined number of times, then, it is judged that the buffer tends to underflow. And, the processing unit 35 is made to suspend operation during at least one period of the above-mentioned reproduction period.

Abstract: To evaluate a communications network, a plurality of network evaluation signals, or probative test packets, are selectively sent and received through the network. Responsive to these evaluation signals, network evaluation parameters are determined and stored. Queuing theory analysis, responsive to these parameters, determines the response time and throughput characteristics, including discrete capacity, utilization and performance, of the network. Calculation of the value of the network's discrete utilization involves the measurement of the network's average delay waiting for service, measurement of the network's standard deviation of delay waiting for service, calculation of discrete utilization from the ratio of these observed values, and then refinement of that calculation by proportionate factoring in instances of dropped samples as cases of one hundred percent utilization to arrive at a final figure for percent of network discrete utilization.

Abstract: Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

Abstract: Methods for slice-based encoding of program guides and user interfaces. The program guides include multiple video streams for picture-in-picture and other applications. A method for encoding the program guide includes encoding a first set of slices for each of a plurality of graphics pages; and encoding a second set of slices for each of a plurality of video streams. The user interfaces are multi-functional and may be used for electronic commerce and other applications. A method of generating the user interface includes encoding a set of slices for each of a plurality of objects, each object being characterized by an identity, at least one attribute, and at least one operation. In one embodiment of this method, the plurality of objects include an electronic commerce object, where the electronic commerce object is attributed with a first hyper text markup language (HTML) page.

Abstract: A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device that initially receives the N bit digital data signal, and a sink device that receives the N bit digital data signal from the source device. The N bit digital data signal has a skew when received by the sink device. A skew detection circuit in the sink device detects the skew in the N bit digital data signal and generates a skew detection signal. A line supplies the skew detection signal to the source device. A compensation circuit in the source device receives the skew detection signal and compensates for the skew in the N bit digital data signal.

Abstract: A method of and system for estimating a parameter of a local maxima or minima of a function. An interpolated local maxima or minima is determined. An interpolation offset is then derived, comprising a deviation between locations of the interpolated and sampled local maxima or minima of the function. An estimate of the parameter is derived from the interpolation offset.

Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low frequency is inputted and improves operation frequency by using different programmable dividers to operate at different division rates when clock signals of high frequency and low frequency are inputted. Additionally, the optimum clock synchronization device may be embodied by using a replica delay unit corresponding with the package type.

Abstract: A delay variation buffer controller allowing proper cell delay variation control reflecting an actual network operation status is disclosed. A detector detects an empty status of the data buffer when data is read out from the data buffer at intervals of a controllable time period. A counter counts the number of contiguous times the empty status was detected. A proper time period is calculated depending on a value of the counter at a time when the empty status is not detected and the value of the counter is not zero. A timing corrector corrects the controllable time period to match the proper time delay and setting the controllable time delay to a predetermined value when the empty status is not detected and the value of the counter is zero.

Abstract: A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character.

Abstract: A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process, changes in operating voltage, and fluctuations in temperature. A clock signal is inverted, thus generating an inverted clock signal which is then delayed multiple times, resulting in several delayed versions of the inverted clock signal, with each version being delayed a different length of time. The logical state of each delayed version of the inverted clock signal is then stored. That stored logical state provides an indication as to the magnitude of the delay of the integrated circuit which may then be used to tune critical signals of the integrated circuit to avoid timing problems resulting from variations in IC propagation delay.

Abstract: A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (104). The synchronization circuit (110) gates the output of the multiplexor (108) such that a pulse appears at the synchronization circuit's (110) output port (114) only when the circuit is gated by a signal at input TRIG (112). The synchronization circuit (110) creates a time aperture for the multiplexor output.

Abstract: A system for performing Bit Interleaved Parity-8 (BIP-8) computation on large concatenated payloads, in a processing node of an optical communications networks. The BIP-8 computation system comprises storage means associated with each processing strip for allowing the comparison between calculated and transmitted frame error check values to be delayed.

Abstract: Transmitting data packets received from a non-constant delay medium includes storing the data packets in a buffer, determining a play-out schedule for the data packets based on timing information in the data packets, and transmitting the data packets from the buffer in accordance with the play-out schedule. Two of the data packets may contain time-stamps and the play-out schedule may be determined based on a difference between the time-stamps.

Abstract: An interface is provided for interfacing at least one information stream with at least one modulator in the headend or hub of a broadband communications system. The interface allows for separating the media access control function from the modulator. By updating timing references, variable delays are handled appropriately.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: Encapsulating cells includes receiving cells at a queue associated with decision points. Each decision point corresponds to a number of cells and is associated with a threshold criterion. The following operations are repeated until a threshold criterion is satisfied. A number of cells corresponding to a decision point are accumulated at the queue. Jitter associated with the cells at the queue is predicted, and it is determined whether the predicted jitter satisfies the threshold criterion associated with the decision point. If the predicted jitter satisfies the threshold criterion, the cells are sent to a buffer coupled to the queue. Otherwise, the cells continue to be accumulated at the queue. The cells in the buffer are encapsulated.

Abstract: A device, system and method for aligning data received on a plurality of data lanes in a data link are disclosed. One or more alignment vectors are generated for each of a plurality of data lanes where each alignment vector represents a location of an alignment character in an associated one of the data lanes. For each data lane, a plurality of alignment vectors may be associated with one or more alignment windows associated with the data lane. If the alignment vectors of the data lanes are associated with a common alignment window, an alignment position may be selected for each data lane.

Abstract: An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two edges of two-phase clock signals CLKb and CLKc having a relatively narrower interval of 57 ps synchronizes with a phase of a transition point of the input data i. By changing clock signals to be phase-locked in three delay locked loops (DLLs), a phase interval of 57 ps is formed.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A reception synchronization apparatus capable of achieving precise synchronization of an OFDM signal including a frame guard added to the OFDM signal includes a multiplier for calculating the correlation between a received OFDM signal and an OFDM signal delayed by a delay circuit; a moving integration circuit for adding a signal from the multiplier over a guard period; n frame guard removing circuits, which respectively receive a signal from the moving integration circuit, remove the frame guard period from the received signal, and output a resultant signal; n interval integrators for cumulatively adding signals outputted from the frame guard removing circuits; and a detection circuit for detecting a maximum peak from the results from the n interval integrators and generating a detection signal indicating a synchronization timing position corresponding to the detected maximum peak position.

Abstract: A method, apparatus (22), and program are provided for determining an amount of bandwidth available in at least a portion of at least one communication path (5, 3, 6, 7, 10-1, 9, 12, 13, 14, 24a, 24b) coupling a plurality of nodes (1, 15, 22) together. The communication path (5, 3, 6, 7, 10-1, 9, 12, 13, 14, 24a, 24b) is exercised using information signals, to determine the amount of time it takes for at least one of those information signals to traverse the communication path (5, 3, 6, 7, 10-1, 9, 12, 13, 14, 24a, 24b) in at least one direction, and the amount of bandwidth available in at least a portion of the communication path (5, 3, 6, 7, 10-1, 9, 12, 13, 14, 24a, 24b) is determined, based on the amount of time determined in the exercising step.

Abstract: A plurality of delay circuits successively delay a received data. The received data and delayed data signals are sampled in response to both leading and trailing edges of a clock having a frequency substantially identical with that of a data transmission rate of the received data. When a sampling value having the same value V (V=1 or 0) appears continuously N times in the sampling operation of the received data 101 (where N is an even number), it is judged that a data of value V is continuously received (N/2) times.

Abstract: A local communication layer is placed in communication with a remote communication layer via a communication link established between a local modem and a remote modem. The communication layers may, for instance, be PPP layers. The communication is then interrupted, for example, by being temporarily paused or being placed on hold. In one scenario, the communication is placed on hold by the remote modem, as a result of a call-waiting alert received by the remote modem. After the communication has been placed on hold, the local modem monitors PPP frames from the local PPP layer and spoofs the local PPP layer by way of responses to the local PPP layer requests as if such responses were made by the remote PPP layer.