Abstract: A system and method for generating and remotely installing a private secure and auditable network is provided. Node identification, link, and application information is input into a template. A generator generates components using the information in the template and the components are remotely installed using an installation server. The components include agent modules which are each installed at predetermined target site and establish communication with the installation server to facilitate the download of other components, including application software and configuration files. Each node can only be installed once and is specific to a predetermined target site. For each link, a unique pair of keys is generated in a form which is not human readable, each key corresponds to a different direction of communication over the link. Data transmitted between nodes is encrypted using public-private key pairs.

Abstract: Time-slot interchange switches include measurement circuits that automatically measure frame alignment associated with a plurality of multi-frame data streams received by the switch. Internal programming circuits are also provided to convert the frame alignment measurements into frame offsets. Unacceptable frame offsets are also automatically identified using error control circuitry. These measurement and programming circuits streamline frame offset measurement techniques and enable on-chip measurement and conversion of frame delays to frame offsets and programming of frame offset registers (FORs).

Abstract: The transmission distance for DDS subscriber lines over a repeaterless four-wire link is extended to customer premises beyond the standard four-wire loop range of approximately 18 kft (56 kbps, 56 kbps with secondary channel capability, and 64 kbps) by employing commercially available ISDN transceiver chip hardware to multiplex a DDS data channel into quarter-rate (2B1Q) ISDN channels. At least one of a signalling channel and an out-of-band maintenance channel is used to convey differential delay compensation information, without modifying the framing structure of the transported channels, or requiring additional bandwidth for a separate framing channel.

Abstract: The present invention presents an anti-meta trap (AMT) circuit for maintaining the data integrity of transmitted bit data in various applications. The anti-meta trap (AMT) circuit implement bit data integrity checks to prevent bit data from being misinterpreted at the bit level, that is, from being sampled at a data transition state. The invention also presents an anti-meta circuit combined with an auto-synchronization circuit to synchronize the phase of complete, bit-data verified cells, e.g., ATM data cells. The combined AMT-ASC is therefore able to verify the integrity of the data at the bit level, and synchronizing fixed-length data cells.

Abstract: Even the case where the transmission rate for packets is varied in forming a sequence of packets from the packets, time information previously added to each packet is corrected based on absolute time information added to each of the packets forming the sequence of packets, thereby making it possible to realize a data processing apparatus and method capable of significantly improving the transmission efficiency for packetized data.

Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Abstract: All mutual interference occurring between TCM-ISDN and ADSL that communicate by utilizing a line having the same properties and using the same reference signal, and all mutual interference occurring between ADSLs are rejected, by delaying the TTR in the own ATU-C by S1 and approximately adjusting the TTR transmitted to the ATU-R which is a device to be communicated by S2.

Abstract: An implementation of a synchronous state machine, responsive to a time division multiplexed external input signal having plural time slots in a repetitive structure, has all of its flip-flop outputs hooked up to a state memory so that the state produced by each time slot is stored until that time slot is again repeated at the external input, at which point the stored state is recalled from memory for being input along with the incoming time slot data; in this way the hardware is shared between time slots. A substitution element is disclosed having a flip-flop with its output routed to memory and for providing a memory output as its output. A design methodology is taught whereby a state memory and a substitution element is substituted for each flip-flop in a synchronous state machine implemented for one time slot of a repeating pattern of time slots.

Abstract: There is disclosed a method and apparatus for controlling the size of a jitter buffer in an audio receiver. The method an apparatus are such that network jitter can be distinguished from burst periods, where a large number of data packets (or packets) are transmitted rapidly. This method comprises the steps of monitoring the network for at least one burst period and then determining a likelihood for at least one subsequent burst period from this at least one burst period. The jitter buffer size is then adjusted based on the likelihood of this subsequent burst period. Apparatus for performing these method steps is also disclosed.

Abstract: A variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.

Abstract: For executing setting suspend and resume securely, a suspend packet transmitter includes a device status checking unit for checking whether or not a device connected with a communication network fulfills suspend and resume function; a judging unit for judging with reference to data in said device status checking unit whether or not a device without suspend and resume function exists in a domain set in suspend state by means of inputted suspend device number and port number; and a packet transmitting unit for transmitting a suspend packet with said inputted suspend device number and port number when all devices are judged as devices with suspend and resume function in said judging unit.

Abstract: An apparatus and method for expanding a service area of a code division multiple access (CDMA) system restricted in terms of timing. The service area of a CDMA mobile communication system, which is defined by a radius longer than a radius of a communication supported area, namely, a cell, restricted in terms of timing due to the hardware of a base station modem ASIC equipped in the system, is radially divided into a plurality of radial zones by a constant distance not longer than a maximum possible cell radius allowed by the base station modem ASIC. In accordance with the present invention, signal processing units are used which are configured in such a fashion that one of them covers the entire zone of the service area in regard to forward links from an associated base station to mobile stations in different zones of the service area while covering only the zone nearest to the base station in regard to reverse links from the mobile stations to the base station.

Abstract: A method, a device and a system for delay equalizing of fragment data streams transmitted via N individual paths and forming a virtual data stream, wherein the virtual data stream and each of said fragment data streams consisting of data frames; the method including gradual minimization of differential delay of the fragment data streams at one or more intermediate points between a source point and a destination point of the virtual data stream. The gradual minimization of the differential delay can be provided by devices (30, 32) respectively fitted at the intermediate points; each of the devices comprises a control unit (36) and N memory buffer blocks (34), each associated with a respective individual path.

Abstract: A compensation module or for a network device of a telecommunications network delays a first clock signal by a predetermined first delay time to form a delayed first clock signal and delays a second clock signal by a predetermined second delay time to form a delayed second clock signal. The compensation module then adapts the second delay time so that the delayed second clock signal is adapted to the phase of the delayed first clock signal.

Abstract: In a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit operates the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal.

Abstract: A multiplexed data producing apparatus which multiplexes N (integer) pieces of object data in which one of video data, audio data, and digital data is multiplexed to produce one piece of multiplexed data comprises a temporal storage means for temporarily storing the N pieces of object data; a control means for controlling synchronization of time information of each object data for each temporarily stored object data; and a multiplexing means for multiplexing the processed object data to produce multiplexed data.

Abstract: The invention relates to a protective device for a clean robot that includes a base 7 in which actuators 4 and 5 for driving a robot arm 3 are accommodated; a translational guide 8 for causing the base 7 to travel in a rectilinear direction; and a robot controller 10 that drives and controls the drive motor 4A and 5A of the robot arm 3 and an actuator 9 of the translational guide 8; wherein the protective device further includes acceleration sensors 11, which are disposed in the base 7 and are provided in respective axes so that they can detect an impact, when the clean robot 1 interferes with a surrounding substance, as vibration acceleration in the three-dimensional directions; an interference detecting device 13 that outputs a pulse when the detection signals of the acceleration sensors 11 of the respective axes exceed the threshold values that will become standards; and the first AND circuit that converts signals outputted from the interference detection means of the respective axes to interference signal

Abstract: A device for data stream analyzing that are able to recognize different data streams and then start processors or functionalities to store or check data in a data stream, comprising processor means including a program memory, making it possible to parse a data stream in a way that is controlled by an interchangeable program. There will be no need for changing the hardware. This could save time and money for companies responsible for providing, maintaining and updating network switches. The device also includes a multiplexable data stream delayline for receiving said data streams, and multiplexing means for connecting different parts of the data stream to said processor.

Abstract: A multiplexer is provided for making data into a plurality of cells and then for transmitting the plurality of cells through a cell transmission path. The multiplexer includes a first delay-fluctuation adding unit adding a first maximum value of delay fluctuation occurring when the multiplexer transmits the cell, to a predetermined area of the cell; a second delay-fluctuation adding unit adding a second maximum value of delay fluctuation occurring when the multiplexer reproduces the data from the cell, to the predetermined area; a storage unit storing the data; and a data-read control unit controlling reading the data stored in the storage unit by following a maximum value of delay fluctuation stored in the predetermined area. Accordingly, the multiplexer can control absorption of the delay fluctuation individually for each cell transmission path.

Abstract: A method and an apparatus provide for controlled access to a shared communication medium. Time slots on a forward channel include information regarding status useful for remote units to determine whether a reverse channel is available for seizure. Additionally, information along the forward channel provides guidance to the remote units to control attempts to seize the reverse channel. In one embodiment a remote unit divides a data package into a plurality of portions and attempts to seize the reverse channel using a single portion of the data package which corresponds to one time slot on the reverse channel. It then waits until it receives notification along the forward channel that the first data portion was successfully received before it attempts to send any of the remainder of its data in consecutive time slots on the reverse channel.

Abstract: In a method for reducing latency in packet telephony caused by anti-jitter buffering, audio data elements are received and placed in a telephony input buffer used for anti-jitter buffering. Rather than wait until the buffer is full, the audio data elements are clocked, or played, out of the buffer at a rate slower than the normal play rate. In this way, latency due to the initial buffer fill period is reduced or eliminated. Audio data elements continue to be played out at a slower than normal rate until the buffer fill level reaches a threshold. At that time, the play rate for sending data elements out of the telephony input buffer is adjusted to the normal play rate. In an alternative embodiment of the present invention, the fill level of the telephony input buffer is controlled within a desired range by speeding up or slowing down the rate at which audio data elements are played out of the telephony input buffer.

Abstract: A circuit for extracting a data clock signal from an input data stream, comprising a programmable delay element for receiving an arbitrary clock signal, delaying the arbitrary clock signal by a variable programmable amount and in response generating an extracted data clock signal, and a clock phase detector for comparing logic level transitions of the input data stream with transitions of the extracted data clock signal and in response generating a delay adjust signal for defining the variable programmable amount of delay such that the transitions of the input data stream are substantially aligned with the transitions of the arbitrary clock signal.

Abstract: In a packet voice system, a dynamic build-out delay approach in a receiver during the duration of a call. In particular, the build-out delay is applied at least twice during the duration of the call. In one embodiment, a packet voice system includes an ATM Adaptation Layer Type 2 (AAL-2) and Service Specific Convergence Sublayer (SSCS) System. The receiver portion of the SSCS System recovers AAL-2 packets and plays back the compressed audio to a voice decoding element. In providing playback, the receiver applies the build-out delay at the start of each talk-spurt. The voice decoding element provides an uncompressed audio stream. In another embodiment, the receiver portion of the SSCS System applies the build-out delay at the start of the each talk-spurt as a function of the length of the previous silence interval.

Abstract: A phase detecting/collating circuit collates a phase of a reception serial data input from outside through an external interface circuit, a phase of the reception data shift clock output from the clock frequency divider/corrector circuit, and a phase of a phase collating clock obtained by delaying the reception data shift clock by ¼ periodic cycle of the reception data shift clock by means of the delay circuit. By the phase collation in the phase detecting/collating circuit, if a difference in phase capable of generating a reception error in the data transmission circuit is detected, the clock shortening timing signal or the clock elongating timing signal is output. A reception clock frequency divider/corrector circuit corrects such as to shorten or elongate said reception data shift clock when a clock shortening timing signal or a clock elongating timing signal is input, respectively. With this effect, the reception operation in the data transmission circuit is executed always normally.

Abstract: The invention describes a method for transmitting and forwarding packets from source nodes with variable bit rates (VBR) and how it can be integrated with other types of traffic, over a packet switching network. The sources can generate traffic with predefined average and peak rates. Packets enter the network in predefined time interval and are forwarded over each link inside the network within a periodic time interval if there is sufficient capacity. When arriving packets exceed predefined average capacity, packets are rescheduled for alternative time intervals or discarded. This invention facilitates congestion-free forwarding from one input port to multiple output ports, and consequently, from one source to multiplicity of destinations for packets within the predefined average rate. Such packets that are destined to multiple destinations reach all of their destinations in redefined time intervals and with delay jitter that is no larger than one time interval.

Abstract: A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.

Abstract: An apparatus and method for receiving a bitstream containing timing information and respective program information, the program information is processed and associated with locally generated timing information to form an output bitstream, the locally generated timing information is synchronized to the received timing information so that the timing relationships of the received program information are preserved even after the program information is processed.

Abstract: The invention describes a method for interfacing a packet-switched network with real-time streams from various sources, such as circuit-switched telephony network sources. The network interfaces and gateways maintain a common time reference (CmR), which is obtained either from an external source (such as GPS—Global Positioning System) or is generated and distributed intemally. A data packet that is packetized at the gateway is scheduled to be forwarded to the network in a predfined time that is responsive to the common time reference. The invention relates, in particular, to timely forwarding and delivery of data packet between voice over IP (VoIP) gateways. Consequently, the invention provides a routing service between any two VoIP gateways where the end-to-end performance parameters, such as loss, delay and jitter, have deterministic guarantees. Furthermore, the invention enables gateway functions with minimum delay.

Abstract: A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.

Abstract: A method and apparatus for analyzing and monitoring packet streams in “real time”. The packet analyzer comprises an input buffer, a real-time analysis unit, a non-real-time analysis unit, a graphics unit, a monitor and a flushing circuit. A packet stream is received into the input buffer where the data is either read by the real-time analysis unit or flushed by the flushing circuit. Messages are passed between the real-time analysis unit and the non-real-time analysis unit to report on detected errors or to update packet stream information. In turn, real time packet stream information are displayed and updated on a display via the graphic unit. A method of detecting framing errors in a packet stream is incorporated by setting a 9th bit in the input buffer for each byte of data in a packet.

Abstract: An information processing apparatus capable of receiving and processing a variety of types of input is shown with features that make it easy to add properly synchronized information as desired. A CCD photoelectrically converts into image signals the light of objects collected by a photographic lens. The image signals of the photographic images are digitized by an analog/digital (A/D) conversion circuit, and are compressed by a digital signal processor (DSP). A central processing unit (CPU) records on a memory card the photographic images along with their input date and time as header information. When sound information is received through a microphone during reproduction of the photographic images, the CPU 34 records on the memory card the sound information along with the input date and time header information of the photographic images.

Abstract: A system for synchronizing a carrier frequency of an orthogonal frequency division multiplexing (OFDM) transmission apparatus, even when a carrier frequency offset is above a frequency bandwidth of one subchannel. The synchronization of the carrier frequency in the OFDM transmission apparatus is accomplished by alternating between a coarse mode for synchronizing an integer part of the carrier frequency offset and a fine mode for synchronizing a prime part of the carrier frequency offset.

Abstract: In a code division multiplexed system, a subscriber unit (260, FIG. 1), which includes a pseudonoise code generator (70), is synchronized with the pseudonoise code generator (220) of a communications node (200). Synchronization between the pseudonoise code generators (70, 220) is achieved through measuring the time delay of a signal transmitted from the communications node (200) to the subscriber unit (260) and advancing the code generator of the subscriber unit in accordance with the time delay. This permits transmissions from the subscriber unit (260) to be received synchronously at the satellite. The synchronization is maintained through the periodic transmission from the communications node (200) to the subscriber unit (260) of a message which commands the subscriber unit (260) to adjust the timing of its pseudonoise code generator. The resulting synchronous code division multiplexed system offers increased capacity over conventional systems.

Abstract: A constant phase crossbar switch system which avoids phase discontinuities at the outputs of the crossbar switch. The crossbar switch system includes input logic, a crossbar switch, output logic and a phase locked loop. The phase locked loop is used to generate a high speed internal clock from a system clock. High speed serial data streams transmitted at the internal clock frequency are received from corresponding transmitters and are coupled to the input logic. The input logic generates multiple versions of each serial data stream, one of the versions being undelayed and the other versions delayed by some fraction of a bit time. State machines are employed to selects the version of the serial data stream which results in the data stream data window being generally centered with respect to the high speed internal clock. The selected version of the data stream is employed as the active input to the crossbar switch.

Abstract: An improved acquisition and tracking system for Global Positioning System (GPS) signals. The system relies on block adjustment of the synchronizing signal of the bi-phase shift keying (BPSK) signal in order to obtain correct carrier frequency and phase angle. This improved system has the advantages of being more robust in the presence of noise than conventional approaches and also of lending itself to simplified implementation since synchronization of the Coarse/Acquisition (C/A) code need only be within half of a chip in order to maintain lock.

Abstract: A block radio design is disclosed that prevents the primary analog-to-digital converter from saturating and thus prevents the introduction of intermodulation products into the multi-carrier signal. The block radio comprises a strong signal suppressor that selectively suppresses any carrier signal in the multi-carrier signal before the multi-carrier signal is digitized by the analog-to-digital converter, thus preventing the possibility that the analog-to-digital converter can be saturated. Furthermore, the strong signal suppressor attenuates the stronger carrier signals without affecting the weaker carrier signals.

Abstract: According to the present disclosure, an parallel formatted data signal is applied to an input (300), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (606) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (706), the delayed second signal is applied to a second parallel-to-serial converter (708), and first and second bit-serial data streams are produced. A controller (710) synchronizes an Arithmetic Logic Unit (616) to the first and second bit-serial data streams so that the ALU (616) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.

Abstract: A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit for allocating an address to each channel of the multiplex data, a RAM for holding an information group obtained by a pointer extracting process and a pointer process, and RAM controlling unit for controlling a sequence of an operation to write-in/read-out the RAM to serially conduct the pointer process on the received multiplex data, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels.

Abstract: Apparatus and method for processing serial data signals. In one general aspect, the method features receiving a first serial data signal having a clock frequency and phase, detecting a phase characteristic of the first serial data signal, and delaying the first serial data signal based on the phase characteristic of the first serial data signal to align at least one point in the first serial data signal with at least one point in a system clock signal.

Abstract: A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.

Abstract: A method of implementing a time base change to a time-division multiplexec bitstream, for example an MPEG-2-compatible bitstream. The time base change is in response to a Time Base Change Flag. The bitstreams have video and audio packetized elementary streams, and each of these streams has a common time base. Each of the packetized elementary streams has a packet header, and packet data. The packet headers of the packetized elementary streams each contain a Presentation Time Stamp/Decoding Time Stamp flag field, a Presentation Time Stamp field, and a Decoding Time Stamp field. A time base change is indicated by a change in the PCR. The first step in changing the Time Base is receiving a discontinuity in the bitstream. This is used to disable synchronization of the video and audio bitstreams, and to mark a data byte in the bitstream associated with the Time Base Change Flag. The time base change is carried out and an interrupt is issued when the marked data byte arrives for decoding.

Abstract: The quality of service provided by a connection in transferring data units (19) between first and second points (A, B) across a network (10), is measured by a method involving monitoring the normal connection traffic at the first and second points (A, B) to detect the occurrence of the same events at each point (unit 22). An event is deemed to have occurred at a monitored network point when a predetermined set of criteria concerning one or more data units is satisfied by the connection data-unit traffic at the point concerned. Whenever an event is detected, an event report or "digest" is generated (unit 25), this digest including a signature based on the contents of the data units giving rise to the event. Digests from both monitored network points (A, B) are sent to a correlation unit (30) where digests relating to the occurrence of the same event at the two network points are matched up. The matched digest pairs are then passed to a measurement unit (31) to derive quality of service measurements.

Abstract: A radio selective paging receiver includes a reception unit, a control unit, and a timepiece unit. The reception unit is controlled to start transmission in synchronism with at least a standard time, receives a radio signal modulated by a selective paging signal containing time information in transmission information, and demodulates the radio signal. The control unit controls operation of the reception unit, determines call reception and time information in accordance with the demodulated signal, and processes the call reception and the time information. The timepiece unit at least temporarily holds the obtained time. In setting the time information obtained by operating the reception unit to the timepiece unit, the control unit adjusts the time with a predetermined time lag such that a carry to the minute or hour unit is not generated at a predetermined timing self data is received.

Abstract: A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device.

Abstract: A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver, includes a variable delay means which operates to introduce a delay shift into the said received radio signal. A correlator operates to correlate n-chips of the local reference code with n-samples of the received signal communicated thereto, and generates a correlation signal representative of a result of the correlation. A code acquisition controller operates in combination with the correlation signal to maintain the delay shift for at least one correlation and thereafter to change the delay shift, wherein the delay shift is a fraction of one chip period.

Abstract: Disclosed is a transmission frame format converter circuit with a first-in-first-out(FIFO) memory where the inputting and outputting of a data signal are conducted at different clock rates, which has: a write control circuit which writes write-in data and a frame pulse which is extracted from a transmission line and indicates a head position of the write-in data in the FIFO memory; and a read control circuit which judges that read-out data are valid only when the frame pulse to be read out from the read control circuit is active and then reads out the read-out data from the FIFO memory, and which judges that the read-out data are invalid and then conducts the resetting of the write control circuit and the FIFO memory.

Abstract: An asynchronous digital system, an asynchronous data path circuit, an asynchronous digital signal processing circuit and an synchronous digital signal processing method, which enables improved processing speed while maintaining high reliability are provided by dividing the overall chip into blocks with a specified area, forming the connection between the blocks by applying thereto a delay insensitive (DI) model or a quasi delay insensitive (QDI) model, while forming each block by applying thereto a scalable delay insensitive (SDI) model. In the SDI model, the system is configured using circuit components having a delay assumed during design in which if the specification states that a signal transition (b) in a subcircuit 7 precedes a signal transition (c) in a subcircuit 8, k.multidot.

Abstract: The invention describes a method for transmitting and forwarding packets over a packet switching network wherein the delay between two switches increases, decreases, or changes arbitrarily over time. Packets are being forwarded over each link inside the network in predefined periodic time intervals. The switches of the network maintain a common time reference, which is obtained either from an external source (such as GPS--Global Positioning System) or is generated and distributed internally. The time intervals are arranged with simple periodicity and complex periodicity (like seconds and minutes of a clock). When the delay increases at some point of time, a packet may be late for its predefined forwarding time interval. In such case, the packet is delayed until the next time interval of its virtual pipe. When the link delay decreases, packets are buffered until the first time interval of its virtual pipe.

Abstract: The present invention comprises a dynamic skew compensation circuit. The present invention includes a receiver, a plurality of channel inputs built into the receiver, and a delay stack structure coupled to the plurality of channel inputs. The receiver is adapted to accept data from a parallel data transfer cable. The channel inputs couple to each of the individual communications channels which comprise the parallel data transfer cable. The delay stack structure includes a plurality of delay stacks, each coupled to a respective channel input. Each delay stack dynamically selects an additional delay amount for its respective communications channel such that each communications channel of the parallel data transfer cable is deskewed with respect to the others. In so doing, the distances across which data can be received and the speeds at which data is transferred via the parallel data transfer cable is increased.

Abstract: A multimedia terminal having a host processor, an audio and video encoder and a system time clock. The encoders are input as digital video elementary frames into a multiplexer. The multiplexer includes a mux processor, a video FIFO and a video mux logic circuit coupled to both the mux processor and the video FIFO. Mux logic is operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in the FIFO to form the payload of a transport packet.