Particular Confinement Layer Patents (Class 372/45.01)
  • Patent number: 10290997
    Abstract: A method of producing an electronic component includes providing a surface comprising a first region and a second region adjoining the first region, arranging a sacrificial layer above the first region of the surface, arranging a passivation layer above the sacrificial layer and the second region of the surface, creating an opening in the passivation layer above the first region of the surface, wherein the opening in the passivation layer is created with an opening area that is smaller than the first region, and removing the sacrificial layer and the portions of the passivation layer that are arranged above the first region.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 14, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jens Mueller, Christoph Stephan, Robert Walter, Stefan Hartauer, Christian Rumbolz
  • Patent number: 10290996
    Abstract: A bottom-emitting vertical-cavity surface-emitting laser (VCSEL) structure includes a first substrate permitting the passage of light therethrough, an n-doped distributed Bragg reflector (nDBR), a p-doped distributed Bragg reflector (pDBR), one or more active layers, at least one of a high contrast grating mirror and a dielectric-enhanced metal mirror, and a plurality of layers, where the VCSEL structure is configured to be flip chipped to a second substrate. The pDBR and the nDBR define a laser cavity extending vertically therebetween and containing the one or more active layers. The at least one of a high contrast grating mirror and a dielectric-enhanced metal mirror may be disposed over the pDBR. The plurality of layers may be disposed over the at least one of the high contrast grating mirror and the dielectric-enhanced metal mirror to optically and hermetically seal the laser cavity.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 14, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sagi Varghese Mathai, Stanley Cheung, Wayne V. Sorin, Michael Renne Ty Tan
  • Patent number: 10283935
    Abstract: A vertical cavity surface emitting laser device includes a substrate, a first-type doped distributed Bragg reflector (DBR) disposed on the substrate, a first electrode disposed on the substrate, an active layer disposed on the first-type doped DBR, a second-type DBR disposed on the active layer, and a second electrode disposed on the second-type DBR. The second-type DBR defines a first doping concentration region, and a second doping concentration region disposed between the first doping concentration region and the active layer and that has a doping concentration less than that of the first doping concentration region. The second-type doped DBR has a confinement member formed in the first doping concentration region, and defining an aperture.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 7, 2019
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Babu Dayal Padullaparthi, Feng Lin
  • Patent number: 10267988
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin
  • Patent number: 10263137
    Abstract: A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1-z1As, the first window layer includes Alz2Ga1-z2As, and z1>z2.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 16, 2019
    Assignee: EPISTAR CORPORATION
    Inventor: Yi-Chieh Lin
  • Patent number: 10256368
    Abstract: Provided is a semiconductor substrate including a growth substrate, one or more compound semiconductor layers disposed on the growth substrate, and one or more control layers disposed between the compound semiconductor layers. Each control layer includes multiple nitride semiconductor layers including at least Al.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: April 9, 2019
    Assignee: SK Siltron Co., Ltd.
    Inventors: Jung-Hyun Eum, Kwang-Yong Choi, Jae-Ho Song, Dong-Kun Lee, Kye-Jin Lee, Young-Jae Choi
  • Patent number: 10256372
    Abstract: A display device including a backplane, a plurality of light-emitting devices, a first distributed Bragg reflector layer and a second distributed Bragg reflector layer is provided. The light-emitting devices are disposed on the backplane. The first distributed Bragg reflector layer is disposed between the backplane and the light-emitting devices. The light-emitting devices are disposed between the first distributed Bragg reflector layer and the second distributed Bragg reflector layer. A projected area of the first distributed Bragg reflector layer on the backplane is larger than a projected area of one of the light-emitting devices on the backplane or a projected area of the second distributed Bragg reflector layer on the backplane is larger than a projected area of one light-emitting device on the backplane.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 9, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Yu-Hung Lai, Tzu-Yang Lin
  • Patent number: 10250012
    Abstract: A vertical cavity surface emitting laser (VCSEL) array may include a plurality of VCSELs. A size of an emission area of a first VCSEL, of the plurality of VCSELs, may be different from a size of an emission area of a second VCSEL of the plurality of VCSELs. The first VCSEL may be located closer to a center of the VCSEL array than the second VCSEL. A difference between the size of the emission area of the first VCSEL and the size of the emission area of the second VCSEL may be associated with reducing a difference in operating temperature between the first VCSEL and the second VCSEL, or reducing a difference in optical power output between the first VCSEL and the second VCSEL.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 2, 2019
    Assignee: Lumentum Operations LLC
    Inventors: Ajit Vijay Barve, Eric R. Hegblom
  • Patent number: 10243330
    Abstract: Optical beam quality of an optoelectronic device is improved by suppression of high-order transverse optical modes by their resonant interaction with the continuum of modes in the surrounding regions, such continuum being realized by replacement of one or several layers by layers having a lower refractive index. In particular, selective oxidation of GaAlAs-based vertical cavity surface emitting laser results in (Ga)AlO layers surrounding the aperture and having a lower refractive index than the original (Ga)AlAs layers. The continuum of optical modes originates due to the modification of the optical field in the areas surrounding the aperture caused by the low index insertions positioned to result in enhancement of the optical field in their vicinity.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 26, 2019
    Assignee: VI SYSTEMS GMBH
    Inventors: Nikolay Ledentsov, Vitaly Shchukin
  • Patent number: 10230215
    Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 12, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Luke Graham, Andy MacInnes
  • Patent number: 10193308
    Abstract: Embodiments may relate to a multiple quantum well (MQW) laser for operating at high temperatures, comprising at least one quantum well made of compressively strained InGaAlAs layers that are alternatively stacked with tensile strained InGaAlAs layers, the at least one quantum well surrounded on one side by a n-doped InP cladding and on the other by a p-doped InP cladding so as to form a double hetero-junction. A confinement layer of lattice-matched InAlAs may be provided between the quantum well and the p-doped cladding, having a first surface facing or adjacent to the quantum well and a second surface facing or adjacent to the p-doped cladding. An additional electron containment layer of tensile strained InAlAs may be provided facing or adjacent to one surface of the confinement layer, having a thickness smaller than that of the confinement layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventor: Pierre Doussiere
  • Patent number: 10193023
    Abstract: A light-emitting diode chip including a p-type semiconductor layer, a light-emitting layer, an n-type semiconductor layer, and a first metal electrode is provided. The light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. The n-type semiconductor layer includes a first n-type semiconductor sub-layer, a second n-type semiconductor sub-layer, and an ohmic contact layer. The ohmic contact layer is disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer. The first metal electrode is disposed on the first n-type semiconductor sub-layer. A region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, so as to form ohmic contact between the first metal electrode and the ohmic contact layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 29, 2019
    Assignee: PlayNitride Inc.
    Inventors: Jyun-De Wu, Yu-Yun Lo
  • Patent number: 10186840
    Abstract: A semiconductor laser including current block layers disposed between a p-type clad layer and a p-type light guide layer and a current confinement region which is a region between the current block layers is configured as follows. A width of an opening portion of an insulating layer is made narrow above a wide portion of the current confinement region in which the wide portion, a tapered portion, a narrow portion, a tapered portion and the wide portion are disposed in this order between an incidence side (HR side) and an emission side (AR side), and both ends of the wide portion are covered by an insulating layer. According to such a configuration, it is possible to suppress generation of super luminescence in the wide portion, and it is thus possible to achieve improvement in beam quality and higher output of the beam.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuo Fukagai
  • Patent number: 10177533
    Abstract: An edge-emitting semiconductor laser and a method for operating a semiconductor laser are disclosed. In an embodiment, the edge-emitting semiconductor laser includes an active zone within a semiconductor layer sequence and a stress layer. The active zone is configured for being energized only in a longitudinal strip perpendicular to a growth direction of the semiconductor layer sequence. The semiconductor layer sequence has a constant thickness throughout in the region of the longitudinal strip so that the semiconductor laser is gain-guided. The stress layer may locally stress the semiconductor layer sequence in a direction perpendicular to the longitudinal strip and in a direction perpendicular to the growth direction. A refractive index of the semiconductor layer sequence, in regions which, seen in plan view, are located next to the longitudinal strip, for the laser radiation generated during operation is reduced by at least 2×10?4 and by at most 5×10?3.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 8, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Alexander Bachmann
  • Patent number: 10163024
    Abstract: Provided are: an acquisition section that acquires image data; a detection section that detects a marker portion indicated in the image data; a communication section that performs communication with either one or a plurality of external servers including at least one of a plurality of dictionary functions; a processing section that (i) specifies, from the dictionary functions, a dictionary function in accordance with a type of the marker portion, and (ii) causes the communication section to transmit, to the external server including the specified dictionary function, an instruction to search for a text indicated by the marker portion, and for information related to the text, by using the dictionary function; and a generation section that generates a glossary including the received information related to the text upon reception of the information related to the text as a search result from the external server by the communication section.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 25, 2018
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Sachiko Yoshimura, Yumi Nakagoshi, Akihiro Umenaga, Naoto Hanatani, Hironori Hayashi
  • Patent number: 10153397
    Abstract: A semiconductor light-emitting device includes a first conductive semiconductor layer on a substrate, a superlattice layer including a plurality of first quantum barrier layers and a plurality of first quantum well layers, the plurality of first quantum barrier layers and the plurality of first quantum well layers being alternately stacked on the first conductive semiconductor layer, an active layer on the superlattice layer, and a second conductive semiconductor layer on the active layer, wherein a Si doping concentration of at least one of the plurality of first quantum well layers is equal to or greater than 1.0×1016/cm3 and less than or equal to 1.0×1018/cm3. Thus, the semiconductor light-emitting device may have increased light output and reliability.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-seok Choi, Min-ho Kim, Jeong-wook Lee, Jai-won Jean, Chul-min Kim, Jae-deok Jeong, Min-hwan Kim, Jang-mi Kim
  • Patent number: 10153614
    Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 11, 2018
    Assignee: APPLE INC.
    Inventors: Chin Han Lin, Weiping Li, Xiaofeng Fan
  • Patent number: 10141720
    Abstract: A nitride semiconductor laser element includes an electron barrier layer between a p-side light guide layer and a p-type clad layer. The electron barrier layer has a bandgap energy larger than that of the p-type clad layer. The p-side light guide layer is made of AlxGa1?xN containing no Indium, where 0?x<1. A film thickness dn of the n-side light guide layer and a film thickness dp of the p-side light guide layer satisfy relationships dp?0.25 ?m and dn?dp.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: November 27, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Masao Kawaguchi, Osamu Imafuji, Shinichiro Nozaki, Hiroyuki Hagino
  • Patent number: 10134948
    Abstract: An improved light emitting heterostructure is provided. The heterostructure includes an active region having a set of barrier layers and a set of quantum wells, each of which is adjoined by a barrier layer. The quantum wells have a delta doped p-type sub-layer located therein, which results in a change of the band structure of the quantum well. The change can reduce the effects of polarization in the quantum wells, which can provide improved light emission from the active region.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 20, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska
  • Patent number: 10135226
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10122153
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1?y), where 0.8<y<1, and SizGe(1?z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10109982
    Abstract: A semiconductor device includes: a semiconductor layered structure including an active layer, a first region including a part of the active layer and extending in a layered direction, a second region including at least a part of an end portion of the active layer and extending in the layered direction, disordering of the second region being higher than the first region, and a third region including a portion of the active layer between the first region and the second region and extending in the layered direction, disordering of the third region being higher than the first region and lower than the second region; and an electrode configured to inject an electric current to the active layer.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 23, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Hidehiro Taniguchi
  • Patent number: 10107749
    Abstract: An active plasmon sensor comprising a single crystalline semiconductor CdS nano-slab atop a silver surface separated by a magnesium fluoride (MgF2) gap layer. The surface plasmon effect localizes the electromagnetic field at the interface between the metal and semiconductor, allowing both the device's physical size and mode confinement to shrink down to the nanometer scale in a dimension perpendicular to the metal surface.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 23, 2018
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Zhang, Ren-Min Ma, Sadao Ota
  • Patent number: 10096975
    Abstract: A laterally grown edge emitting laser is provided. A semiconductor structure is disposed on a substrate. A first, a second and a third III-V optical layers are sequentially and laterally grown on and from a sidewall of the semiconductor structure. A cladding semiconductor layer is disposed next to the third III-V optical layer and electrically connected to the III-V optical layer. Then, a first contact structure and a second contact structure is disposed on and electrically connected to the semiconductor structure and the cladding semiconductor layer, respectively. In the edge emitting laser, each of the first, second and third III-V optical layers may independently include a III-V semiconductor including at least one of group III elements of boron (B), gallium (Ga), aluminum (Al) and indium (In), and at least one of group V elements of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ning Li
  • Patent number: 10090643
    Abstract: A light-emitting device is provided. The light-emitting device comprises: an epitaxial structure comprising a first DBR stack, a light-emitting stack and a second DBR stack and a contact layer in sequence; an electrode on the epitaxial structure; a current blocking layer between the contact layer and the electrode; a first opening formed in the current blocking layer; and a second opening formed in the electrode and within the first opening; wherein a part of the electrode fills in the first opening and contacts the contact layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: October 2, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hsu, Yi-Wen Huang, Yi-Hung Lin, Chih-Chiang Lu
  • Patent number: 10069280
    Abstract: A semiconductor optical element includes a semiconductor layer portion that includes an optical waveguide layer. The semiconductor layer portion contains a first impurity having a function of suppressing atomic vacancy diffusion and a second impurity having a function of promoting atomic vacancy diffusion, between a topmost surface of the semiconductor layer portion and the optical waveguide layer. The semiconductor layer portion includes two or more regions that extend in a deposition direction with different contents of at least one of the impurities. At least one of the two or more regions contains both the first impurity and the second impurity. The two or more regions have different degrees of disordering in the optical waveguide layer achieved through atomic vacancy diffusion and different band gap energies of the optical waveguide layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 4, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kouhei Kinugawa, Hidehiro Taniguchi, Masafumi Tajima
  • Patent number: 10062565
    Abstract: A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Shinya Takado, Norikazu Ito, Atsushi Yamaguchi
  • Patent number: 10054740
    Abstract: Some embodiments of the present disclosure describe a tapered waveguide and a method of making the tapered waveguide, wherein the tapered waveguide comprises a first and a second waveguide, wherein the first and second waveguides overlap in a waveguide overlap area. The first and second waveguides have a different size in at least one dimension perpendicular to an intended direction of propagation of electromagnetic radiation through the tapered waveguide. Across the waveguide overlap area, one of the waveguides gradually transitions or tapers into the other.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 21, 2018
    Assignee: INTEL CORPORATION
    Inventors: Yoel Chetrit, Judson D. Ryckman, Jeffrey B. Driscoll, Harel Frish, Ling Liao
  • Patent number: 10050173
    Abstract: A light emitting device includes a semiconductor light emitting unit and a light-transmitting substrate. The light-transmitting substrate includes an upper surface having two long sides and two short sides and a side surface, and the semiconductor light emitting unit is disposed on the upper surface. The side surface includes two first surfaces, two second surfaces, and rough micro-structures. Each of the first surfaces is connected to one of the long sides of the upper surface, and each of the second surfaces is connected to one of the short sides of the upper surface. The rough micro-structures are formed on the first surfaces and the second surfaces, a covering rate of the rough micro-structures on each of the first surfaces is greater than or equal to a covering rate of the rough micro-structures on each of the second surfaces. A manufacturing method of the light emitting device is also provided.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 14, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Jing-En Huang, Kai-Shun Kang, Yu-Chen Kuo, Fei-Lung Lu, Teng-Hsien Lai
  • Patent number: 10050736
    Abstract: An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 14, 2018
    Assignee: INPHI CORPORATION
    Inventor: Radhakrishnan L. Nagarajan
  • Patent number: 10050413
    Abstract: A semiconductor laser apparatus is provided and has a substrate, a first type cladding layer, a first type waveguide layer, an active layer, a second type waveguide layer, a second type cladding layer, and a capping layer disposed in sequence. The active layer has a light producing portion and a light emitting portion. A laser produced by the light producing portion, emits along a direction from the light producing portion toward the light emitting portion. The light emitting portion includes a first inactive region, a light emitting region, and a second inactive region. A refractive index of the light emitting region is lower than a refractive index of the first inactive region, the refractive index of the light emitting region is lower than a refractive index of the second inactive region, and width of a first part of the light emitting region continuously increases along the direction.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 14, 2018
    Assignee: Landmark Optoelectronics Corporation
    Inventors: Shu-Wei Chiu, Yin-Jie Ma, Wei Lin
  • Patent number: 10033160
    Abstract: An interband cascade (IC) light emitting device comprising a plurality of interband cascade stages, wherein at least one of the IC stages is constructed to have an electron injector made of one or more QWs, a type-I quantum well (QW) active region, a barrier layer positioned between the active region and the electron injector, a hole injector made of one or more QWs, and a barrier layer positioned between the active region and the hole injector. In at least one embodiment, a type II heterointerface layer is between the electron injector and an adjacent hole injector. The well layer of the type-I QW active region has compressive strain, while the barrier layers which flank the type-I QW active region comprise tensile strain layers. In certain embodiments, the electron injector and the hole injector comprise tensile strained layers.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 24, 2018
    Assignees: The Board of Regents of the University of Oklahoma, National Research Council of Canada
    Inventors: Rui Q. Yang, James A. Gupta
  • Patent number: 10027090
    Abstract: A laser diode chip is described. In an embodiment the laser diode chip includes an n-type semiconductor region, a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region, wherein the active layer is in the form of a single quantum well structure. The single quantum well structure includes a quantum well layer, which is arranged between a first barrier layer and a second barrier layer, wherein the first barrier layer faces the n-type semiconductor region, and the second barrier layer faces the p-type semiconductor region. An electronic bandgap EQW of the quantum well layer is smaller than an electronic bandgap EB1 of the first barrier layer and smaller than an electronic bandgap EB2 of the second barrier layer, and the electronic bandgap EB1 of the first barrier layer is larger than the electronic bandgap EB2 of the second barrier layer.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 17, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Christoph Eichler, Teresa Wurm
  • Patent number: 9997891
    Abstract: A tunable source includes a short-cavity laser optimized for performance and reliability in SSOCT imaging systems, spectroscopic detection systems, and other types of detection and sensing systems. The short cavity laser has a large free spectral range cavity, fast tuning response and single transverse, longitudinal and polarization mode operation, and includes embodiments for fast and wide tuning, and optimized spectral shaping. Disclosed are both electrical and optical pumping in a MEMS-VCSEL geometry with mirror and gain regions optimized for wide tuning, high output power, and a variety of preferred wavelength ranges; and a semiconductor optical amplifier, combined with the short-cavity laser to produce high-power, spectrally shaped operation. Several preferred imaging and detection systems make use of this tunable source for optimized operation are also disclosed.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 12, 2018
    Assignees: Thorlabs, Inc., Praevium Research, Inc.
    Inventors: Alex Ezra Cable, Vijaysekhar Jayaraman, Benjamin Michael Potsaid
  • Patent number: 9991421
    Abstract: According to one embodiment, a method for manufacturing an LED device includes forming a laminated semiconductor layer including a GaN layer of a first conductivity type, a GaN-based luminous layer, and a GaN layer of a second conductivity type stacked in this order on a surface of a substrate, forming a resist pattern on the laminated semiconductor layer, subjecting the laminated semiconductor layer to reactive ion etching using the resist pattern as a mask to selectively remove the laminated semiconductor layer to form an LED element structure part and an electrode connection region, removing the resist pattern, and treating the substrate including the LED element structure part and the electrode connection region with a first etching residue removing aqueous solution.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 5, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ikuo Uematsu, Makoto Saito, Shinya Ito, Kengo Furutani, Shinichi Sasaki
  • Patent number: 9991666
    Abstract: A semiconductor laser device includes a substrate, a buffer layer provided on an upper surface of the substrate and formed of InP, a laser element having a ridge structure formed above the buffer layer, and an epi intermediate layer formed of a compound semiconductor containing As and exposed to the outside.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 5, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Morita
  • Patent number: 9977188
    Abstract: A method of fabricating a waveguide mode expander includes providing a substrate including a waveguide, bonding a chiplet including multiple optical material layers in a mounting region adjacent an output end of the waveguide, and selectively removing portions of the chiplet to form tapered stages that successively increase in number and lateral size from a proximal end to a distal end of the chiplet. The first optical material layer supports an input mode substantially the same size as a mode exiting the waveguide. One or more of the overlying layers, when combined with the first layer, support a larger, output optical mode size. Each tapered stage of the mode expander is formed of a portion of a respective layer of the chiplet. The first layer and the tapered stages form a waveguide mode expander that expands an optical mode of light traversing the chiplet.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: May 22, 2018
    Assignee: Skorpios Technologies, Inc.
    Inventors: Damien Lambert, Guoliang Li, John Zyskind, Stephen B. Krasulick
  • Patent number: 9979158
    Abstract: A vertical cavity surface emitting laser comprising a first reflector, a second reflector comprising a layer stack of semiconductor or isolating layers, an active region arranged between the first and second reflectors, and an additional layer on top of the layer stack at the light output side, said additional layer forming an output interface of the laser, wherein the refractive index of the additional layer is smaller, equal to or larger than the smallest refractive index of the refractive indices of said layer stack.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 22, 2018
    Assignee: Technische Universitaet Berlin
    Inventors: Dieter Bimberg, Gunter Larisch, James A. Lott
  • Patent number: 9972973
    Abstract: A semiconductor laser diode type of a buried-hetero structure (BH-LD) is disclosed. The LD provides a mesa, a first burying layer, and a second burying layer, where the burying layers are provided in respective sides of the mesa so as to expose a top of the mesa. The mesa includes a lower cladding layer, an active layer, and an upper cladding layer, where the cladding layers have conduction type opposite to each other and, combined with the burying layers, constitute a carrier confinement structure. The second burying layer has an even surface overlapping with an even surface of the first burying layer, and has a thickness in a portion of the even surface that is thinner than a thickness thereof in a portion except for the even surface.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 15, 2018
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Takayuki Watanabe
  • Patent number: 9972972
    Abstract: A vertical cavity light emitting device includes: a first multilayer film reflector; a semiconductor structure layer that is formed on the first multilayer film reflector and includes a semiconductor layer of a first conductivity type, an active layer, and a semiconductor layer of a second conductivity type opposite to the first conductivity type; an insulating current confinement layer formed on the semiconductor layer of the second conductivity type; a through opening formed in the current confinement layer; a transparent electrode for covering the through opening and the current confinement layer, the transparent electrode being in contact with the semiconductor layer of the second conductivity type through the through opening; a second multilayer film reflector formed on the transparent electrode; and a mixed composition layer formed to be in contact with an edge of the through opening and in which the current confinement layer and the transparent electrode are mixed.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 15, 2018
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Komei Tazawa, Ji-Hao Liang, Seiichiro Kobayashi, Masaru Takizawa, Keisuke Nakata
  • Patent number: 9966734
    Abstract: The present invention discloses a semiconductor laser comprising an optical waveguide structure which may include a lower waveguide layer, an active layer of multiple quantum wells and an upper waveguide layer, which are successively stacked from bottom to top, a grating layer being formed on upper portion of the active layer, wherein the upper waveguide layer, a cladding layer and a contact layer are formed as a ridge which has a light incidence end surface and a light output end surface, wherein a beam expanding structure is formed on one end of the output end surface. The beam expanding structure has a beam expanding portion with a shape gradually contracted inwards from the light output end surface. Preferably, the beam expanding portion has a horizontal divergence angle of 5° to 20°.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 8, 2018
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Ninghua Zhu, Jianguo Liu, Jinjin Guo, Wei Chen
  • Patent number: 9933576
    Abstract: An electro-optic device may include a photonic chip including an insulator layer, and a semiconductor layer over the insulator layer and defining an optical grating coupler. The optical grating coupler may have a series of alternating curved ridges and valleys. The optical grating coupler has first and second sides and a medial portion. The medial portion has a medial grating period T based upon a targeting wavelength. One or more of the first and second sides have a side grating period different than T.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 3, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Charles Baudot
  • Patent number: 9927574
    Abstract: An optical component includes a component body, and at least one angled-facet waveguide formed in the component body, wherein the angled-facet waveguide is substantially mirror-symmetrical in shape relative to a line at or near the center of the angled-facet waveguide.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Daniel M. Kuchta, Benjamin Giles Lee, Laurent Schares, Clint Lee Schow
  • Patent number: 9929293
    Abstract: In a superlattice (SL) photodetector, each period of the SL includes first and second semiconductor layers having different compositions, at least one of which comprises indium arsenide (InAs). At least one of these two semiconductor layers has a graded composition. In embodiments, the first semiconductor layer comprises InAs and the second semiconductor layer is a graded layer comprising indium arsenide antimonide (InAsSb), wherein the antimony (Sb) concentration is varied. In examples, the Sb concentration in the second layer gradually increases from the top and bottom toward the middle of the layer.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: March 27, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jin K. Kim, John F. Klem, Eric A. Shaner, Benjamin Varberg Olson, Emil Andrew Kadlec, Anna Tauke-Pedretti, Torben Ray Fortune
  • Patent number: 9922887
    Abstract: Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 20, 2018
    Assignee: Acacia Communications, Inc.
    Inventors: Diedrik Vermeulen, Long Chen, Christopher Doerr
  • Patent number: 9917414
    Abstract: A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light. The second semiconductor material of the photonic light generating device is present in a via opening that is provided into a waveguide core material and an underlying dielectric material. The via opening exposes a surface of the first semiconductor material.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana
  • Patent number: 9912118
    Abstract: Semiconductor laser with mirror facet protection against degradation including a modified segment near the exit window that has a double waveguide with a reduced confinement factor compared with the confinement factor of the double waveguide of the main laser segment, such that the radiation at the exit facet in the modified double waveguide is pushed away from the active region, less radiation is absorbed at the facet and less heat is produced by nonradiative recombination at the exit facet, while the field distribution of the two double waveguides have a good overlap and low transfer losses due to the use of waveguide type structures with an active waveguide and a passive trapping waveguide.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 6, 2018
    Inventor: Iulian Basarab Petrescu-Prahova
  • Patent number: 9881849
    Abstract: An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: January 30, 2018
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Kyle W. Maples, Daniel J. Ewing
  • Patent number: 9873308
    Abstract: The invention relates to a heating system for heating a living being, for instance, a person (2) within a vehicle (1) being preferentially a hybrid car or an electric car. The heating system comprises an infrared laser system (5, 6) for illuminating the living being with infrared laser light, thereby heating the living being. Thus, heating radiation is used, which has a high collimation and which can be focused relatively easily. The heating can therefore be confined to a certain region, in which the living being is located. The heating can even be confined to the living being or to parts of the living being only. This more focused heating allows for a reduction of the energy consumption.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 23, 2018
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Holger Moench, Mark Carpaij
  • Patent number: 9871349
    Abstract: There is provided a light-emitting element including a laminated structure including a first compound semiconductor layer having a first conductivity type, a second compound semiconductor layer having a second conductivity type different than the first conductivity type, and a third compound semiconductor layer formed between the first and second compound semiconductor layers and including an active layer. A second end surface of the second compound semiconductor layer and a third end surface of the third compound semiconductor layer are formed at respective second and third angles theta2 and theta3 relative to a virtual vertical direction of the laminated structure and satisfy the following relationship: “absolute value of theta3 is equal to or greater than 0 degree and smaller than absolute value of theta2”.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 16, 2018
    Assignee: SONY CORPORATION
    Inventors: Kunihiko Tasai, Eiji Nakayama, Yuusuke Nakayama, Shigetaka Tomiya