Particular Confinement Layer Patents (Class 372/45.01)
  • Patent number: 10594111
    Abstract: A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles Caër, Lukas Czornomaz
  • Patent number: 10587092
    Abstract: In a semiconductor laser according to an embodiment of the present disclosure, a ridge part has a structure in which a plurality of gain regions and a plurality of Q-switch regions are each disposed alternately with each of separation regions being interposed therebetween in an extending direction of the ridge part. The separation regions each have a separation groove that separates from each other, by a space, the gain region and the Q-switch region adjacent to each other. The separation groove has a bottom surface at a position, in a second semiconductor layer, higher than a part corresponding to a foot of each of both sides of the ridge part. The semiconductor laser includes an electrode provided over the bottom surface of each separation groove with an insulating layer being interposed therebetween.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 10, 2020
    Assignee: SONY CORPORATION
    Inventors: Tomoki Ono, Mikio Takiguchi, Toyoharu Oohata, Takahiro Koyama
  • Patent number: 10574032
    Abstract: A semiconductor module of the present disclosure includes: a base body including a groove part of which two inner side surfaces are inclined, the base body including an electrode pad which is provided on at least one inner side surface; and a semiconductor element including a semiconductor substrate including a first surface, a second surface opposite to the first surface, and two side surfaces which are inclined in a diagonal direction to the first surface and are opposite to each other, a semiconductor layer located on the first surface, and an electrode disposed on at least one side surface. The semiconductor element is located in the groove part so that the at least one side surface is disposed along the at least one inner side surface of the base body, and at least one electrode of the semiconductor element is connected to the electrode pad of the base body.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: February 25, 2020
    Assignee: Kyocera Corporation
    Inventors: Takehiro Nishimura, Chiaki Doumoto
  • Patent number: 10564353
    Abstract: Some embodiments of the present disclosure describe a tapered waveguide and a method of making the tapered waveguide, wherein the tapered waveguide comprises a first and a second waveguide, wherein the first and second waveguides overlap in a waveguide overlap area. The first and second waveguides have a different size in at least one dimension perpendicular to an intended direction of propagation of electromagnetic radiation through the tapered waveguide. Across the waveguide overlap area, one of the waveguides gradually transitions or tapers into the other.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Yoel Chetrit, Judson D. Ryckman, Jeffrey B. Driscoll, Harel Frish, Ling Liao
  • Patent number: 10554017
    Abstract: Edge-emitting laser diodes having high confinement factors and lattice-matched, porous cladding layers are described. The laser diodes may be formed from layers of III-nitride material. A cladding layer may be electrochemically etched to form a porous cladding layer having a high refractive index contrast with an active junction of the device. A transparent conductive oxide layer may be deposited to form a top-side cladding layer with high refractive index contrast and low resistivity.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 4, 2020
    Assignee: Yale University
    Inventors: Jung Han, Yufeng Li, Ge Yuan
  • Patent number: 10551645
    Abstract: According to one embodiment, a waveguide element includes a first crystal region, and a second crystal region. The first crystal region extends in a first direction and includes a first nitride semiconductor. The second crystal region extends in the first direction, includes a second nitride semiconductor, and is continuous with the first crystal region. A second direction crosses the first direction. The second direction is from the first crystal region toward the second crystal region. A <0001> direction of the first crystal region is from the first crystal region toward the second crystal region. A <0001> direction of the second crystal region is from the second crystal region toward the first crystal region.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Hikosaka
  • Patent number: 10545200
    Abstract: A system and method for performing vector magnetometry are described. A method can include illuminating diamond with a modulated optical signal and a modulated microwave (MW) signal. A first, bias magnetic field is also applied to the diamond. Light emitted from the diamond in response to the optical signal, the MW signal, and the first magnetic field is detected via a single detector at a fixed position relative to the diamond. A modulation of the detected light encodes information corresponding to a plurality of nitrogen vacancy (NV) axes of the diamond.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 28, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: John Francis Barry, Jennifer May Schloss, Matthew James Turner, Mikael Paul Backlund, Ronald Walsworth
  • Patent number: 10547160
    Abstract: The optical mode of a photonic device is coupled between a first region made of a semiconducting material, and a second region made of a dielectric material. Photons are generated within the first region, while the optical mode is predominantly stored within the second region. The thickness of the first region and its width are controlled to determine its effective refractive index, enabling control of the optical mode.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 28, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Christos T. Santis, Amnon Yariv
  • Patent number: 10546974
    Abstract: Disclosed are a light-emitting device, a method of fabricating the same, a light-emitting device package, and a lighting system. The light-emitting device includes a first-conductivity-type semiconductor layer, an active layer disposed on the first-conductivity-type semiconductor layer and including a quantum well having a composition of InxGa1-xN (0<x<1) and a quantum barrier having a composition of InyGa1-yN (0?y<1), and a second-conductivity-type semiconductor layer disposed on the active layer. The active layer includes a first quantum well disposed on the first-conductivity-type semiconductor layer, a first quantum barrier disposed on the first quantum well, a second quantum well disposed on the first quantum barrier, and a second quantum barrier disposed on the second quantum well.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: January 28, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Hyun Oh Kang
  • Patent number: 10541136
    Abstract: In one aspect a method of fabricating an n-doped strained germanium (Ge) film is disclosed, which includes depositing a strained Ge film on an underlying substrate, implanting at least one electron-donating dopant in the Ge film, and exposing the implanted Ge film to one or more laser pulses having a pulsewidth in a range of about 1 ns to about 100 ms so as to generate a substantially crystalline strained Ge film. In some embodiments, the pulses can cause melting followed by substantial recrystallization of at least a portion of the implanted Ge film. In some embodiments, the resultant Ge film can have a thickness in a range of about 10 nm to about 1 microns.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 21, 2020
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Eric Mazur, Michael J. Aziz, Hemant Gandhi, David Pastor
  • Patent number: 10541511
    Abstract: A semiconductor light-emitting element includes a laminated structure which has an active layer between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, a first semiconductor layer which includes at least the first conductivity-type semiconductor layer of the laminated structure, an insulation film which is formed on the first semiconductor layer and has an opening, and a second semiconductor layer which is formed on the insulation film and includes at least the second conductivity-type semiconductor layer of the laminated structure. The second semiconductor layer includes a first region facing the opening of the insulation film and a second region not facing the opening, and the second region has a portion with a higher impurity concentration than the first region.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventors: Kota Tokuda, Takayuki Kawasumi
  • Patent number: 10534132
    Abstract: Some embodiments are directed to a method for manufacturing photonic waveguides and to photonic waveguides manufactured by this method.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 14, 2020
    Assignees: UNIVERSITÉ DE FRANCHE-COMTÉ, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Nadège Courjal, Fabien Henrot, Ètienne Fizaine, Clément Guyot
  • Patent number: 10529890
    Abstract: Provided is a light emitting semiconductor structure that operates as a light emitting diode (LED). In embodiments of the invention, the light emitting semiconductor structure includes a first barrier region, a second barrier region, and a single quantum well having a preselected thickness between the first barrier region and the second barrier region. The preselected thickness according to embodiments is selected to achieve a predetermined charge density in the quantum well. The predetermined charge density according to embodiments results from a predetermined bias current applied to the semiconductor structure. The predetermined bias current according to embodiments comprises less than about 1 mA.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ning Li, Qinglong Li, Kunal Mukherjee, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10522708
    Abstract: A method for allowing a reflective layer to abut against an edge of a metal contact while preventing contamination of a metal contact for an LED die is provided. The method includes encapsulating an electrical contact (i.e. metal contact) via with a barrier layer prior to deposition of a reflective film layer. The barrier layer encapsulates the metal contact by defining a mask pattern with a larger size than the metal contact via, which prevents the metal contact from becoming contaminated by the reflective film. This encapsulation reduces contamination of the metal contact and also reduces the voltage drop during operation of the LED die.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 31, 2019
    Assignee: LUMILEDS LLC
    Inventors: Yue Chau Kwan, Li Ma, Liang Zhang, Kenneth Morgan Davis, Bing Xuan Li
  • Patent number: 10516252
    Abstract: A laser diode includes an active zone that emits radiation in a lateral emission angle range in a plane of the active zone via an emission side of a layer arrangement, an electrical contact is configured on a top side of the layer arrangement, the electrical contact includes a metallic adhesion layer and at least one metallic contact layer, the adhesion layer is arranged on the layer arrangement, the adhesion layer includes a layer stack including a first and a second layer, the first layer is arranged on the layer arrangement, the first layer is configured in a planar fashion, the second layer is subdivided into at least one first and at least one second partial surface, the adhesion layer is arranged in the first partial surface, and the contact layer is arranged on the first partial surface and in the second partial surface.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 24, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Alexander Bachmann, Volker Grossmann
  • Patent number: 10510577
    Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 10511148
    Abstract: A tunable laser device is provided. The tunable laser device includes an active layer configured to generate first light by a first source; first and second reflective layers spaced apart from each other having the active layer disposed between the first reflective layer and the second reflective layer to form a resonance cavity; and a variable refractive index unit in the resonance cavity and having a refractive index being variable according to a second source, the second source being different from the first source.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jineun Kim, Unjeong Kim, Hyochul Kim, Yeonsang Park, Moonil Jung
  • Patent number: 10498108
    Abstract: A surface-emitting laser array includes a plurality of light emitting parts. Each light emitting part includes a reflection mirror including aluminum gallium arsenide (AlxGa(1-x)As) where x is greater than 0.95 but less than or equal to 1; an active layer; and an electrode surrounding an emission region, from which laser light is emitted, the electrode covering a region between adjacent light emitting parts in the plurality of light emitting parts.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: December 3, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazuma Izumiya, Naoto Jikutani, Masayuki Numata
  • Patent number: 10497629
    Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 10490708
    Abstract: Embodiments of the invention include a semiconductor light emitting device capable of emitting first light having a first peak wavelength and a semiconductor wavelength converting element capable of absorbing the first light and emitting second light having a second peak wavelength. The semiconductor wavelength converting element is attached to a support and disposed in a path of light emitted by the semiconductor light emitting device. The semiconductor wavelength converting element is patterned to include at least two first regions of semiconductor wavelength converting material and at least one second region without semiconductor wavelength converting material disposed between the at least two first regions.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 26, 2019
    Assignee: LUMILEDS LLC
    Inventors: Michael David Camras, Oleg Borisovich Shchekin, Rafael Ignacio Aldaz Granell, Patrick Nolan Grillot, Frank Michael Steranka
  • Patent number: 10483721
    Abstract: A vertical cavity light-emitting device includes: a semiconductor substrate having a hexagonal crystal structure; a line mask extending linearly along at least one of a [11-20] direction and directions equivalent to the [11-20] direction on a c-plane of the semiconductor substrate; a first reflector provided on an exposed region exposed from the line mask on the c-plane of the semiconductor substrate, the first reflector comprising a high refractive index semiconductor film and a low refractive index semiconductor film having a refractive index smaller than that of the high refractive index semiconductor film, the high refractive index semiconductor film and the low refractive index semiconductor film being alternately layered; a light-emitting structure layer provided on the first reflector; and a second reflector disposed on the light-emitting structure layer so as to be opposed so the first reflector.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 19, 2019
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Komei Tazawa, Ji-Hao Liang, Seiichiro Kobayashi
  • Patent number: 10454249
    Abstract: In a semiconductor laser device, a n-type cladding layer, a multi-quantum well active layer, and a p-type cladding layer are sequentially laminated on an n-type substrate, and a stripe structure is provided on this semiconductor laminated section. The n-type cladding layer has a first n-type cladding layer configured of Alx1Ga1-x1As (0.4<x1?1), and a second n-type cladding layer configured of (Alx2Ga1-x2)1-y2Iny2P (0?x2?1, 0.45?y2?0.55). The p-type cladding layer is configured of (Alx3Ga1-x3)1-y3Iny3P (0?x3?1, 0.45?y3?0.55). The width of the stripe structure is 10 ?m or more, and the refractive index with respect to the laser oscillation wavelength of the first n-type cladding layer is less than or equal to the refractive index with respect to the laser oscillation wavelength of the second n-type cladding layer.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: October 22, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tomoya Inoue
  • Patent number: 10451477
    Abstract: The present invention relates to a monitoring apparatus for a laser beam, including a body having a passage opening and a sensor that is disposed on the body, wherein impact of the laser beam onto the body can be detected using the sensor.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 22, 2019
    Assignee: MBDA Deutschland GmbH
    Inventor: Georg Beidenhauser
  • Patent number: 10444593
    Abstract: Methods and systems for a vertical junction high-speed phase modulator are disclosed and may include a semiconductor device having a semiconductor waveguide including a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section. The semiconductor device has a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib and slab sections. The rib section may be either fully n-doped or p-doped in each cross-section along the semiconductor waveguide. Electrical connection to the p-doped and n-doped material may be enabled by forming contacts on the raised ridges, and electrical connection may be provided to the rib section from one of the contacts via periodically arranged sections of the semiconductor waveguide, where a cross-section of both the rib section and the slab section in the periodically arranged sections may be fully n-doped or fully p-doped.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 15, 2019
    Assignee: Luxtera, Inc.
    Inventors: Attila Mekis, Subal Sahni, Yannick De Koninck, Gianlorenzo Masini, Faezeh Gholami
  • Patent number: 10404032
    Abstract: An optical power monitoring device detects an optical power propagating through an optical fiber including at least a core and a cladding. The optical power monitoring device includes: a first optical fiber; a second optical fiber having a larger core diameter than the first optical fiber; a connection part where an end surface of the first optical fiber and an end surface of the second optical fiber are spliced; a first leakage part for leakage of a beam from the first optical fiber to the outside; a second leakage part for leakage of a beam from the second optical fiber to the outside; a first photodetector that detects an optical power leaking from the first leakage part; and a second photodetector that detects an optical power leaking from the second leakage part.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: September 3, 2019
    Assignee: FANUC CORPORATION
    Inventors: Hisatada Machida, Hiroshi Takigawa
  • Patent number: 10373939
    Abstract: A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: August 6, 2019
    Assignee: Skorpios Technologies, Inc.
    Inventors: Stephen B. Krasulick, John Dallesasse
  • Patent number: 10374393
    Abstract: Semiconductor Quantum Cascade Lasers (QCLs), in particular mid-IR lasers emitting at wavelengths of about 3-50 ?m, are often designed as deep etched buried heterostructure QCLs. The buried heterostructure configuration is favored since the high thermal conductivity of the burying layers, usually of InP, and the low losses guarantee devices high power and high performance. However, if such QCLs are designed for and operated at short wavelengths, a severe disadvantage shows up: the high electric field necessary for such operation drives the operating current partly inside the insulating burying layer. This reduces the current injected into the active region and produces thermal losses, thus degrading performance of the QCL. The invention solves this problem by providing, within the burying layers, effectively designed current blocking or quantum barriers of, e.g. AIAs, InAIAs, InGaAs, InGaAsP, or InGaSb, sandwiched between the usual InP or other burying layers, intrinsic or Fe-doped.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: August 6, 2019
    Assignee: Alpes Lasers SA
    Inventors: Alfredo Bismuto, Jérôme Faist, Emilio Gini, Borislav Hinkov
  • Patent number: 10361083
    Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 23, 2019
    Assignee: President and Fellows of Harvard College
    Inventors: Eric Mazur, Mengyan Shen
  • Patent number: 10333276
    Abstract: Embodiments are notably directed to a vertical microcavity. The vertical microcavity includes a first reflector and a second reflector, each of which includes one or more material layers extending perpendicular to a vertical axis x. The cavity may further include a confinement region extending between the first reflector and the second reflector, so as to be able to confine an electromagnetic wave. The confinement region may include a single layer material, which is structured so as to create an effective refractive index variation for the electromagnetic wave to be confined, in an average plane of the single layer material, perpendicularly to said vertical axis x. Additional examples are further directed to related microcavity systems and methods of fabrication.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kristian Samuel Cujia Pena, Thilo Hermann Stoeferle
  • Patent number: 10333278
    Abstract: A semiconductor laser includes a semiconductor layer sequence having an n-conducting n-region, a p-conducting p-region and an intermediate active zone, an electrically conductive p-contact layer that impresses current directly into the p-region and is made of a transparent conductive oxide, and an electrically conductive and metallic p-contact structure located directly on the p-contact layer, wherein the semiconductor layer sequence includes two facets forming resonator end faces for the laser radiation, in at least one current-protection region directly on at least one of the facets a current impression into the p-region is suppressed, the p-contact structure terminates flush with the associated facet so that the p-contact structure does not protrude beyond the associated facet and vice versa, and the p-contact layer is removed from at least one of the current-protection regions and in this current-protection region the p-contact structure is in direct contact with the p-region over the whole area.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 25, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Clemens Vierheilig, Andreas Löffler
  • Patent number: 10290996
    Abstract: A bottom-emitting vertical-cavity surface-emitting laser (VCSEL) structure includes a first substrate permitting the passage of light therethrough, an n-doped distributed Bragg reflector (nDBR), a p-doped distributed Bragg reflector (pDBR), one or more active layers, at least one of a high contrast grating mirror and a dielectric-enhanced metal mirror, and a plurality of layers, where the VCSEL structure is configured to be flip chipped to a second substrate. The pDBR and the nDBR define a laser cavity extending vertically therebetween and containing the one or more active layers. The at least one of a high contrast grating mirror and a dielectric-enhanced metal mirror may be disposed over the pDBR. The plurality of layers may be disposed over the at least one of the high contrast grating mirror and the dielectric-enhanced metal mirror to optically and hermetically seal the laser cavity.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 14, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sagi Varghese Mathai, Stanley Cheung, Wayne V. Sorin, Michael Renne Ty Tan
  • Patent number: 10290997
    Abstract: A method of producing an electronic component includes providing a surface comprising a first region and a second region adjoining the first region, arranging a sacrificial layer above the first region of the surface, arranging a passivation layer above the sacrificial layer and the second region of the surface, creating an opening in the passivation layer above the first region of the surface, wherein the opening in the passivation layer is created with an opening area that is smaller than the first region, and removing the sacrificial layer and the portions of the passivation layer that are arranged above the first region.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 14, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jens Mueller, Christoph Stephan, Robert Walter, Stefan Hartauer, Christian Rumbolz
  • Patent number: 10283935
    Abstract: A vertical cavity surface emitting laser device includes a substrate, a first-type doped distributed Bragg reflector (DBR) disposed on the substrate, a first electrode disposed on the substrate, an active layer disposed on the first-type doped DBR, a second-type DBR disposed on the active layer, and a second electrode disposed on the second-type DBR. The second-type DBR defines a first doping concentration region, and a second doping concentration region disposed between the first doping concentration region and the active layer and that has a doping concentration less than that of the first doping concentration region. The second-type doped DBR has a confinement member formed in the first doping concentration region, and defining an aperture.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 7, 2019
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Babu Dayal Padullaparthi, Feng Lin
  • Patent number: 10267988
    Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Jui Hsieh Lai, Tien-Yu Huang, Wen-Cheng Chen, Yushun Lin
  • Patent number: 10263137
    Abstract: A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1-z1As, the first window layer includes Alz2Ga1-z2As, and z1>z2.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 16, 2019
    Assignee: EPISTAR CORPORATION
    Inventor: Yi-Chieh Lin
  • Patent number: 10256372
    Abstract: A display device including a backplane, a plurality of light-emitting devices, a first distributed Bragg reflector layer and a second distributed Bragg reflector layer is provided. The light-emitting devices are disposed on the backplane. The first distributed Bragg reflector layer is disposed between the backplane and the light-emitting devices. The light-emitting devices are disposed between the first distributed Bragg reflector layer and the second distributed Bragg reflector layer. A projected area of the first distributed Bragg reflector layer on the backplane is larger than a projected area of one of the light-emitting devices on the backplane or a projected area of the second distributed Bragg reflector layer on the backplane is larger than a projected area of one light-emitting device on the backplane.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 9, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Yu-Hung Lai, Tzu-Yang Lin
  • Patent number: 10256368
    Abstract: Provided is a semiconductor substrate including a growth substrate, one or more compound semiconductor layers disposed on the growth substrate, and one or more control layers disposed between the compound semiconductor layers. Each control layer includes multiple nitride semiconductor layers including at least Al.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: April 9, 2019
    Assignee: SK Siltron Co., Ltd.
    Inventors: Jung-Hyun Eum, Kwang-Yong Choi, Jae-Ho Song, Dong-Kun Lee, Kye-Jin Lee, Young-Jae Choi
  • Patent number: 10250012
    Abstract: A vertical cavity surface emitting laser (VCSEL) array may include a plurality of VCSELs. A size of an emission area of a first VCSEL, of the plurality of VCSELs, may be different from a size of an emission area of a second VCSEL of the plurality of VCSELs. The first VCSEL may be located closer to a center of the VCSEL array than the second VCSEL. A difference between the size of the emission area of the first VCSEL and the size of the emission area of the second VCSEL may be associated with reducing a difference in operating temperature between the first VCSEL and the second VCSEL, or reducing a difference in optical power output between the first VCSEL and the second VCSEL.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 2, 2019
    Assignee: Lumentum Operations LLC
    Inventors: Ajit Vijay Barve, Eric R. Hegblom
  • Patent number: 10243330
    Abstract: Optical beam quality of an optoelectronic device is improved by suppression of high-order transverse optical modes by their resonant interaction with the continuum of modes in the surrounding regions, such continuum being realized by replacement of one or several layers by layers having a lower refractive index. In particular, selective oxidation of GaAlAs-based vertical cavity surface emitting laser results in (Ga)AlO layers surrounding the aperture and having a lower refractive index than the original (Ga)AlAs layers. The continuum of optical modes originates due to the modification of the optical field in the areas surrounding the aperture caused by the low index insertions positioned to result in enhancement of the optical field in their vicinity.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 26, 2019
    Assignee: VI SYSTEMS GMBH
    Inventors: Nikolay Ledentsov, Vitaly Shchukin
  • Patent number: 10230215
    Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 12, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Luke Graham, Andy MacInnes
  • Patent number: 10193023
    Abstract: A light-emitting diode chip including a p-type semiconductor layer, a light-emitting layer, an n-type semiconductor layer, and a first metal electrode is provided. The light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. The n-type semiconductor layer includes a first n-type semiconductor sub-layer, a second n-type semiconductor sub-layer, and an ohmic contact layer. The ohmic contact layer is disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer. The first metal electrode is disposed on the first n-type semiconductor sub-layer. A region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, so as to form ohmic contact between the first metal electrode and the ohmic contact layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 29, 2019
    Assignee: PlayNitride Inc.
    Inventors: Jyun-De Wu, Yu-Yun Lo
  • Patent number: 10193308
    Abstract: Embodiments may relate to a multiple quantum well (MQW) laser for operating at high temperatures, comprising at least one quantum well made of compressively strained InGaAlAs layers that are alternatively stacked with tensile strained InGaAlAs layers, the at least one quantum well surrounded on one side by a n-doped InP cladding and on the other by a p-doped InP cladding so as to form a double hetero-junction. A confinement layer of lattice-matched InAlAs may be provided between the quantum well and the p-doped cladding, having a first surface facing or adjacent to the quantum well and a second surface facing or adjacent to the p-doped cladding. An additional electron containment layer of tensile strained InAlAs may be provided facing or adjacent to one surface of the confinement layer, having a thickness smaller than that of the confinement layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventor: Pierre Doussiere
  • Patent number: 10186840
    Abstract: A semiconductor laser including current block layers disposed between a p-type clad layer and a p-type light guide layer and a current confinement region which is a region between the current block layers is configured as follows. A width of an opening portion of an insulating layer is made narrow above a wide portion of the current confinement region in which the wide portion, a tapered portion, a narrow portion, a tapered portion and the wide portion are disposed in this order between an incidence side (HR side) and an emission side (AR side), and both ends of the wide portion are covered by an insulating layer. According to such a configuration, it is possible to suppress generation of super luminescence in the wide portion, and it is thus possible to achieve improvement in beam quality and higher output of the beam.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuo Fukagai
  • Patent number: 10177533
    Abstract: An edge-emitting semiconductor laser and a method for operating a semiconductor laser are disclosed. In an embodiment, the edge-emitting semiconductor laser includes an active zone within a semiconductor layer sequence and a stress layer. The active zone is configured for being energized only in a longitudinal strip perpendicular to a growth direction of the semiconductor layer sequence. The semiconductor layer sequence has a constant thickness throughout in the region of the longitudinal strip so that the semiconductor laser is gain-guided. The stress layer may locally stress the semiconductor layer sequence in a direction perpendicular to the longitudinal strip and in a direction perpendicular to the growth direction. A refractive index of the semiconductor layer sequence, in regions which, seen in plan view, are located next to the longitudinal strip, for the laser radiation generated during operation is reduced by at least 2×10?4 and by at most 5×10?3.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 8, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Alexander Bachmann
  • Patent number: 10163024
    Abstract: Provided are: an acquisition section that acquires image data; a detection section that detects a marker portion indicated in the image data; a communication section that performs communication with either one or a plurality of external servers including at least one of a plurality of dictionary functions; a processing section that (i) specifies, from the dictionary functions, a dictionary function in accordance with a type of the marker portion, and (ii) causes the communication section to transmit, to the external server including the specified dictionary function, an instruction to search for a text indicated by the marker portion, and for information related to the text, by using the dictionary function; and a generation section that generates a glossary including the received information related to the text upon reception of the information related to the text as a search result from the external server by the communication section.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 25, 2018
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Sachiko Yoshimura, Yumi Nakagoshi, Akihiro Umenaga, Naoto Hanatani, Hironori Hayashi
  • Patent number: 10153614
    Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 11, 2018
    Assignee: APPLE INC.
    Inventors: Chin Han Lin, Weiping Li, Xiaofeng Fan
  • Patent number: 10153397
    Abstract: A semiconductor light-emitting device includes a first conductive semiconductor layer on a substrate, a superlattice layer including a plurality of first quantum barrier layers and a plurality of first quantum well layers, the plurality of first quantum barrier layers and the plurality of first quantum well layers being alternately stacked on the first conductive semiconductor layer, an active layer on the superlattice layer, and a second conductive semiconductor layer on the active layer, wherein a Si doping concentration of at least one of the plurality of first quantum well layers is equal to or greater than 1.0×1016/cm3 and less than or equal to 1.0×1018/cm3. Thus, the semiconductor light-emitting device may have increased light output and reliability.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-seok Choi, Min-ho Kim, Jeong-wook Lee, Jai-won Jean, Chul-min Kim, Jae-deok Jeong, Min-hwan Kim, Jang-mi Kim
  • Patent number: 10141720
    Abstract: A nitride semiconductor laser element includes an electron barrier layer between a p-side light guide layer and a p-type clad layer. The electron barrier layer has a bandgap energy larger than that of the p-type clad layer. The p-side light guide layer is made of AlxGa1?xN containing no Indium, where 0?x<1. A film thickness dn of the n-side light guide layer and a film thickness dp of the p-side light guide layer satisfy relationships dp?0.25 ?m and dn?dp.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: November 27, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Masao Kawaguchi, Osamu Imafuji, Shinichiro Nozaki, Hiroyuki Hagino
  • Patent number: 10134948
    Abstract: An improved light emitting heterostructure is provided. The heterostructure includes an active region having a set of barrier layers and a set of quantum wells, each of which is adjoined by a barrier layer. The quantum wells have a delta doped p-type sub-layer located therein, which results in a change of the band structure of the quantum well. The change can reduce the effects of polarization in the quantum wells, which can provide improved light emission from the active region.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 20, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska
  • Patent number: 10135226
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu