Abstract: Aspects of the disclosure include a method for video coding. The method includes receiving input data associated with a current block in a current image frame of video data, where the current block is coded by intra-prediction or to be coded by intra-prediction. The method also includes determining an intra-prediction mode of the current block, selecting one of a plurality of filters including at least a default filter and an N-tap filter, and generating filtered neighboring samples by filtering neighboring samples adjacent to the current block using the selected filter, where N is a positive integer different from 3. Moreover, the method includes encoding or decoding the current block by predicting the current block based on the filtered neighboring samples and the intra-prediction mode.

Abstract: Apparatus and methods may provide improved equalizer performance, e.g., for optical-fiber-based communication systems. A least-mean-square (LMS) equalizer may include a decision feedback path containing feedback carrier recovery (FBCR), which may have low latency, and which may thus enable high-speed tap updating in the equalizer. Feed-forward carrier recovery (FFCR) may be applied, in parallel with the FBCR, to provide equalizer output by compensating, e.g., for phase noise, with improved carrier recovery/compensation, versus using FBCR to generate the output.

Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Abstract: Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.

Abstract: A headset system for use with especially in a call center environment, in which method a wireless connection is established between headset and base unit, and the wireless connection is maintained while indicating from a headset user interface to the base unit that the headset is available for receiving an incoming call. The headset system is connected to a telephone system and has a processor configured to receive mode information and to operate according to the received mode information. The headset has a headset user interface and controls the headset signal processor to operate in accordance with user input. The headset is further configured to provide the end-of-call information to the base unit while maintaining the wireless connection.

Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.

Abstract: A device includes circuitry configured to determine feedforward and feedback coefficients for an adaptive frequency-domain decision feedback equalizer (AFD-DFE) based on previously received signals. The equalizer output is determined by applying the feedforward and feedback coefficients of the AFD-DFE to a received signal, and the feedforward and feedback coefficients of the AFD-DFE are updated based on the equalizer output.

Abstract: A remote device configured to control operation of a remote electronic device, such as a garage door opener, is provided. A transmitter circuit may be configured to receive and transmit communications directed to the remote electronic device. The communications may include data arranged according to a plurality of the control packet formats, and communications to the remote electronic device may include data transmitted according to the plurality of control packet formats.

Abstract: A device includes circuitry configured to determine feedforward and feedback coefficients for an adaptive frequency-domain decision feedback equalizer (AFD-DFE) based on previously received signals. The equalizer output is determined by applying the feedforward and feedback coefficients of the AFD-DFE to a received signal, and the feedforward and feedback coefficients of the AFD-DFE are updated based on the equalizer output.

Abstract: In a method for an optimized transmission of data in a wired multi-carrier (multi-carrier modulation—MCM) transmission system from a transmitter to one or more receivers via a transmission channel, only one specified supply power is provided for the transmitter, a transmitted signal for transmitting data has a plurality of subcarriers, and the data together with redundant information is distributed to the plurality of subcarriers in such a way that the receiver can dispense with some of the subcarriers in order to determine the data. The method includes a step of determining frequency-dependent access impedances of the wired transmission channel on the transmitter, and a step of adjusting the signal amplitude of the individual subcarriers on the basis of the measured frequency-dependent access impedances sand the limited supply power.

Abstract: A plurality of GNSS satellite signals feeds the signal processing engine operating in certain processing mode including carrier phase smoothed pseudorange positioning, precise point positioning (PPP), pseudorange differential (DGNSS), and carrier phase differential (RTK). The processing engine calculates two estimates of the ionosphere delay for each satellite: the filtered delay and the instant delay. Comparison of them allows to detect turbulent variation of the ionosphere and adjust parameters of two-parametric dynamic mode which improves positioning precision.

Abstract: A method for training a neural network to be configured to filter a multipath corrupted signal is provided. The method includes receiving, at the neural network, real or simulated multipath corrupted signal data, and training the neural network on the multipath corrupted signal data using a complex iterated least square thresholding algorithm (CILST) capable of processing both real and complex signals.

Abstract: Methods and systems for fast convergence. One embodiment includes the following steps: extracting a digital representation of a common mode signal of a received differential signal sent by a transceiver, and generating, by a fast-adaptive mode-conversion canceller (FA-MCC), a compensation signal to mitigate differential interference; feeding the received differential signal to at least one of the following: a digital equalizer, and a digital canceller (DEDC); wherein the FA-MCC and the DEDC feed a slicer; responsive to receiving an indication that a serious differential interference has occurred, indicating the transceiver to transmit known data; and utilizing the received known data for improving the accuracy of the slicer's errors, which enables rapid adaptation of the FA-MCC to a level that mitigates the serious differential interference and enables requesting retransmission of erred packets fast enough to maintain a fixed rate of data transmission over a 2-millisecond window.

Abstract: The invention relates to the field of channel coding and modulation technique, more specifically, to a single-carrier channel estimation method, comprising: equalizing a carrier of an input current-frame signal and of a channel of the current-frame signal, to obtain a sequence code of the current-frame signal, decision value of transmission sequence of the current-frame signal and estimated value of signal-to-noise ratio of the current-frame signal; calculating the current-frame signal, the sequence code and the estimated value of signal-to-noise ratio to obtain a initial channel estimation; calculating the current-frame signal, the decision value of transmission sequence and the estimated value of signal-to-noise ratio to obtain a reference channel; obtaining a filtered channel value after filtering the reference channel; and obtaining the estimated channel of the next-frame signal after implementing adaptive filtering on the estimated value of initial channel and filtered channel value, by reference to the

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: A method includes: generating a packet, where first L time domain sequence bits of a second symbol in the packet are the same as first L time domain sequence bits of an information bearing section in a time domain sequence of a first symbol in the packet, the first symbol includes a cyclic prefix CP and the information bearing section, the second symbol is a symbol following the first symbol, a length of the CP is 16 bits, and a length of the information bearing section is 64 bits, where 1?L?64; and sending the packet to a receive end, so that the receive end receives and parses the packet.

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Abstract: An apparatus, method, computer readable medium, and system are provided to determine whether a non-linear signal impairment is present in a network communication channel. For instance, a computing device may transmit equalization coefficients to a user device to modify future signals generated by the user device. If the equalization coefficients are unable to reduce a signal impairment, the signal impairment may be a non-linear signal impairment. The computing device may generate symbol placements based on signals received from the user device and transmit status messages.

Abstract: A method and apparatus for adapting, in parallel, two operating parameters associated with an equalizer circuit is disclosed. A control circuit may be configured to initialize a first operating parameter to an initial value, and modify a second operating parameter based upon the initial value of the first parameter. In response to determining a peak amplitude of an output signal of the equalizer circuit is less than a threshold value, the control circuit may be further configured to select a new value for the first operating parameter and adapt, in response to the change in the first operating parameter, the second operating parameter based on a performance metric of the equalizer circuit.

Abstract: A machining path creating device for wire electric discharge machines creates a machining path for machining a keyway in a side surface of a round hole. The machining path creating unit compares a “keyway depth” and a diameter of the round hole input by an operator. The machining path creating device determines that the input “keyway depth” is a cut depth when the input “keyway depth” is smaller than the diameter of the round hole and that a value obtained by subtracting the diameter of the round hole from the input “keyway depth” is the cut depth when the input “keyway depth” is larger than the diameter of the round hole.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.

Abstract: An alternative method of data communications using orthogonal time frequency shifting (OTFS) wireless waveforms configured so as to transmit data in a manner that is relatively insensitive to communications channel distortions and frequency shifts. In contrast to prior methods taught by applicant, the present disclosure teaches an alternative modulation scheme that maps data symbols intended for data transmission onto a symplectic-like 2D Fourier transform which operates on a form of the original data symbols. This 2D Fourier transform in turn is passed through a filter bank of narrow band filters, and the output in turn used to modulate transmitted waveforms according to various time slices until the entire 2D Fourier transform has been transmitted. At the receiver, and inverse of this process can be used to both characterize the data channel and correct the received signals for channel distortions, thus receiving a clear form of the original data symbols.

Abstract: An RFID receiver (1) comprises an antenna (11) configured to receive a radio signal (20) from an RFID transmitter (2) and to generate an electrical signal (110) from the radio signal (20) received from the RFID transmitter (2). A decoder circuit (10) is connected to the antenna (11) and configured to extract from the electrical signal (110) generated by the antenna (11) data bits encoded in the electrical signal (110). The decoder circuit (10) comprises an analog-to-digital converter (12) connected directly to the antenna (11) and configured to generate a digital input signal (13) from the electrical signal (110) generated by the antenna (11). A bit extractor (14) is connected to the analog-to-digital converter (12) and configured to extract the data bits from the digital input (13) signal generated by the analog-to-digital converter (12).

Abstract: A system and method for acoustic echo cancellation is provided. Embodiments may include receiving, at one or more microphones, an audio reference signal from an audio speaker. Embodiments may also include filtering the audio reference signal using one or more adaptive audio filters. Embodiments may further include analyzing a level of signal energy of the audio reference signal with regard to time, frequency and audio channel to identify at least one maximum error contribution point. Embodiments may also include updating the one or more adaptive audio filters based upon, at least in part, the analyzed audio reference signal.

Abstract: This disclosure describes circuit configurations that may be used for active noise cancellation in the digital domain. In particular, this disclosure proposes the use a down sample unit and an up sample unit, rather than memory-based delay circuits, to achieve one or more desired delays in digital adaptive noise cancellation circuits or other circuits that use delay for signal processing. The delay achieved by the down sample unit and the up sample unit may be tunable so as to allow flexibility in producing the necessary delay for different active noise cancellation circuit configurations. Many different adaptive noise cancellation circuit configurations are discussed, and the techniques may also be useful for other types of circuits, such as low-latency equalization circuits.

Abstract: A near field communication (NFC) reader is disclosed. The NFC reader includes a first section. The first section includes an NFC controller and a filter coupled to the NFC controller. The filter includes a filter capacitor. The first section further includes a first tuning circuit coupled to the filter. The first tuning circuit includes a tuner capacitor that is electrically coupled in parallel to the filter capacitor. The first tuning circuit is configured and adapted to be coupled to a coaxial cable. The NFC reader also includes a second section. The second section includes a second tuning circuit. The second tuning circuit includes a second tuner capacitor and a damping resistor. The second tuning circuit is configured and adopted to be coupled to the coaxial cable. The second section further includes an antenna coupled to the second tuning circuit.

Abstract: A self-calibrating antenna system having a radio frequency (RF) detector configured to estimate a time delay of a transmission signal on a transmission line, which couples an RF front end with an antenna tuner, based on a magnitude and phase of an input impedance of the transmission line at a first set of a plurality of respective frequencies, and a transceiver configured to transmit to the antenna tuner a calibrated tuning control command based on the estimated time delay to calibrate the antenna tuner and the transmission line.

Abstract: The present disclosure provides an apparatus and method for measuring echo responses of communication links used in in-vehicle networks with high resolution and high dynamic range, allowing for diagnostics of various failures and/or degradations with high precision. Additional information can be provided to indicate signaling quality, insertion loss, and return loss of the communication links used in in-vehicle networks. Together, these measures and information can provide a comprehensive diagnostic capability that improves network reliability and safety of in-vehicle networks.

Abstract: A digital pre-distortion system can inversely model a power amplifier of a system to linearize the transmitter. A complex baseband model for digital pre-distortion based on a narrowband signal assumption is unworkable for an ultra wide band Cable television application. Predistortion can use a true wide band model including real-valued basis terms, obtained from a real-valued signal. When raised to a power, both even and odd harmonics or both odd or even other non-linear terms are represented and negative frequency fold-over can be accounted for. A Hilbert transform can be applied. Compressed sensing can be used to reduce the number of basis terms in the true real wide band model to generate a sparse model. Sparse equalization can be added to improve the stability of the digital pre-distortion system.

Abstract: An apparatus and method are provided for controlling a delay circuit. Included is a delay circuit configured to receive a probe signal. Further provided is a controller in electrical communication with the delay circuit. The controller is configured to perform various operations, in response to the receipt of the probe signal by the delay circuit. A positive peak and a negative peak of an output of the delay circuit are measured. Further, a ratio involving the positive peak and the negative peak of the output of the delay circuit is calculated. A delay of the delay circuit is controlled, based on the ratio.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. Upon a good Signal-to-Noise Ratio (SNR) being achieved, a selected set of the tap weights of the equalizer filter are frozen or set to smaller values, while others continue to adapt and the timing recovery loop continues the clock recovery process. Thereby, the adaptation of equalization can be adjusted to attenuate the equalization filter's effect on clock delay correction by limiting the adaptation time or speed relative to those of the entire timing recovery loop.

Abstract: A technique is provided for estimating time of arrival of a signal transmitted as a pulse and received as a sum of pulses. The received signal is filtered with a novel filter that lowers the early side lobes of the received signal to noise level. A first energy rise point is identified at a point of the main lobe of the filtered received signal, at which the energy is higher than the noise by a predetermined level. Starting from the identification of the first energy rise points, the time of arrival is estimated via curve matching, in which the shape of the filtered received signal is matched to the shape of composed by a sum of one or more reference curves that are shifted both in time and in energy. The reference curves are found by applying to the transmitted signal the same filter applied to the received signal.

Abstract: One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.

Abstract: A system can be configured to control an equalizer circuit to equalize a data signal without requiring prior knowledge of the data signal's data rate. In an example, the system includes an equalizer circuit configured to equalize a data signal based on an equalizer control signal to produce an equalized signal, and a pattern detector configured to detect a specified data pattern in the equalized signal at each of multiple sampling rates. A control circuit can be configured to generate a preferred equalization control signal based on a sampling rate, selected from the multiple sampling rates, at which the pattern detector detects the specified data pattern in the equalized signal.

Abstract: A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.

Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.

Abstract: A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.

Abstract: A differential detector for a receiver and a method of detecting the value of symbols of a signal is disclosed. In particular, a detector comprising: an analog to digital converter for sampling samples from symbols of a signal; a differentiator configured to differentiate the samples with a transfer function to produce a differentiated series of samples for each symbol; and a decision device configured to determine the value of each symbol by comparing values of the differentiated series of samples with boundary condition values.

Abstract: A device includes circuitry configured to determine feedforward and feedback coefficients for an adaptive frequency-domain decision feedback equalizer (AFD-DFE) based on previously received signals. The equalizer output is determined by applying the feedforward and feedback coefficients of the AFD-DFE to a received signal, and the feedforward and feedback coefficients of the AFD-DFE are updated based on the equalizer output.

Abstract: The present document relates to the design of anti-aliasing and/or anti-imaging filters for resamplers using rational resampling factors. In particular, the present document relates to a method for implementing such anti-aliasing and/or anti-imaging filters with reduced computational complexity. In addition, the present document relates to further aspects of an audio encoding and decoding system, such as the phase relation between the channels of a multi-channel audio signal and/or the structure of the bitstream of an encoded audio signal.

Abstract: Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Abstract: This document describes techniques for decoding a convolutionally coded signal using a trellis decoder in a drift robust manner. A convolutionally coded and differentially modulated signal may be received. The signal may be decoded using a trellis. A noise prediction loop may be used to reduce noise characteristics of the signal. A frequency offset estimation loop may be used to reduce a frequency offset drift of the signal. The noise prediction loop and the frequency offset estimation loop may be applied at each branch of the trellis.

Abstract: A method of implementing troposcatter communications is provided. Transmittal of signals between receive and transmit antennas is performed in the time domain. After reception of a transmitted signal, the signal is converted to the frequency domain for signal processing. After signal processing, the signal is converted back into the time domain.

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

Abstract: A system and apparatus are disclosed for a method and apparatus for equalizing signals. An apparatus that incorporates teachings of the present disclosure may include, for example, an equalizer having a channel estimation calculator for calculating a time domain channel estimation from a baseband signal, a Fast Fourier Transform processor for translating the time domain channel estimation to a frequency domain channel estimation, a tap weight calculator for calculating a frequency domain tap weight according to the frequency domain channel estimation, an inverse Fast Fourier Transform processor for translating the frequency domain tap weight calculation to a time domain tap weight calculation, and a filter for equalizing the baseband signal according to the time domain tap weight calculation.

Abstract: Embodiments of the present disclosure provide an estimation apparatus and method for a nonlinear characteristic, which may simply and quickly estimate the nonlinear characteristic of a system to be measured by calculating parameters of the nonlinear model of the system to be measured according to the fundamental power and harmonic power of output signals of the system to be measured on at least two frequency spots obtained through measurement, with the accuracy of the result of estimation being relatively high.

Abstract: A serial transmitter that outputs one symbol every unit interval (UI) from a data source is presented. The serial transmitter includes a serial output port that outputs one symbol every unit interval (UI) from a data source. The serial transmitter also includes a plurality of driver segments that jointly drive the serial output port. Each driver segment is configured to use one of N phases of a sampling clock to serialize and transmit data from the data source. Different sets of the driver segments are configured to use different phases of the sampling clock for serializing and transmitting data, the sampling clock being a half-rate clock having a period of two UI.

Abstract: Receiver circuitry for receiving a data signal includes summation node circuitry that predicts an error value of the received data signal. The receiver circuitry also includes adaptation engine circuitry coupled to the summation node circuitry. The adaptation engine circuitry determines a transmitter adjustment based on the error value and sends a freeze signal to one or more components of the receiver to cause the receiver to continue operating without changing current settings of the one or more components. The receiver circuitry further includes a user interface and sequence controller, coupled to the adaptation engine circuitry, wherein the user interface and sequence controller sends a signal indicative of the transmitter adjustment to the transmitter.