Abstract: A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: A receiver includes a front-end amplifier, a sampler, and a decision-feedback equalizer. The front-end amplifier provides for amplifying a received input signal to yield an amplified input signal. The sampler provides for sampling the amplified input signal so as to yield a sampler output signal. The sampler output signal is a function of the amplified input signal and a reference signal coupled to a reference input of the sampler. The decision feedback equalizer provides for adjusting the reference signal as a function of feedback based at least in part on the sampler output signal.

Abstract: Provided are a data receiver circuit and a method of adaptively controlling an equalization coefficient using the same. The data receiver circuit includes n sampling receivers, n decision feedback equalizer (DFE) circuits, and a data recovery circuit. The n sampling receivers are configured to sample an input signal and output n respective sampling signals in response to n respective clock signals. The n DFE circuits are configured to equalize the n respective sampling signals in response to a DFE control signal and generate n respective pre-recovery signals in response to the n equalized sampling signals and n respective previous pre-recovery signals, the DFE control signal for changing an equalization ability of the n DFE circuits. The data recovery circuit is configured to select one of the n respective pre-recovery signals, and output the selected n pre-recovery signal as a recovered input signal.

Abstract: The current application is directed to joint decoding and equalization using a decision feedback equalizer. An example method to which the current application and certain of the current claims are directed uses joint trellis decoding and decision feedback equalization to efficiently estimate non-contiguous symbols using non-contiguous equalizer outputs. The estimation process uses all new possibilities of symbol values, rather than old decision feedback symbol estimates.

Abstract: A method for equalizing a received signal is provided. The signal is filtered and transmitted over a channel using an encoding scheme, where the encoding scheme has transmit symbols. This transmitted signal is then shaped such that the filtering and equalization adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative DFE with significantly reduced comparator levels.

Abstract: A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.

Abstract: Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

Abstract: A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.

Abstract: Time-interleaved analog-to-digital (AD) conversion circuit, which includes first and second AD converters that generate first and second digital signal sequences by converting an analog input signal into first and second digital signals with a first frequency at first and second timings mutually different with each other is disclosed. The AD conversion circuit further includes a FIFO that receives the first and second digital signal sequences, and a correction filter including first and second portions that are supplied with a common clock signal. The correction filter generates a first corrected digital signal sequence by adding the first synchronized digital signal sequence and the second synchronized digital signal sequence passed through the first portion of the correction filter, and a second corrected digital signal sequence by passing the second synchronized digital signal sequence through the second portion of the correction filter.

Abstract: An IQ mismatch correction circuit comprises: a correction circuit which performs a correction process to I-phase and Q-phase input signals by using one pair of first- or higher-order digital filters; two or more control circuits which independently generate two or more control variables to derive two or more coefficients of transfer functions of the digital filters; and one or more pairs of analyzing filters which change frequency characteristics of the corrected I-phase and Q-phase output signals so that the frequency characteristics is different from those of the original signals. The first control circuit measures a temporally averaged IQ phase mismatch state between the I-phase and Q-phase output signals. The second control circuit measures a temporally averaged IQ phase mismatch state between output signals on I-phase and Q-phase sides of one pair of analyzing filters. These states are fed back to the digital filters as first and second control variables, respectively.

Abstract: A receiver is optimized by adapting the taps of a decision feedback equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update a tap of the decision feedback equalizer. The updating of the tap continues until the number of margin hits has been minimized.

Abstract: Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

Abstract: In an RF signal transmission network such as the reverse channels of a coaxial cable network, there is provided at least one adaptive equalizer for pre- or post-filtering inter-symbol interference in the transmitted signals, the adaptive equalizer having a series of coefficients for which values are required. In order to improve the transmission efficiency the preamble used in these channels is shortened by coarsely estimating the channel using a short “unique word’ placed at the beginning of the equalizer training sequence. The coarse channel estimate is crudely inverted to produce a set of equalizer coefficients which partially equalize the channel. By initializing the adaptive equalizer with these approximate coefficients, it is possible to reduce the length of the training sequence needed for the equalizer to converge.

Abstract: In a receive node of a wireless network, an iterative multi-user multi-stage interference cancellation receiver is used. After each stage of interference cancellation, interference characteristics change. An adaptive strategy is used in which after each stage of interference cancellation, impairment covariance is parametrically updated and combining weights of the receiver are adapted to reflect the updated impairment covariance.

Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.

Abstract: A method and device for compensating for undesirable signal characteristics such as baseline wander that includes a linear equalization filter responsive to receive an input, a combiner responsive to an output of the linear equalization filter, and a decision feedback equalization filter responsive to an output of the combiner, where the combiner is further responsive to an output of the decision feedback equalizer. Additionally, an error feedback circuit is responsive to the output of the combiner, and the combiner is further responsive to an output of the error feedback circuit to form a compensated signal having reduced distortion relative to the distorted signal.

Abstract: Embodiments of the present disclosure provide a method for tuning an analog equalizer and a digital equalizer associated with a communications channel. A plurality of signals is injected into a model of a communication channel, the model being configured to have an analog equalizer at a receiving end, tuning a setting of the analog equalizer to obtain a first ratio of a pulse peak to a rise time in a precursor portion of the injected plurality signals that are received from the channel, injecting another plurality of signals into the model of the communication channel, the model being reconfigured to have the tuned analog equalizer and a digital equalizer downstream of the tuned analog equalizer, and tuning a setting of the digital equalizer based on a post-cursor tail characteristic of the another plurality of signals. Other embodiments are also described and claimed.

Abstract: A receiver is optimized by adapting parameters of components within the receiver. Various component parameters are adapted by using either a least means squared algorithm or a steepest descent algorithm. The taps of a decision feedback equalizer can be adapted by using either a least means squared algorithm or a steepest descent algorithm. The gain value of a linear equalizer and the input of a digital to analog converter coupled to the linear equalizer are also adapted through the least means squared algorithm or a steepest descent algorithm. A variable gain amplifier is also capable of being adapted through the use of the least means squared algorithm. Clock offsets are also configured by use of a steepest descent algorithm.

Abstract: In particular embodiments, a method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.

Abstract: In one embodiment, a receiver circuit is provided. The receiver circuit includes a low-power equalization circuit having a first linear equalization circuit coupled to receive serial data. The receiver circuit includes a low-noise equalization circuit having a second linear equalization circuit coupled to receive the serial data, and a non-linear equalization circuit coupled to an output of the second linear equalization circuit. The receiver circuit includes a control circuit configured to enable the low-power equalization circuit and disable the low-noise equalization circuit in response to a first state of a control signal. The control circuit is configured to disable the low-power equalization circuit and enable the low-noise equalization circuit in response to a second state of the control signal.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: Wireless communication receiver with hybrid equalizer and RAKE receiver. The receiver compares performance of the system for RAKE only and RAKE in combination with equalizer estimates. The receiver enables or disables the equalizer accordingly.

Abstract: A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.

Abstract: Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.

Abstract: A communication device is provided for receiving a packet including a preamble part having a continuous waveform, a sync part having a specific pattern and a data part, which has been modulated by changing electrical load. The communication device includes: a preamble detection unit for detecting the preamble part from a received signal to extract sampling timing based on the continuous waveform; a sync detection unit for detecting the sync part from the received signal based on the sampling timing to output a timing signal indicating a start position of the sync part; a delay buffer for giving a delay to the received signal so that the head of the sync part is not outputted until the detection of the sync part is determined; an adaptive equalization unit for performing adaptive equalization using the sync part based on the timing signal by inputting the delayed received signal; and a decoding unit for performing decoding processing of an equalized output signal from the adaptive equalization unit.

Abstract: System and method for equalizing an orthogonal frequency division multiplexed signal having been encoded by spreading subcarriers in the frequency domain using orthogonal codes includes receiving the signal at a receiver (300), demodulating the signal to produce demodulated information, producing a spread frequency domain representation of the demodulated information, determining an equalized representation by adjusting the power and phase of the spread frequency domain representation at least one frequency based on adjustment values, de-spreading the equalized spread frequency domain representation using the orthogonal codes to produce a de-spread frequency domain representation including received subcarriers, determining a subcarrier value for each of the received subcarriers, orthogonally spreading the determined subcarrier values using the orthogonal codes to produce a model spread frequency representation, calculating expected error values based upon the model spread frequency representation and the equa

Abstract: An FFE/DFE equalizer is provided that uses unclocked FIR filters. At least one of the unclocked FIR filters has tunable delay cells that can be tuned to adjust their respective time delay time periods. Because the FIR filters of the FFE/DFE equalizer are unclocked, the complexity and die area associated with clocking circuits are avoided, thereby enabling costs to be reduced. Because the delay cells of at least one of the FIR filters are tunable to enable their respective time delay periods to be adjusted, very good equalizer performance is achieved without having to use clocked circuits. In addition, because clocked circuits are not used in the FIR filters, the need for clocking circuits to control the timing of clocked circuits is obviated, which leads to a reduction in the amount of power consumed by the FFE/DFE equalizer.

Abstract: Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.

Abstract: A symbol sequence contained in a received signal comprising a cyclic convolution of a Walsh code multiplexed signal and a channel impulse response of a multipath channel is detected using Walsh Hadamard domain equalization techniques. The method comprises converting the received signal and the channel impulse response of the multipath channel from the time domain to the WHT domain, and determining the symbol sequence based on equalizing the received signal in the WHT domain using WHT spectra of the channel impulse response to remove inter-symbol interference from the received signal due to cross-correlation between Walsh codes.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained IT resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with IT resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences.

Abstract: A communication signal receiver includes an adder, a slicer, and an infinite impulse response (IIR) filter. The adder performs an addition on a first signal and a filtered signal to generate an output signal. The slicer performs a hard decision on the output signal to generate a detecting result. The IIR filter is coupled to the slicer and the adder for processing the output signal to generate the filtered signal. The communication signal receiver further includes a decoder. The decoder receives and decodes the output signal to generate a decoded output signal, wherein the decoder is a Viterbi decoder.

Abstract: A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: The present invention is directed to joint decision feedback equalizer (DFE) and Trellis decoder adaptable to an Ethernet transceiver. A Trellis coded modulation (TCM) decoder includes a one-dimensional branch metric unit (1D-BMU) configured to calculate 1D branch metrics; a four-dimensional branch metric unit (4D-BMU) configured to combine the 1D branch metrics to generate 4D branch metrics; an add-compare-select unit (ACSU) configured to perform add, compare and select (ACS) operations on the 4D branch metrics for each state to obtain path metrics; and a survivor memory unit (SMU) configured to store and keep track of symbols. A decision feedback unit (DFU) is coupled to receive the symbols from the SMU in order to estimate inter-symbol interference (ISI) quantity, which is then fed back to the 1D-BMU.

Abstract: One or more embodiments to iteratively detect and decode data transmitted in a wireless communication system, featuring a MIMO detector and a soft input soft-output error-correction-code decoder. More specifically, a method suitable for iterative detection and decoding schemes is proposed, which is able to output near optimal bit soft information processing efficiently given input bit soft information. First, a transmitting source is selected as a reference layer, wherein the associated symbol represents a reference transmit symbol. Subsequently, a set of candidate values are identified for the reference transmit symbol. For each candidate value a candidate transmit sequence is estimated through a novel spatial decision feedback equalization process based on both Euclidean distance metrics and the a-priori soft information provided by the SISO ECC decoder. The novel DFE technique uses a novel bit metric.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.

Abstract: An embodiment of the invention pertains to demodulating a data communication into a sequence of symbols. In this embodiment, a first filter generates a first convolution between a first plurality of coefficients and the data communication. The data communication is a distortion of a first sequence of symbols selected from a plurality of symbols in a constellation. A first error circuit maps the first convolution to a second sequence of symbols. An adaption circuit adjusts the first coefficients until a convergence at a last one of the symbols in the second sequence. A second filter generates a second convolution between a second plurality of coefficients and the data communication. The second coefficients are initialized to the first coefficients from the adaption circuit. A second error circuit maps the second convolution to a third sequence of symbols.

Abstract: A method used in the receiver of a communication system is provided to suppress narrow band interferences, known as ingress, that are present in the communication channel, which is shared by a plurality of transmitters each having a channel pre-equalizer, by means of a Time Division Multiple Access (TDMA) scheme or Synchronous Code Division Multiple Access (SCDMA) scheme. The method comprises filtering the interferences using Infinite Impulse Response (IIR) notch filters, and providing IIR all-pass filters devised to compensate for substantially all phase distortions introduced by the notch filters. The method also includes an algorithm to detect the narrow band interferences and an adaptive equalizer to equalize the channel by computing the coefficients of the transmitters' pre-equalizers, and arranged such that the equalization of the channel is isolated from the suppression of the interferences.

Abstract: Methods and systems for processing signals in a receiver are disclosed herein and may include updating a plurality of filter taps utilizing at least one channel response vector and at least one correlation vector, for a plurality of received clusters, based on initialized values related to the at least one channel response vector and the at least one correlation vector. At least a portion of the received signal clusters may be filtered utilizing at least a portion of the updated plurality of filter taps. The update may be repeated whenever a specified signal-to-noise ratio (SNR) for the received signal clusters is reached. The initialized values may be updated during a plurality of iterations, and the update may be repeated whenever a specified number of the plurality of iterations is reached.

Abstract: A method of equalizing a signal received over transmission channel defined by BEM coefficients of a basis expansion model of its channel taps, comprising the step of approximately solving the relation (I) for x[n] by an iterative method, n being the index of time, y[n] being the received signal, x[n] being the equalized signal, Bm[n] being the mth basis function of the basis expansion model, M being the model order of the basis expansion model, and blm, being the BEM coefficient of the mth of the basis function of the /th channel tap, and w[n] being optional noise.

Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.

Abstract: A receiver for receiving a data signal having a channel profile may include an equalizer, to which the data signal is feedable, the equalizer having a plurality of filters and a switching device coupled to the filters, a selection device, which is disposed such that it determines a first number and a second number in dependence on the channel profile, and the switching device is disposed such that it connects a number of linear filters corresponding to the first number to form a first overall filter and connects a number of linear filters corresponding to the second number to form a second overall filter.

Abstract: An improved Tomlinson Harashima Precoding (THP) communication system through special configuration of its feedback coefficients is disclosed. Improvement, in terms of THP system robustness against analog-to-digital (ADC) sampling phase variation, is achieved either by deriving feedback coefficients of the Decision Feedback Equalizer at worst ADC sampling phase or by inserting a Zero Edge Filter (ZEF) at the receiver. The ZEF modifies the communication system such that the feedback filter coefficients derived in the Decision Feedback Equalizer (DFE) mode and later used in the THP mode is capable to compensate the zero at Nyquist Frequency due to a non-optimum sampling, phase of the ADC. The THP communication system, modified and improved with the insertion of ZEF, is operable to switch from an adaptive Decision Feedback Equalizer (DFE) mode to a THP mode having an adaptive Linear Equalizer (LE) at the receiver.

Abstract: Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.