Abstract: A BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected in series for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR system as a function of an addition of at least first and second signals and a subtraction of at least a third signal. The third signal includes a first delayed output sample generated by the second delay line multiplied by a first prescribed value. The first delayed output sample and the output data sample are temporally nonadjacent to one another.

Abstract: In Software defined elastic optical networks, modulation format and constellation size may be flexibly modified. As a result, digital signal processing (DSP) algorithm should be compatible with different modulation schemes or readily reconfigurable at the optical coherent receiver. Therefore we propose a novel cascaded adaptive blind equalizers based on decision-directed modified least mean square (DD-MLMS) algorithm for polarization separation and carrier phase recovery. The algorithm is square quadrature amplitude modulation (QAM) independent so that it could be applied in the elastic optical systems. The 28 Gbaud polarization multiplexing quadrature phase shift keying (PM-QPSK) and PM-16QAM back-to-back transmission is demonstrated. The results show that the performance is very close to the general algorithm but with a benefit of the reduced operation complexity.

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract: A receiving circuit includes: a sampling circuit to sample input data in synchronization with first clock to obtain boundary data, and sample the input data in synchronization with second clock to obtain center data; a decision feedback equalizer to perform equalization on the center data using an equalization coefficient, and output first output data; a first comparator circuit to perform binary decision on the boundary data and output second output data; a phase detection circuit to detect phase information of the input data using the first output data and the second output data; a phase difference computation circuit to calculate phase difference of the first output data using the equalization coefficient; a first phase adjustment circuit to adjust phase of the first clock using the phase information; and a second phase adjustment circuit to adjust phase of the second clock using the phase information and the phase difference.

Abstract: Systems and methods for decoding block and concatenated codes are provided, including channel state information estimation such as by using optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics, including HD Radio receivers and systems.

Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences.

Abstract: Briefly, in accordance with one or more embodiments, in response to receiving a single carrier signal that is not phase locked, channel equalization may be applied to the signal via a channel equalizer. The equalized signal may be phase averaged to provide a signal that is at least partially phase stabilized. The channel equalizer may then be trained by feeding back the at least partially phase stabilized phase reference to the channel equalizer. The resulting signal may then be decoded via coherent or quasi-coherent detection.

Abstract: An adaptive equalizer and an adaptive equalizing method are provided. The adaptive equalizer includes an adaptive equalizing unit, for adaptively equalizing an inputted signal to output the equalized signal; a coefficient updating unit, for updating a coefficient of a filter of the adaptive equalizing unit; a switching unit, connected between the coefficient updating unit and the adaptive equalizing unit and a monitoring device, for controlling on or off of the switching unit in accordance with the fact that a down sampling phase of the inputted signal or a down sampling phase of the equalized signal is within a predetermined range. When the switching unit is on, the coefficient updating unit is capable of updating the coefficient of the adaptive equalizing unit, and when the switching unit is off, the coefficient updating unit is incapable of updating the coefficient of the adaptive equalizing unit.

Abstract: A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal.

Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

Abstract: A system for controlling start-up of a feedback controller includes a memory device and a processing circuit. The processing circuit is configured to receive a gain parameter from the feedback controller and to store the gain parameter in the memory device. The processing circuit is further configured to multiply the stored gain parameter and to cause the feedback controller to use the multiplied gain parameter in response to a determination that the feedback controller has restarted.

Abstract: An adaptive equalizer (100) has a signal converter (200) for performing a fast Fourier transform and/or an inverse fast Fourier transform. The signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.

Abstract: Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit time, a first delay circuit to delay an output signal of the first discrimination circuit and that includes N-number (N>=2) of stages of unit delay circuits connected in cascade and operating in unit time, a second delay circuit to receives an output signal of the second discrimination circuit and that includes not less than an (N+1)-number of stages of unit delay circuits connected in cascade and operating in unit time, and a control unit that receives an output of the first delay circuit, and a second output signal output from the second delay circuit.

Abstract: A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Abstract: The present invention discloses a signal transmission device performing compensation by filtering characteristics for generating a transmission signal according to a pulse amplitude modulation signal. The signal transmission device comprises: a filtering characteristic compensation circuit for generating a compensation signal according to the pulse amplitude modulation signal and a filtering function; a filter coupled to the filtering characteristic compensation circuit for generating a filtered signal through filtering the compensation signal according to the aforementioned filtering function; and an analog front-end circuit for generating the transmission signal according to the filtered signal.

Abstract: Systems and methods for decoding block and concatenated codes are provided, including channel state information estimation such as by using optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics, including HD Radio receivers and systems.

Abstract: One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed.

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.

Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.

Abstract: A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an input coupled to the first input of the subtractor. The weighting circuit, responsive to a weighting coefficient, is coupled between an output of the function circuit and the second input of the first subtractor. The function generator has a transfer function with a third-power term and the weighting coefficient is set to a value based on the level of the signal peaks that will least partially reduce distortion in signals on the output of the subtractor.

Abstract: A method of receiving data including receiving, on one or more carrier waveforms, signals representing a plurality of data elements of an original data frame wherein each of the data elements are represented by cyclically time shifted and cyclically frequency shifted versions of a known set of waveforms. The method further includes generating, based upon the signals, a received data frame and generating an equalized data frame by performing an equalization operation using elements of the received data frame, the equalization operation correcting for distortion introduced into the signals during propagation of the carrier waveforms through a channel.

Abstract: A method of equalizing a signal received over transmission channel defined by BEM coefficients of a basis expansion model of its channel taps, comprising the step of approximately solving the relation (I) for x[n] by an iterative method, n being the index of time, y[n] being the received signal, x[n] being the equalized signal, Bm[n] being the mth basis function of the basis expansion model, M being the model order of the basis expansion model, and blm being the BEM coefficient of the mth of the basis function of the lth channel tap, and w[n] being optional noise.

Abstract: An equalization device (500) includes a sample hold unit (501) that samples and holds an input signal, a multiplication unit (503) that multiplies the output signal of the sample hold unit (501) by a coefficient, a sample hold unit (502) that samples and holds the input signal at a timing delayed from the sample hold timing of the sample hold unit (501) by one symbol length, a multiplication unit (504) that multiplies the output signal of the sample hold unit (502) by a coefficient, and an addition unit (505) that adds the output signal of the multiplication unit (503) and the output signal of the multiplication unit (504) to output a sum signal.

Abstract: A transceiver including an equalizer configured to receive an input signal. A control circuit selects a predetermined coefficient, maintains the predetermined coefficient at a fixed value, and based on the predetermined coefficient, selects first coefficients and second coefficients. The control circuit that, while maintaining the predetermined coefficient at the fixed value and while the equalizer is receiving the input signal, adjusts a coefficient of one of the first or second coefficients. The equalizer includes: first taps configured to, based on the first coefficients, filter the input signal to generate a first filtered signal; a unity tap configured to, based on the predetermined coefficient, filter the first filtered signal to generate a second filtered signal; and second taps configured to, based on the second coefficients, filter the second filtered signal to generate a third filtered signal. An output transmits the third filtered signal.

Abstract: A method, apparatus and computer program product are configured to provide calibration accuracy in an analog filter. In this regard, a method is provided that includes estimating a cutoff frequency for an analog filter. The method further includes causing a filter tuning word to be modified based on the estimated cutoff frequency for the analog filter. The method also includes determining a residual cutoff frequency mismatch for the analog filter. The method also includes causing an equalizer configuration to be selected for a digital filter based on the determined residual cutoff frequency mismatch.

Abstract: Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

Abstract: A communication receiver including a time domain receive filter to provide a filtered output, the filtered output including colored noise. The receiver also includes a frequency domain, fractionally-spaced equalizer (FSE) unit to receive the filtered output from the receive filter. The FSE unit determines a separate weighting factor for each subcarrier, and the weighting factor is determined based on a noise variance of the subcarrier.

Abstract: A decision feedback equalizer is provided for correcting ISI on a first postcursor without using received decision data of a preceding bit. The decision feedback equalizer includes an amplifying circuit that is to be supplied with received data, a duobinary signal decision device for determining an output signal from the amplifying circuit, the duobinary signal decision device including a flip-flop, a shift register for successively shifting a decision result held by the flip-flop, and a plurality of current control blocks that are to be supplied with respective output signals from the shift register, and feeding back output signals to an output terminal of the amplifier to control the potential thereof.

Abstract: Systems, methods, and other embodiments associated with adaptively determining settings of a transmit equalizer are described. According to one embodiment, a signal is received from a transmitter and a signal contribution of the transmit equalizer is removed from the signal to produce a residual signal. Revised tap coefficients are computed based, at least in part, on the residual signal. Revised tap coefficient settings, that are based, at least in part, on the revised tap coefficients, are provided to the transmit equalizer.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: A decision feedback equalizer (DFE) includes a sampler for receiving a first input signal and comparing an amplitude of the first input signal with a first predetermined voltage level and a second predetermined voltage level. The DFE includes a DFE logic circuit for receiving at least one first sign signal based on comparison results, and for selectively updating a tap coefficient based on the at least one first sign signal. The DFE logic circuit is configured to update the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is not between the first predetermined voltage level and the second predetermined voltage level. The DFE logic circuit is configured to maintain the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is between the first and the second predetermined voltage levels.

Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.

Abstract: A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

Abstract: Disclosed are a receiving equalization device and a method thereof, the receiving equalization device including a subtracter to output a first output signal, an eye monitor block to obtain a sampling timing by using the output first signal, and a slicer to generate a sampling signal by sampling the first output signal based on the sampling timing, and to return the generated sampling signal to the subtracter via a feedback filter or an algorithm determining block.

Abstract: A transmitter includes an equalizer for conditioning a data signal in response to a first and a second equalizer setting. The first and second equalizer settings are both associated with a selected point on a two-dimensional search grid. The search grid includes a first equalizer setting and a second equalizer setting for each point on the search grid. The transmitter transmits a data signal across a first channel medium using settings associated with a selected point on the search grid. A receiver analyzes the received signal from the transmitter to determine a signal quality metric. The search grid is used to select settings from neighboring points to produce signals that are evaluated to produce signal quality metrics. The results of the evaluations are used to efficiently search the search grid for optimum equalizer settings for the transmitter.

Abstract: A transmitter inserts parity samples into a stream of information symbols in an inter-symbol correlated (ISC) signal. The inserted parity samples may be utilized to generate estimates of corresponding information symbols when they are received by a receiver. The information symbols may be pulse shaped by a first pulse shaping filter characterized by a first response. The parity samples may be pulsed shaped by a second pulse shaping filter characterized by a second response. The first response and the second response are diverse or uncorrelated. The transmitter may transmit the ISC signal comprising the pulse shaped information symbols and the pulse shaped parity samples. The parity samples may be generated utilizing a non-linear function over a plurality of the information symbols. The non-linear function may be diverse from a partial response signal convolution corresponding to the information symbols and is designed according to a desired SNR value at the receiver.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract: Described embodiments provide a method of adjusting configurable parameters of at least one linear equalizer in a communication system. A transmitting device applies an input signal to a receiver. The at least one linear equalizer equalizes the input signal. A sampler generates one or more sampled values of the input signal. A data detector digitizes the sampled values of the input signal. At least one error detection module generates an error signal based on one or more of a plurality of sampled values of the input signal and a target value. An adaptation module determines a gradient signal based on a comparison of one or more of the plurality of sampled values of the input signal and one or more of the plurality of values of the error signal. The adaptation module adjusts a transfer function of the at least one linear equalizer based on the determined gradient signal.

Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: The present invention is directed to a decision feedback equalizer that implements a multipath delay calculator to determine the delay between a line-of-sight component of a received data signal and a reflection of the line-of-sight component. The determined delay is used to control when decisions are used within the decision feedback equalizer so that the appropriate decisions are delayed until the reflection is received. In this way, the reflection can be substantially removed from the data signal using decisions that were generated when the line-of-sight component was received. Because the correction window is limited to the time when the reflection is received, the number of taps required to perform equalization is greatly reduced resulting in a decision feedback equalizer with less circuitry or logic.

Abstract: Narrowband ingress estimation and characterization using equalizer taps. A equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) is implemented to process an input signal thereby generating an output signal. Analysis of the frequency response of the equalizer including the FFE and the DFE of the equalizer allows for the determination of whether or not narrowband ingress exists within the signal received by the equalizer. For example, analysis of the signal output from the equalizer provides for determination of the overall frequency response of the equalizer. In addition, analysis of the respective equalizer coefficients within one or both of the FFE and the DFE of the equalizer may be used to determine the overall frequency response of the equalizer. Narrowband ingress may be identified when the combination of the FFE (having a notch therein) and the DFE provides for an overall flat frequency response.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.

Abstract: An adaptive equalizer includes an equalization circuit and an operation number change unit. The equalization circuit includes a plurality of cascade-coupled delay taps. The equalization circuit equalizes an input signal by adding calculation results of the plurality of delay taps. The operation number change unit changes a number of operations of the plurality of delay taps according to an equalization error of the equalization circuit.

Abstract: A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node.

Abstract: A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.

Abstract: A method is provided for specifying a transmission mode for each signal portion of a multi-carrier signal transmitted between a first and second device. The method includes defining an adaptive modulation and coding set divided into a plurality of subsets, each of the plurality of subsets including a plurality of transmission modes for transmitting a signal portion. The method further includes selecting a transmission mode subset from the plurality of subsets for transmission of the multi-carrier signal from a first to a second device, selecting a signal portion transmission mode for each signal portion from the plurality of transmission modes of the selected transmission mode subset, defining semantic bits that indicate the selected transmission mode subset, defining an indicator bit for each signal portion indicating the selected sub-carrier transmission mode, and transmitting the semantic bits and the indicator bit for each signal portion from a first to a second device.