Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.

Abstract: Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.

Abstract: A method, apparatus, and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix.

Abstract: A method of realizing smart antenna based on software radio and system therefore in IMT-2000 CDMA system. Channel conditions are classified according to the features of wireless communication channel conditions, covariance matrix of array receiving signals is step-by-step dimension-reduced and decorrelated using special smoothing differential processing method, obtaining the structure related to the receiving signals by gradually converting correlated signal into independent signal sources and realizing conditions recognition, and respectively calculating receiving weights and transmitting weights using corresponding receiving adaptive beam forming algorithm and transmitting adaptive beam forming algorithm selected according to the result of channel condition classifying.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period.

Abstract: The device is used for decoding convolution-encoded reception symbols. In this context, transmission data are modulated with a modulation scheme to form symbols, which are encoded with a transmission filter to form convolution-encoded transmission symbols. A convolution-encoded transmission symbol contains components of several symbols arranged in time succession. These transmission symbols are transmitted via a transmission channel and received as reception symbols. The Viterbi decoder decodes the reception symbols by use of a modified Viterbi algorithm. Before running through the Viterbi decoder, the reception symbols are processed by a state-reduction device, which determines additional items of information relating to possible consequential states of the decoding independently of the decoding through the Viterbi decoder in every state of the decoding. The state-reduction device uses the additional items of information to restrict the decoding through the Viterbi decoder to given consequential states.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: In one embodiment, a method includes accessing an input signal from a receiver that includes a series of bits and further comprising residual boundary intersymbol interference (ISI). The method includes identifying a first bit sequence in the input signal and identifying a second bit sequence in the input signal that differs from the first bit sequence with respect to one or more data values of one or more bits in the first and second bit sequences corresponding to particular residual boundary ISI for measurement. The method includes determining a difference between first boundary error in the first bit sequence and second boundary error in the second bit sequence and measuring the particular residual boundary ISI by the difference for use in adaptive equalizer control.

Abstract: Provided is a transmission circuit that includes first and second drive circuits. A first digital signal at a data rate of a predetermined period length is input to the first drive circuit. A second digital signal at the data rate of the predetermined period length shifted by ½ of the predetermined period length relative to the first digital signal is input to second drive circuit. The outputs of the first drive circuit and the second drive circuit are connected. The connected output indicates the maximum level or the minimum level when the value of the first digital signal and the value of the second digital signal are the same. The connected output indicates a level between the maximum level and the minimum level when the value of the first digital signal and the value of the second digital signal are different.

Abstract: A digital communications receiver includes an input configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of a plurality of data bits. A processor adjusts a magnitude and filters the received signal. An equalizer applies a cyclic prefix restoration to the adjusted and filtered signal, producing a second signal, converts the second signal from time domain to frequency domain to produce a frequency domain signal, and determines a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.

Abstract: Methods and apparatus are provided for performing equalization of communication channels. In an embodiment of the invention, at least one tap can be selected from a set of feedforward taps of feedforward filter circuitry, where each tap of the selected at least one tap has a magnitude that is greater than or substantially equal to a magnitude of any tap of the set of feedforward taps that is not in the selected at least one tap. In addition, at least one tap can be added to a set of taps of feedback filter circuitry in communication with the feedforward filter circuitry. The invention advantageously allows for more efficient and reliable equalization of communication channels.

Abstract: A method of processing a digital broadcasting signal includes generating a transport stream including a plurality of transport packets; selecting one of the transport packets as a starting packet to be mapped into a first data segment of an encoded data frame; and constructing deterministic data frames in the transport stream beginning with the starting packet; wherein at least one of the 52 transport packets does not have an adaptation field; wherein all remaining ones of the 52 transport packets do have an adaptation field; and wherein the at least one transport packet that does not have an adaptation field is provided at a fixed location in each of the slices.

Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Abstract: An equalizer that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. When the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.

Abstract: To realize a GDFE precoder for multi-user MIMO systems, which significantly reduces the computational cost while resulting in no capacity loss, one method comprises computing an effective UL channel matrix HUL using one of two methods HUL=HDLH, or HUL=[(Pt/Nt)HDLHHDL+I]?1/2HDLH; extracting Hk from HUL; computing a singular value decomposition of the DL channel between the BS and kth UT, Hk, for all K UTs, Hk=UkSkVkH; extracting all singular values as s=[diag(S1), . . . , diag(SK)]; extracting a vector ? from s by choosing first utmost Nt largest non-zero singular values of s; sorting elements in ? in decreasing order; performing water-filling to allocate power and obtain a diagonal matrix ?k representing power allocations corresponding to the singular values of the kth UT; computing an UL covariance matrix for each UT as ?k=Uk?kUkH; and obtaining an overall input covariance matrix D for the equivalent UL channel.

Abstract: Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.

Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A method of reducing error in transmissions received in a receiver is provided. A transmission containing a synchronization signal is inputted through a first filter to a synchronization correlator, to generate a timing error of the synchronization signal. An amount of delay of the synchronization signal sufficient to reduce the timing error is determined. The transmission is delayed by the amount of delay by being passed through at least a second, variable filter whose delay is determined using a stochastic gradient algorithm. The synchronization correlator may also generate a deviation error of the synchronization signal and determine an amount of deviation correction sufficient to reduce the deviation error as well as generating a frequency error of the synchronization signal and determining an amount of frequency correction sufficient to reduce the frequency error.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract: A system and method for reusing existing directional information to configure antennas in a wireless network is disclosed. The method includes retrieving existing directional information, the existing directional information having been established in a previous antenna training session with a receiver. The method further includes performing a signal-to-noise ratio (SNR) estimation procedure comprising: transmitting an SNR estimation probe message to the receiver via a directional antenna tuned with the existing directional information, and determining whether an estimated SNR value associated with the SNR estimation probe message is equal to or greater than a threshold SNR value. The method further includes transmitting a data message to the receiver via the directional antenna tuned with the existing directional information if it is determined that the estimated SNR value is equal to or greater than the threshold SNR value.

Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ?1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal ?1 (or its complement). The fundamental-enhanced signal ?1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y??1. The fundamental-notched signal y??1 is itself enhanced to generate a harmonic-enhanced signal ?2 that is used to notch the fundamental-notched signal y??1 again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ?1.

Abstract: Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.

Abstract: A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed by DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate transition data bits. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the transition data bits. The weighted threshold is calculated from at least one of the prior-received DFE detected data bits. In one embodiment, the DFE detection may also be dependent on an effective delay (?) of the DFE circuit in relation to the received signal baud-period, T.

Abstract: Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: A first phase adjustment circuit adjusts phases of a data decision clock signal and a first boundary decision clock signal according to a phase adjustment amount based on an output signal of a data decision circuit and an output signal of a first boundary decision circuit. A second phase adjustment circuit adjusts a phase of a second boundary decision clock signal according to a result of adding the phase adjustment amount and a phase adjustment amount offset. An adaptive equalization control circuit adjusts an equalization coefficient of an equalization circuit according to a data width of an output signal of the equalization circuit based on a logical comparison result between the output signal of the data decision circuit and an output signal of a second boundary decision circuit when the phase adjustment amount offset is changed.

Abstract: Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount: The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.

Abstract: Disclosed is a co-channel feedback signal cancelling regenerative repeater of the Advanced Television Systems Committee (ATSC) that extracts a predetermined reference value of feedback signal to be able to cancel the feedback signal among received signals, including: a signal receiving unit; a signal demodulating unit that converts frequency of a received signal and demodulates it into a baseband signal; an interference equalizing unit that corrects characteristics of the demodulated signal and cancels feedback signal; a channel equalizing unit that compensates for channel distortion of an original signal from which the feedback signal is cancelled; a modulating unit that modulates the channel distortion-compensated original signal and converts it into an analog signal; and a signal transmitting unit that converts the frequency of the modulated signal, controls and amplifies its gain, and transmits a regenerative transmission signal.

Abstract: An apparatus for performing channel estimation includes a time-domain estimating circuit to perform a channel estimation on a time-domain received signal to output a time-domain estimated signal, a second frequency-domain converting circuit to convert the time-domain estimated signal into a frequency-domain estimated signal, an error computing circuit to produce an error signal based on the frequency-domain estimated signal and a frequency-domain received signal, and a compensation circuit to compensate the frequency-domain estimated signal using the error signal so as to produce a final channel estimation signal. The apparatus is located in a receiving device that includes a first frequency-domain converting circuit to convert the time-domain received signal into the frequency-domain received signal, and an equalizer to generate a frequency-domain recovered signal based on the frequency-domain received signal and the final channel estimation signal.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Disclosed are an equalizer and an equalization method employing an adaptive algorithm for high speed data transmissions. The equalizer includes: a subtraction unit subtracting a feedback signal from an input signal to generate a subtraction signal; a timing signal generation unit generating a sampling timing signal; an equalization signal generation unit equalizing the subtraction signal according to the sampling timing signal to generate an equalization signal; and a feedback signal generation unit calculating a filter coefficient value by using the subtraction signal and the equalization signal, delaying the equalization signal, and weighting the delayed equalization signal according to the filter coefficient value to generate a feedback signal.

Abstract: A mechanism for jointly correcting carrier phase and carrier frequency errors in a demodulated signal. A computer system may receive samples of a baseband input signal (resulting from QAM demodulation). The computer system may compute values of a cost function J over a grid in a 2D angle-frequency space. A cost function value J(?,?) is computed for each point (?,?) in the grid by (a) applying a phase adjustment of angle ? and a frequency adjustment of frequency ? to the input signal; (b) performing one or more iterations of the K-means algorithm on the samples of the adjusted signal; (c) generated a sum on each K-means cluster; and (d) adding the sums. The point (?e,?e) in the 2D angle-frequency space that minimizes the cost function J serves an estimate for the carrier phase error and carrier frequency error. The estimated errors may be used to correct the input signal.

Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

Abstract: In an embodiment of an equalizer, a demodulator for MMSE-SIC receives a symbol vector to provide first information. A decoder receives the first information to provide second information to the demodulator. The decoder iteratively processes the first information to provide the second information. The demodulator and decoder are coupled in a loop for feeding back the second information for iteratively refining the first information. A detection-cancellation block of the demodulator receives the symbol vector to provide an equalized vector. A channel pre-processor block of the demodulator receives an initial vector output of the detection-cancellation block for the symbol vector for a demodulating-decoding iterative sequence to provide a weight vector. The channel pre-processor block provides an approximation using a fixed matrix to generate the weight vector. The detection-cancellation block receives the weight vector for equalization of the symbol vector in order to provide the equalized vector.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: A chip equalization apparatus and method for selecting cluster signals from broadcast signals being continuously received in multi-path channels for extracting a plurality of cluster signals from among the received broadcast signals and using a plurality of chip equalizers each having a tap coefficient update part for updating the tap coefficients of the selected cluster signals when the equalization outputs are combined to compensate the broadcast signals and provide low power consumption and efficient equalization for use in a satellite broadcasting receiving system.

Abstract: Disclosed is an adaptive receiving MIMO (multi input and multi output) system and method which decides a symbol detecting order so as to estimate the symbol having the minimum summation of weights of least square errors at the time of estimating the symbol for respective equalizers provided in parallel by the number of transmit antennas, and updates filter tap coefficients based on the RLS algorithm according to the detecting orders. Therefore, the filter tap coefficients are directly updated without tracking channels in the time-varying channel environment, and accordingly, detection performance very similar to those of the channel tracking and conventional V-BLAST scheme is provided with reduced complexity.