Abstract: A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.

Abstract: A method of initializing tap coefficients of an equalizer may include estimating impulse response coefficients of a channel through which a received signal traveled based on a known portion of the received signal. The method may also include loading the impulse response coefficients into a channel filter and generating a reference signal. The reference signal may be passed through the channel filter to build a training signal. Tap coefficients of the equalizer may be adjusted based on the training signal from the channel filter and on a delayed version of the reference signal.

Abstract: Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.).

Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: Various embodiments of the innovation provide adaptive equalization training for a receiver in a communication system. In certain embodiments, the receiver's coefficients are re-optimized while links are active and initialized.

Abstract: One or more embodiments describe a decision feedback equalizer utilizing symbol error rate biased adaptation function for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include determining values of tap coefficients used by the DFE based. The tap coefficients may be determined based on an error signal that is based on an estimated inter-symbol-correlated (ISC) signal. The tap coefficients may be determined based on a set of error vector(s), where each error vector in the set represents a difference between estimated symbols generated in the receiver and expected symbols. Determining the values of the tap coefficients may include using a symbol error rate function that estimates the actual symbol error rate in the receiver, wherein the symbol error rate function receives as input the set of error vector(s).

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: This invention discloses circuit and methods to decouple and pipeline block decision feedback multiplexer (MUX) loop in parallel processing decision feedback circuits. In one embodiment of this invention, a block decision feedback MUX loop consists of a pipelined intra-block decision feedback MUX stage and an inter-block decision feedback MUX stage to handle intra-block decision feedback selection and inter-block decision feedback selection separately. In the pipelined intra-block decision feedback stage, inter-block dependency is eliminated to enable pipelining. In another embodiment of this invention for moderately timing-critical parallel processing decision feedback circuits, a block decision feedback MUX loop is piecewise split into multiple series connected segments that each segment contains parallel branches. The intra-segment decision feedback selections of different segments are decoupled and processed in parallel.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A method for equalizing a received signal is provided. The signal is filtered and transmitted over a channel using an encoding scheme, where the encoding scheme has transmit symbols. This transmitted signal is then shaped such that the filtering and equalization adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative DFE with significantly reduced comparator levels.

Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.

Abstract: A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.

Abstract: An interference channel equalizer for receiving and processing at least two distinct RF data signals transmitted over the same frequency to a single receiving station that has at least one receiver for each distinct transmitted RF data signal. Each receiver processes an RF data signal received by its antenna and outputs an output data signal which corresponds to one of the distinct transmitted RF data signals. Each receiver includes an antenna configured to receive an RF data signal, a demodulator, a delay block to selectively delay the received RF data signal, an interference cancellation feed forward filter that uses the received signal from another receiver to remove co-channel due to another distinct RF transmitted data signal from the signal being processed, and a decision feedback equalizer to mitigate both intersymbol and multi-path interference from the received signal being processed.

Abstract: Apparatus and methods are provided to construct parameters associated with a precoder to a channel. Embodiments include apparatus and methods to apply a maximum a posteriori probability (MAP) equalization using offsets of signals introduced at a transmit end of a channel. Embodiments include apparatus and methods to construct a channel precoder based on using approximation of channel responses for a range of channel lengths.

Abstract: A hybrid equalization system includes an equalization device, a target channel impulse response device, a maximum likelihood sequence estimation device and a multiplexer. The equalization device receives a sampled baseband signal and performs an equalization operation thereon for generating first estimated symbols. The target channel impulse response device convolutes the first estimated symbol and a predetermined target channel response function for generating a training symbol corresponding to a target channel. The maximum likelihood sequence estimation device performs a maximum likelihood sequence estimation on the sampled baseband signal trained by first estimated symbols based on the target channel impulse response for generating second estimated symbols. The multiplexer selects the first estimated symbol or the second estimated symbol as an output of the hybrid equalization system according to a selection signal.

Abstract: A signal processing apparatus includes a signal processing unit configured to carry out signal processing on a single-carrier signal and a multi-carrier signal by making use of a plurality of common filters shared by the single-carrier signal and the multi-carrier signal.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: A method for updating a tap coefficient of a decision feedback equalizer is provided. The method includes sampling a first input signal received by a sampler of a decision feedback equalizer. It is determined if an amplitude of the first input signal falls within a range defined between a first predetermined voltage level and a second predetermined voltage level. If the amplitude of the first input signal falls outside the range, a tap coefficient is updated to generate an updated tap coefficient that is fed back to adjust an amplitude of a second input signal received at an input end of the decision feedback equalizer. If the amplitude of the first input signal falls within the range, the tap coefficient is free from being updated.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding.

Abstract: An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: A filter calculating device includes a first equalization filter calculating section that generates at least a first conversion matrix and a first triangular matrix based on a channel state of a first channel; a first quasi-orthogonalization section that calculates a first unimodular matrix based on the first triangular matrix; and a second equalization filter calculating section that generates at least a second conversion matrix and a second triangular matrix based on a channel state of a second channel and the first unimodular matrix.

Abstract: Assuring acquisition of symbol timing in a full-duplex data transceiver under inter-symbol interference conditions. One embodiment includes a transmitter comprising a first local clock having a first free running frequency, and a receiver comprising a second local clock having a second frequency initially set to a value higher than the first free running frequency. A first type decision-directed timing recovery mechanism is intentionally limited to only decreasing the frequency of the second local clock. A second type decision-directed timing recovery mechanism is not limited to only decreasing the frequency. The receiver receives symbols, decrease the frequency of the second local clock to a third frequency value using the first type decision-directed timing recovery mechanism, disables the first type mechanism after reaching the third frequency, and then phase-lock the second local clock to the optimal phase under MMSE criteria using the second type decision-directed timing recovery mechanism.

Abstract: One or more embodiments describe a decision feedback equalizer for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include initializing values of tap coefficients of the DFE based on values of tap coefficients of a partial response filter through which said transmitted symbols passed en route to said sequence estimation circuit. The method may include receiving estimates of transmitted symbols from a sequence estimation circuit, and receiving an error signal that is generated based on an estimated partial response signal output by the sequence estimation circuit. The method may include updating values of tap coefficients of the DFE based on the error signal and the estimates of transmitted symbols. The method may include generating one or more constraints that restrict the impact of the error signal on the updating of the values of the tap coefficients of the DFE.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: An apparatus includes an input, an output, an equalizer configured to receive an input signal at the input and to output an output signal for the output, and a reset block coupled to the equalizer and the output. The reset block is configured to pull the output signal at the output toward a bias voltage level based on a reset signal.

Abstract: A signal detection apparatus detects the frequency of an input signal without using a PLL. The detection apparatus includes a first and a second orthogonalizer, a phase difference calculator and an integrator, to control the variable coefficient a1 of a band-pass filter. Information e[k]=M·sin(?) representing the phase difference ? between the input data x[k] and the output data y[k] is calculated with the first and second orthogonalizers and the phase difference calculator. The sign of e[k] is inverted and a predetermined integral calculation is performed with the integrator, and the calculated integral value is set as the coefficient a1 of the band-pass filter. Every time input data x[k] is input, the coefficient a1 is changed by reducing it when e[k]>0 and increasing it when e[k]<0. Thus, the frequency of the output signal of the band-pass filter is matched to the input signal.

Abstract: A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.

Abstract: Provided are a transmitting apparatus and a transmitting method in a multiple input multiple output system. A power allocation controller includes a block Tomlinson-Harashima precoder (BTHP) that precodes and outputs data to be transmitted to each user in a nonlinear scheme. The BTHP removes and outputs inference signals from data for each user based on the channel information that is fed back from the users. The data for each user output from the BTHP are allocated with power by the power allocation controller. The power allocation controller calculates power allocation parameters so that receiving minimum distances at receiving ends for each user that receive data through the MIMO antennas are the same, and allocates the calculated parameters to data for each user.

Abstract: In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity model. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal.

Abstract: A technique for equalizing a distributed pilot OFDM signal with decision feedback involves correlating a received OFDM signal against a pilot reference to obtain a coarse channel estimate, where the received OFDM signal includes a distributed pilot signal and an OFDM data signal. The received OFDM signal is equalized based on the coarse channel estimate and the distributed pilot signal is removed to generate a coarse data signal estimate. The coarse data signal estimate is removed from the received OFDM signal using the coarse channel estimate to generate a residual pilot signal. The residual pilot signal can then be correlated against the pilot reference to obtain a fine channel estimate. The received OFDM signal is equalized based on the fine channel estimate, and the distributed pilot signal is removed to produce a fine data signal estimate from which data is recoverable.

Abstract: A system generates a set of candidate signals based on a received signal, whereby each candidate signal represents an adjustment of the signal for a different amount of potential noise. The system selects one of the candidate signals based on a selected subset of previous samples and the values of the selected subset of samples. The subset of previous samples is selected based on a predicted noise pattern.

Abstract: In a method for detecting symbols in a signal received via a communication channel, the signal including a plurality of signal points, each signal point in the plurality of signal points is processed using a decision feedback equalizer (DFE) to produce a DFE decision. Reliability of the DFE decision is assessed to determine whether the DFE decision is at least one of i) reliable or ii) not reliable. When it is determined that the DFE decision is not reliable, a block of signal points of the plurality of signal points is processed using a Viterbi Detector (VD) to generate a block of VD decisions. The block of VD decisions is selected to be used in place of a block of DFE decisions.

Abstract: An apparatus having a transmitter is disclosed. The transmitter generally has a filter coupled to a communication channel. The transmitter may be configured to adjust the filter using information based on an estimate of one or more characteristics of the communication channel.

Abstract: A technique is used to realize a generalized decision feedback equalizer (GDFE) Precoder for multi-user multiple-input multiple-output (MU-MIMO) systems, which significantly reduces the computational cost while resulting in no capacity loss. The technique is suitable for improving the performance of various MU-MIMO wireless systems including future 4G cellular networks. In one embodiment, a method for configuring a GDFE precoder in a base station of a MU-MIMO wireless system having k user terminals, each user terminal having associated therewith a feedforward filter. The method comprises computing a filter matrix C using one of a plurality of alternative formulas of the invention; and, based on the computation of the filter matrix C, computing a transmit filter matrix B for a transmit filter used to process a symbol vector obtained after a decision feedback equalizing stage of the GDFE precoder, a feedforward filter matrix F, and an interference pre-cancellation matrix G.

Abstract: An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive circuit and the one or more tone predictor(s), form a feed-forward NBI predictor wherein the received signal is supplied as the input signal of the adaptive circuit. The result of subtraction may be supplied to a slicer that slices the result, yielding a sliced signal which is subtracted from the received signal to generate a signal can be used as the input signal, to implement a feedback NBI predictor.

Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Abstract: In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.

Abstract: An adaptive finite-impulse-response filter includes a series of taps; each tap has a corresponding value of tap coefficient. Values of tap coefficients are calculated to minimize a system error function. The solution is under-constrained, and some values of tap coefficients can grow and cause overflow errors. Growth of tap coefficients is controlled by introducing tap leakage. Disclosed is a symmetric leakage algorithm, in which an updated value of the tap coefficient of a particular tap is based on the old value of the tap coefficient of the particular tap, on the old values of the tap coefficients of a set of taps preceding the particular tap, and on the old values of the tap coefficients of a series of taps following the particular tap.

Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract: A clock data recovery circuit includes an equalizer, a multi-phase clock generator, a sampling and check unit, a signal edge detection unit and an adjusting unit. The equalizer performs an equalization on an incoming data signal. The multi-phase clock generator generates multiple clock signals and at least one pair of check signals. The sampling and check unit samples the incoming data signal according to the clock signals to obtain a sequence, and checks whether the sequence matches a predetermined pattern. If so, the signal edge detection unit controls the sampling and check unit to detect a transition between values of the sequence two on two based on the pair of check signals to obtain a detection value. The adjusting unit determines whether the transition is too early or too late according to the detection value, and adjusts the equalization on the incoming data signal according to the determination result.

Abstract: Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.

Abstract: Described herein are a method, an apparatus, and a system to compensate inter-symbol interference (ISI) for a signal at a receiver. The apparatus comprises a first logic unit to generate decision feedback equalizer (DFE) coefficients for data samples of a data signal; a second logic unit to generate DFE coefficients for edge samples of the data signal, wherein the DFE coefficients for the edge samples of the data signal are based at least in part on the DFE coefficients for the data samples of the data signal; and a third logic unit to compensate the data and edge samples of the data signal for inter-symbol interference at the data and edge samples of the data signal, wherein the third logic unit to compensate for inter-symbol interference by using the DFE coefficients for the data and edge samples generated by the first and the second logic units respectively.

Abstract: Techniques for performing decision feedback equalization are described. A feed-forward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an on-time sample. The reliability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. Different feed-forward and feedback filter responses may be derived with different constraints on the feedback filter and different assumptions for the reliability parameter. Equalization is performed with the feed-forward and feedback filter responses.