Abstract: According to an embodiment, a signal processing apparatus includes a first signal processor, a second signal processor and a third signal processor. The first signal processor suppresses an offset component remaining in a reproduction signal read from an optical recording medium to obtain a first signal. The second signal processor suppresses a nonlinear distortion component remaining in the first signal to obtain a second signal. The third signal processor suppresses a correlation noise component remaining in the second signal to obtain a third signal.

Abstract: An equalization method includes carrying out frequency domain conversion of M received signals into a 2M received vector having 2M elements, carrying out channel estimation and noise/interference estimation based on the 2M vector, calculating a 2M channel vector and a (2M)×(2M) noise/interference matrix, selecting a 2M?1 or less channel vector from the calculated 2M channel vector, selecting a (2M?1)×(2M?1) or less noise/interference matrix from the calculated (2M)×(2M) noise/interference matrix, calculating a 2M?1 or less equalization coefficient vector as equalization coefficients based on the selected 2M?1 channel vector and the selected (2M?1)×(2M?1) noise/interference matrix, selecting a 2M?1 or less received vector from the 2M received vector, and equalizing the selected 2M?1 received vector by using the calculated. equalization coefficients.

Abstract: A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

Abstract: A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver.

Abstract: A multi-mode parameter adaptation module can comprise different modes for generating parameters to minimize an error between an output of an adaptive processor and an ideal output of the adaptive processor. A mode control module can monitor a performance signal p indicative of an operating condition a receiver of which the adaptive processor is a part. Upon detecting a change condition form the performance signal p, the mode control module can change the operating mode of the parameter adaptation module to suit the current operating condition.

Abstract: Methods of efficient calculation of initial equalizer coefficients are described. In a first stage, a channel matched filter is generated based on an estimate of CIR and then used to filter the CIR estimate. In a second stage, initial FFE coefficients are calculated from a portion of the match filtered CIR and then these initial FFE coefficients and the estimate of CIR may be used to generate initial DFE coefficients. In various embodiments, a window is applied to the CIR estimate before the matched filter is generated. In various embodiments, the second stage is iterated to minimize the pre-echoes following the FFE.

Abstract: Among other things, the present invention addresses timing issues related to a polarity control scheme in DFE implementation. Multiplexing that may be necessary for implementing a polarity control scheme is incorporated into multiplexing that may be required to convert half rate data into full rate data in a delay element of a DFE. Clocking signals are provided to a multiplexer that are encoded with polarity information. The various clock signals are generated using a clock generation circuit that incorporates polarity control.

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.

Abstract: A sampler circuit for a decision feedback equalizer and a method of use thereof. One embodiment of the sampler circuit includes: (1) a first sampler portion including a series-coupled first master regeneration latch and first slave latch, (2) a second sampler portion including a series-coupled second master regeneration latch and second slave latch, and (3) a first feedback circuit coupled to a first node between the first master regeneration latch and the first slave latch and operable to provide a feedback signal to the second master regeneration latch to cause a bias charge to be built up therefor.

Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.

Abstract: Systems and methods are provided for fast and precise estimation of frequency with relatively minimal sampling and relatively high tolerance to noise.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: Described herein is apparatus and system for switching equalization. The apparatus comprises a sampler to sample an input signal; and an attenuator, coupled to the sampler, with a hysteresis associated with the input signal, the hysteresis of the attenuator is configurable to cancel hysteresis of a communication channel coupled to the attenuator.

Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Abstract: A system (10) for beamforming using a microphone array, the system (10) comprising: a beamformer consisting of two parallel adaptive filters (12, 13), a first adaptive filter (12) having low speech distortion (LS) and a second adaptive filter (13) having high noise suppression (SNR); and a controller (14) to determine a weight (?) to adjust a percentage of combining the adaptive filters (12, 13) and to apply the weight to the adaptive filters (12, 13) for an output (15) of the beamformer.

Abstract: A phase offset compensator for compensating a phase offset is provided. The phase offset includes a first phase sub-offset and a second phase sub-offset. The phase offset compensator includes a feedback loop comprising a first loop filter, the feedback loop being configured to compensate the first phase sub-offset of the phase offset, and a feed forward loop comprising a second loop filter, the feed forward loop being configured to compensate the second phase sub-offset of the phase offset.

Abstract: A system that incorporates the subject disclosure may include, for example, a process that includes adjusting a filter in electrical communication between an input terminal and a demodulator. The filter is applied to an information bearing signal, e.g., to mitigate interference, received at the input terminal, resulting in a filtered signal. An error signal is received, indicative of errors detected within information obtained by demodulation of a modulated carrier of the filtered signal. A modified filter state is determined in response to the error signal and the filter is adjusted according to the modified filter state, e.g., to improve mitigation of the interference. Other embodiments are disclosed.

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract: One or more embodiments describe a decision feedback equalizer utilizing symbol error rate biased adaptation function for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include determining values of tap coefficients used by the DFE based. The tap coefficients may be determined based on an error signal that is based on an estimated inter-symbol-correlated (ISC) signal. The tap coefficients may be determined based on a set of error vector(s), where each error vector in the set represents a difference between estimated symbols generated in the receiver and expected symbols. Determining the values of the tap coefficients may include using a symbol error rate function that estimates the actual symbol error rate in the receiver, wherein the symbol error rate function receives as input the set of error vector(s).

Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.

Abstract: A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down.

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract: Methods, systems, and devices are described for equalizing data from an optical signal. Samples are filtered with at least one filter to compensate for polarization mode dispersion in an optical path. The filtered samples may be used to determine errors based on a difference between a radius of a recovered symbol and a target radius. A parameter may be assigned to one or more of the errors and properties of the at least one filter may be updated based on the assigned parameters. The parameter may be assigned from a small set of parameters based on at least one threshold value. Outputs generated from the filtered samples may also be assigned a parameter from a different set of parameters. The parameter assigned to the output may be used to update the particular set of taps of the at least one filter from which the output was generated.

Abstract: A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Abstract: A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.

Abstract: A method of blind tap coefficient adaptation includes receiving a digital data signal including random digital data, equalizing a first portion of the digital data signal using a first set of predetermined tap coefficients and a second portion of the digital data signal using a second set of predetermined tap coefficients. The method includes generating a first eye diagram and a second eye diagram from a first portion and a second portion of an equalized signal, respectively. The first eye diagram is compared with the second eye diagram to determine which of the sets of predetermined tap coefficients results in a data signal having a higher signal quality. The method includes inputting to an equalizer as an initial set of tap coefficients the first set of predetermined tap coefficients or the second set of predetermined tap coefficients according to the determination.

Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.

Abstract: A transceiver including an equalizer and a control circuit. The equalizer receives an input signal and first coefficients. The equalizer includes taps that, based on the first coefficients, filter the input signal to generate an output signal. The taps include a precursor tap, a unity tap and postcursor taps. The control circuit selects the first coefficients such that a sum of the first coefficients is equal to a predetermined value. The first coefficients include a precursor coefficient, a second coefficient, and post cursor coefficients corresponding respectively to the precursor tap, the unity tap, and the postcursor taps. The control circuit: maintains the second coefficient at a fixed value; based on the second coefficient, selects the precursor coefficient and the postcursor coefficients; and while maintaining the second coefficient at the fixed value and while the equalizer is receiving the input signal, adjusts the precursor coefficient or one of the postcursor coefficients.

Abstract: A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Abstract: A radio frequency (RF) front end having group delay mismatch reduction is provided. One embodiment provides a first feed forward path and a second feed forward path. The second feed forward path is electrically in parallel with the first feed forward. The second feed forward path has a first signal path and a second signal path. The first and second signal paths are arranged to be electrically in parallel. The first signal path has a digital filter. The second signal path has a tunable analog filter. The tunable analog filter operates to reduce a delay associated with the second feed forward path as compared with a delay associated with the first feed forward path.

Abstract: A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down.

Abstract: A method, apparatus, and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A method and associated processing module for an interconnection system, providing a pre-tap tuning directing and a post-tap tuning directing. The interconnection system includes a transmitter filter and a receiver equalizer; the transmitter filter performs filtering according to a pre-tap and a post-tap, and the receiver equalizer performs equalization according to an equalizer tap. The pre-tap tuning directing includes: forming an indicative pattern with a plurality of data samples and a transition sample from an equalized signal, comparing if the indicative pattern matches predetermined pattern(s), and accordingly directing whether the pre-tap is incremented/decremented. The post-tap tuning directing selects whether the post-tap is incremented/decremented according to a positive/negative sign of the equalizer tap.

Abstract: In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals.

Abstract: A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver.

Abstract: A pipelined receiver comprises a programmable feed forward equalizer (FFE), a programmable decision feedback equalizer (DFE), and logic for controlling a ratio of FFE and DFE to apply to a received signal based on at least one channel parameter.

Abstract: An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response to the plurality of digital filter control codes. The plurality of source series terminated driver slices configured to generate an output signal according to a selected one of the plurality of communication specifications in response to the plurality of driver slice control codes, a main cursor signal, a pre-cursor signal, and a post cursor signal.

Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.

Abstract: An optical transceiver includes an optical IC coupled to a processor IC. For transmit, the optical IC can be understood as a transmitter IC including a laser device or array. For receive, the optical IC can be understood as a receiver IC including a photodetector/photodiode device or array. For a transmitter IC, the processor IC includes a driver for a laser of the transmitter IC. The driver includes an equalizer that applies high frequency gain to a signal transmitted with the laser device. For a receiver IC, the processor IC includes a front end circuit to interface with a photodetector of the receiver IC. The front end circuit includes an equalizer that applies high frequency gain to a signal received by the receiver IC. The driver can be configurable to receive a laser having either orientation: ground termination or supply termination.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: The present disclosure relates to the field of network communication, and specifically discloses an adaptive equalization method, including: obtaining a first filtered signal according to a first filter coefficient; deciding the first filtered signal based on an original constellation map to obtain a first decision signal, and deciding the first filtered signal based on a level (n?1) constellation map to obtain a level (n?1) pseudo decision signal; if average energy of the level (n?1) error signal is less than a level (n?1) threshold, switching the level (n?1) constellation map to a level n constellation map; obtaining a second filter coefficient according to the update magnitude; obtaining a second filtered signal according to the second filter coefficient; and deciding the second filtered signal based on the original constellation map to obtain a second decision signal. Embodiments of the present disclosure also disclose an adaptive equalizer.

Abstract: Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.