Abstract: A complex band-pass ?? AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

Abstract: A three-order sigma-delta modulator having a feedback and a feedforward configuration. The three-order sigma-delta modulator includes: an analog-to-digital converter; a digital-to-analog converter; a first integrating network; a second integrating network connected in series to the first integrating network; a third integrating network connected in series to the second integrating network; and an adder, to combine a feedforward gain signal generated by passing the first output signal from the first integrating network through a feedforward gain unit with a modulation signal that is generated by passing the third output signal from the third integrating network through a modulation gain unit and to generate a desired noise transfer function.

Abstract: An apparatus for processing a digital signal that generates a one-bit output signal using a delta-sigma modulation apparatus, which includes a quantizer for quantizing an integrated output of a sixth integrator to generate a one-bit output signal that is send to respective integrators through an adder under feedback processing to output the one-bit output signal to the outside of a six-order Delta-sigma modulator, and a control unit for generating a control signal that controls the feedback loop signal from the quantizer so as to change the signal level of a signal component of the audio frequency band of the one-bit output signal. The control unit receives an integrated output from a second integrator being an input side integrator of the six-order delta-sigma modulator.

Abstract: A digital transmission line tap circuit is provided for applying a non-intrusive tap on a digital transmission line thus allowing the transmission signal to be monitored or utilized by another piece of transmission equipment. The tap circuit incorporates all the required functions of the tap in one circuit and eliminates large components, such as termination transformers.

Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.

Abstract: A bandpass sigma-delta modulator using acoustic resonators or micro-mechanical resonators. In order to improve resolution at high frequencies, acoustic resonators or micro-mechanical resonators are utilized in a sigma-delta modulator instead of electronic resonators. The quantized output is fed back using a pair of D/A converters to an input summation device. In fourth order devices, the feed back is to two summation devices in series. Such a sigma-delta modulator is usable in a software defined radio cellular telephone system and in other applications where high-frequency and high-resolution A/D conversion is required.

Abstract: A Delta-Sigma Analog-to-Digital Converter (ADC) that can have a very high sampling rate (over 100 GHz) and which is preferably optically sampled to help achieve its very high sampling rate. The sampling rate can be many times higher than the regeneration speed of the electronic quantizers used in the ADC.

Abstract: A signal processing device uses a ?? modulator having varying effective orders to ensure an S/N ratio by selecting a high order when a 1-bit music signal is output via the ?? modulator. The signal processing device prevents noise during switchover by shifting to a low order just before the ?? modulator is bypassed if this occurs. The present invention provides a digital signal processing device which can switch between an original sound signal and a ?? modulation signal and yield a sufficient S/N ratio for a reprocessed ?? modulation signal. If any 1-bit original sound signal is input, little switching noise is generated.

Abstract: A quantizer adapted for use with a delta-sigma analog-to-digital converter. The quantizer includes first and second comparators adapted to compare an input analog signal to a threshold and provide a digital output in response thereto. First and second thresholds are provided to the first and second comparators respectively. In accordance with the present teachings, a mechanism is provided for changing the thresholds to minimize conversion errors. While the mechanism for changing the thresholds may be implemented with resistive and/or capacitive ladders, in the illustrative embodiment, digital-to-analog converters are utilized. The DACs are driven by error shaping logic. The inventive quantizer allows for an improved delta-sigma analog-to-digital converter design which combines an ADC and a DAC. The DAC reconstructs the analog equivalent of the digital output of the ADC. The ADC is a flash converter consisting of one comparator per threshold.

Abstract: Apparatus for storing or transmitting a one-bit digital signal comprises an input inverter for inverting a subset of the data bits of an input one-bit digital signal, to generate a bit-inverted signal; a storage or transmission medium for storing or transmitting the bit-inverted signal; and an output inverter for inverting the subset of the data bits of the bit-inverted signal, to regenerate the input one-bit digital signal.

Abstract: Provided is a circuit that has a simple circuit configuration and can detect zero values in a 1-bit digital signal irrespective of a recording medium such as SACD. DSD data forming the 1-bit digital signal are successively sent to a shift register (1) whose number of stages corresponds to the number of bits of an idle pattern such as “101010101” which appears when assuming a zero value. For example, the shift register (1) is an 8-bit shift register. An adder (2) sums up the values at each stages of the shift register (1). A zero decision circuit (4) produces an output indicating decision of zero if the sum value is half of the number of bits. A counter (5) keeps counting while the output indicating zero decision is being delivered. If the count value of the counter exceeds a given value, the counter produces an output indicating detection of a zero value.

Abstract: The invention discloses a system and method for improving the out-of-band noise response of a multi-order delta-sigma modulator. The system and method includes programmable delta-sigma modulators which may be programmed to vary the reference signals at each modulator stage subsequent to the first stage relative to the reference signal of the first modulator stage. The resulting signal output will then typically exhibit the enhanced noise suppression characteristics of a dithered signal without the added circuitry and power required of a dithering apparatus.

Abstract: A digital signal processor receives 1-bit audio signals acquired by sigma modulation and sent over a predetermined transmission line and makes a changeover between the audio signal and a mute pattern includes an IEEE 1394 interface. The IEEE 1394 interface receives an isochronous packet sent over an IEEE 1394-formatted transmission line, extracts music data from the packet, supplies the music data to a DRAM, monitors the amount of data stored in the DRAM, reads a 1-bit digital signal or generates a mute pattern such as a 9-6 pattern, and makes a changeover between the 1-bit digital signal read from the DRAM and mute pattern while fading them. The digital signal processor further includes a D-A converter to convert the 1-bit digital signal supplied from the IEEE 1394 interface into an analog signal.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A digital-to-analog converter (“DAC”) system utilizes notch filters and chopping modulation technology to remove l/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency and all harmonics equal to approximately one-half of a digital input signal sampling frequency. A notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Another notch filter attenuating signals having frequencies around twice the chopping frequency further reduces fold back of noise into the baseband.

Abstract: Signal parameter information can be transmitted from a first communications device to a second communications device. For example, communications can be received at the first communications device from the second communications device, and a plurality of samples of a signal parameter can be generated characterizing the received communications. In addition, a plurality of delta-modulation values can be calculated responsive to the respective samples of the signal parameter wherein the plurality of delta-modulation values are associated with corresponding ones of the plurality of samples of the signal parameter characterizing the received communications. The delta-modulation values can be transmitted to the second communications device. Related devices are also discussed.

Abstract: A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.

Abstract: A sigma-delta converter operates over a predetermined bandwidth and includes a feedback loop comprising a forward path and a feedback path. The forward path includes, in series, a summer, a filter, and a comparator. The comparator produces an output signal that is fed back to a negative input of the summer via the feedback path. The sigma-delta converter also includes at least one instability generator positioned in the forward path and/or the feedback path. The instability generator generates one or more out-of-band instabilities in the feedback loop to substantially improve the in-band signal-to-noise performance of the converter for input signal amplitudes near a low end of the converter's dynamic range. The converter may be employed as an A/D converter, a D/D converter, or a D/A converter in a receiver and/or a transmitter of a wireless communication device.

Abstract: DC transients are removed from a digital filter such as a sigma delta filter (in particular from a sigma delta high pass filter) from the outset by presetting an input summing node to a sigma delta modulator. While the input summing node may be preset using any appropriate input, in a disclosed embodiment, a sigma delta high pass filter is preset by switching a partial feedback term between an input containing the non-zero preset value and the normal input comprising the output from the input summing node. The preset value is chosen based on the value of the zero of the transfer function of the sigma delta high pass filter, e.g., with the complement of the gain factor.

Abstract: A delta-sigma modulator for driving an output stage is disclosed. The delta-sigma modulator operates between first and second voltages and includes a loop filter, a quantizer, and a feedback loop coupling an output of the quantizer and an input of the loop filter. The feedback loop includes compensation circuitry for compensating for variations in the first and second voltages in response to a measured average of the first and second voltages and a measured difference between the first and second voltages. Measuring circuitry measures the average and the difference of the first and second voltages.

Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

Abstract: A bandpass sigma-delta modulator using acoustic resonators or micro-mechanical resonators. In order to improve resolution at high frequencies, acoustic resonators or micro-mechanical resonators are utilized in a sigma-delta modulator instead of electronic resonators. The quantized output is fed back using a pair of D/A converters to an input summation device. In fourth order devices, the feed back is to two summation devices in series. Such a sigma-delta modulator is usable in a software defined radio cellular telephone system and in other applications where high-frequency and high-resolution A/D conversion is required.

Abstract: A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A wireless receiver receives a wireless signal by inverting the polarity of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator clocked by said conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a+a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b+b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b+b].

Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Abstract: The present invention relates to a device for performing predetermined processing on a signal inputted thereto that may have signal amplitude of more than one bit, which signal is obtained by subjecting one-bit serial signals to predetermined signal processing, wherein the signal amplitude of more than one bit is converted to a one-bit serial signal by accumulating the signal amplitude exceeding that of one bit, delaying the accumulated signal on the basis of the input signal, and outputting the accumulated signal.

Abstract: A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.

Abstract: The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.

Abstract: A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

Abstract: A code specifies characteristics of pulses transmitted and received by an impulse transmission system. The invention provides methods for defining non-allowable regions within pulse characteristic value range layouts enabling non-allowable regions to be considered when generating a code. Various approaches are used to define non-allowable regions based either on the pulse characteristic value range layout or on characteristic values of one or more other pulses. Various permutations accommodate differences between temporal and non-temporal pulse characteristics. Approaches address characteristic value layouts specifying fixed values and characteristic value layouts specifying non-fixed values. When generating codes to describe pulses, defined non-allowable regions within pulse characteristic value layouts are considered so that code element values do not map to non-allowable pulse characteristic values.

Abstract: A coding method for a pulse transmission system specifies temporal and/or non-temporal pulse characteristics according to temporal and/or non-temporal characteristic value layouts having one or more allowable and non-allowable regions. The method generates codes having predefined properties. The method generates a pulse train by mapping codes to the characteristic value layouts, where the codes satisfy predefined criteria. In addition, the predefined criteria can limit the number of pulse characteristic values within a non-allowable region. The predefined criteria can be based on relative pulse characteristic values. The predefined criteria can also pertain to spectral properties and to correlation properties. The predefined criteria may pertain to code length and to the number of members of a code family. The pulse train characteristics may pertain to a subset of the pulse train.

Abstract: A transmitting apparatus and a reproducing apparatus include a converter for converting an input one-bit digital signal into a multi-bit signal while effecting down-sampling of a sampling frequency. A one-bit digital signal that could develop an overflow (clip) depending on its modulation degree is attenuated at a stage upstream of the input of the converter, and the multi-bit signal is amplified at a stage downstream of the converter to avert a clipped state between the stages.

Abstract: A narrow-band bandpass filter is implemented in a field programmable gate array (FPGA). An analog-to-digital converter quantizes an input analog signal with a high degree of precision to produce input data samples. A sigma-delta modulator re-quantizes the samples with a substantially lower degree of precision. The re-quantized samples are passed through a bandpass, lowpass, or highpass, finite impulse response (FIR) filter which operates at the lower degree of precision. The reduced degree of precision enables a substantial reduction in the number of resources required to implement the narrow-band bandpass, lowpass, or highpass filter in the FPGA. The modulator includes a predictor filter which has a center frequency coinciding with that of the FIR filter, and redistributes noise such that it is lowest within the passband of the FIR filter. The narrow-band filter design can be adapted to incorporate a single or multi-rate decimator configuration.

Abstract: The invention relates to digital signal processing and specifically to level control of a pulse density modulated (PDM) signal generated by a sigma-delta modulator. A single-bit pulse density modulated PDM signal is generated by a first sigma-delta modulator being an analog modulator, for instance. Level control is performed by multiplying the single-bit pulse density modulated PDM signal by a multibit multiplier to obtain a multibit number stream, which is reconverted into a single-bit PDM signal by a second digital sigma-delta modulator, as to the signal-to-noise ratio. Thus the most significant factor in the total signal-to-noise is the noise level of the first sigma-delta modulator, by which the PDM signal was originally generated. In the subsequent second sigma-delta modulator, the PDM signal can then be attenuated as much as is the difference between SNR performance of the modulators without any decrease in the total signal-to-noise ratio.

Abstract: A receiver with an integrated mixer/Sigma-Delta Modulator configuration for digitizing a relatively low-bandwidth signal modulated on a high-frequency carrier, for example in a radio receiver. The Sigma-Delta Modulator has an continuous-time loop filter (F1, F2) with anti-aliasing characteristics which eliminate the need for a separate lowpass filter between the mixer (MX) and the Sigma-Delta Modulator.

Abstract: A Delta-Sigma Analog-to-Digital Converter (ADC) that can have a very high sampling rate (over 100 GHz) and which is preferably optically sampled to help achieve its very high sampling rate. The sampling rate can be many times higher than the regeneration speed of the electronic quantizers used in the ADC.

Abstract: An improved three-order sigma-delta modulator having a feedback and a feedforward configuration.

Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a +a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b +b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b +b].

Abstract: An eight-channel PCM recorder is utilized for recording two channels of delta-sigma modulated audio signals. Employed to this end is a PCM adapter comprising a bit stream divider for dividing the bit streams of the delta-sigma modulated signals into series of sixteen-bit segments, and a reformatter for rearranging the bit segments into eight signals having a format in agreement with the format of the PCM signals normally handled by the PCM recorder. The eight reformatted delta-sigma signals are introduced into the PCM recorder thereby to be recorded in place of the eight channels of PCM signals.

Abstract: A quantizer adapted for use with a delta-sigma analog-to-digital converter. The quantizer includes first and second comparators adapted to compare an input analog signal to a threshold and provide a digital output in response thereto. First and second thresholds are provided to the first and second comparators respectively. In accordance with the present teachings, a mechanism is provided for changing the thresholds to minimize conversion errors. While the mechanism for changing the thresholds may be implemented with resistive and/or capacitive ladders, in the illustrative embodiment, digital-to-analog converters are utilized. The DACs are driven by error shaping logic. The inventive quantizer allows for an improved delta-sigma analog-to-digital converter design which combines an ADC and a DAC. The DAC reconstructs the analog equivalent of the digital output of the ADC. The ADC is a flash converter consisting of one comparator per threshold.

Abstract: A method and apparatus for improving an S/N ratio in a digital-to-analog conversion of a PDM signal are provided. A digital-to-analog conversion system comprises an S/N ratio improving section. The S/N ratio improving section has a signal component extractor which extracts a signal component included in the PDM signal, and outputs a digitally filtered output signal. The digitally filtered output signal has a second full scale smaller than a first full scale of the PDM signal. The S/N ratio improving section also comprises a full-scale matching unit which matches the second full scale of the digitally filtered output signal with a third full scale of digital-to-analog conversion.

Abstract: GSM baseband receiver arrangement using digital signal processing is disclosed. The baseband receiver arrangement comprises two channel for inphase (Iin) and quadrature (Qin) components of the received signal. The DC offset of each channel is separately estimated by accumulating samples from the outputs of the second filter stages M1 and M2 and dividing the result by 64. The result is then negated and applied to the digital DC offset controls I1 and I2. This two stage process ensures that the majority DC offset is removed prior to variable gain, and the residual DC offset is removed before digital frequency shifting. Applying DC offset correction before the digital frequency shifting ensures that DC is annulled for any subsequent shift.

Abstract: A delta-sigma modulator for use in power amplification of audio signals is configured by an integration circuit, a 1-bit quantizer, an output inversion inhibitor circuit, a delay circuit, and an adder. An analog signal is supplied to the integration circuit by way of the adder, wherein it is subjected to integration. An integration result is subjected to quantization by the 1-bit quantizer to produce 1-bit digital signals. The output inversion inhibitor circuit inhibits an output signal of the 1-bit quantizer from being re-inverted during a re-inversion inhibiting period corresponding to a preset number ‘N’ (where N≧2) of clock pulses counted after the timing when the output signal of the 1-bit quantizer is inverted. The output of the output inversion inhibitor circuit is delayed by one sample and is fed back to the adder by way of the delay circuit.

Abstract: A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b0, and a zero at location a0. The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.

Abstract: A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

Abstract: The present invention, generally speaking, provides a simple, all-digital method and apparatus for determining the phase of a first clock signal relative to a second clock signal. The first clock signal may be a digital approximation of a periodic analog signal such as an RF signal. A sampling technique is employed that produces a stream of digital bits containing relative phase information. From the stream of digital bits is formed a digital word indicative of the relative phase. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.