Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: The present invention relates to an apparatus and method of acquiring initial synchronization of a terminal in a mobile communication system. According to an exemplary embodiment of the present invention, one or more auto-correlation values of a preamble constituting a signal that is received from a base station are calculated. Averages of the calculated auto-correlation values according to samples are calculated, and then a peak value is detected among the calculated values. Then, a cell search is performed on the basis of the detected peak value, and a peak value from the result of the cell search is regularized. Then, the regularized peak value is compared with a predetermined reference value such that it is checked whether synchronization of a signal that has been searched is accurate or not.

Abstract: User Equipment in a wireless communication network considers the downlink channel bandwidth in setting out of synchronization (OoS) and in synchronization (IS) thresholds and filter durations. Additionally, the UE may consider transmitter antenna configuration—that is, the number of transmitting antennas in a MIMO system—in setting the OoS and IS thresholds. The UE determines it is OoS when a monitored, filtered, downlink channel quality metric, such as reference symbol SINR, is below the OoS threshold.

Abstract: A method is provided for offsetting a reference frequency of a quadrature reference clock signal. A quadrature reference clock (110) generates the quadrature reference clock signal at the reference frequency, while a quadrature variable offset clock (130) generates a quadrature clock signal at a base offset frequency based on a base offset value it receives from a control circuit (560). The base offset value can be determined in many ways, including reading it from a local memory (910) or receiving it from a remote device (1010). A polyphase mixer (140) performs a polyphase mixing operation between the quadrature reference clock signal and the offset clock signal to generate an agile clock signal having an agile clock frequency equal to the reference frequency plus the base offset frequency. If desired, the method can revise the offset frequency based on actual conditions and determine a corresponding revised offset value (920, 1020).

Abstract: One embodiment of the invention provides a wireless communication device including: a wireless communication unit that wirelessly receives first power consumption information from a device, the first power consumption information including a plurality of data pieces, each data piece indicating power consumption in the device for processing a streaming data signal encoded in each of a plurality of encoding formats; an encoding format selection unit that selects one of the encoding formats for a data signal to be transmitted, based on the received first power consumption information; and an encoding controller that encodes the data signal to be transmitted in the encoding format selected by the encoding format selection unit to generate an encoded data signal as a streaming data and outputs the encoded data signal to the wireless communication unit, wherein the wireless communication unit wirelessly transmits the encoded data signal as the streaming data to the device.

Abstract: A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

Abstract: Systems and methods are described herein that cause data from asynchronous data sources to be provided with a timestamp that corresponds to a common time base. A trigger board can be used to control synchronized data sources, and can generate timestamps when data is collected by the synchronized data sources. Unsynchronized data sources can generate data independent of the trigger board. System timestamps are generated each time data from the synchronized data source and the unsynchronized data source is received. Values of the system timestamp can be modified, and can be replaced by timestamps that correspond to the time base used by the trigger board.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: Improved time synchronization is provided among the devices of an industrial process control system, e.g., a Substation Automation system, during a temporary absence of a system reference time. Hence, disruption of time-critical protection and control functions due to re-synchronization following the temporary absence of the system reference time is avoided, and the availability of time-critical functions configured on the devices is increased. During normal operation, a device of the system records an offset or discrepancy between the system reference time and an internal local clock of the device for a period of several hours. As soon as the system reference time breaks down, the device starts predicting the offset or drift between its local clock and the unavailable system reference time based on the recorded offset history.

Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

Abstract: A system for synchronising stations in a communications network comprising: at least one airborne or space-based vehicle; and at least two stations, each station having receiver means in data communication with the at least one airborne or space-based vehicle and control means in data communication with the receiver means and in control communication with a communication means. When each receiver means receives a synchronisation signal from the at least one airborne or space-based vehicle each receiver means forwards the synchronisation signal to its respective control means. The respective control means processes the synchronisation signal to determine the operational frequency required by its respective communication means to maintain or establish communication with the other station. The respective control means also operates to control its respective communication means to change to the determined operational frequency.

Abstract: A source communication device includes a source network clock to control timing of communicating with other devices in a network, a source streaming clock associated with processing of audio or video data, a time stamp generator to generate a time stamp that includes a source network clock value and a source streaming clock value, and a time stamp insertion mechanism that incorporates the time stamp into a data unit that is to be transmitted to one of the other devices in the network. A sink communication device includes a sink network clock synchronized with the source network clock, a sink streaming clock associated with processing of audio or video data, and a sink time stamp mechanism to compare a sink streaming clock value with the source streaming clock value, and adjust the sink streaming clock based on the comparison.

Abstract: A system and method are provided which coordinate the actions of a plurality of devices via scheduling occurrence of the actions based on synchronized local clocks of the devices. Thus, a plurality of devices are communicatively coupled via a communication network, and the devices have their local clocks synchronized to a high degree of precision, using IEEE 1588, NTP, or some other technique for synchronizing their local clocks. “Time bombs” can be scheduled on the devices to coordinate the occurrence of actions between the devices in accordance with the detonation times set for the respective time bombs. In certain embodiments, not only the detonation time, but also the respective action to be triggered upon detonation is programmable for each device. The time bombs implemented on the various devices can be used to coordinate the operations of the various devices with a high degree of temporal precision.

Abstract: A contactless integrated circuit (IC) card can include: an analog interface block operable to demodulate a received radio frequency (RF) signal into multiple versions thereof according to a first plurality of communication protocols, respectively; a controller operable to select from among a second plurality of communication protocols; and a universal asynchronous receiver/transmitter (UART) operable to select one of the demodulated versions of the RF signal according to the selected protocol.

Abstract: A Sensor Web formed of a number of different sensor pods. Each of the sensor pods include a clock which is synchronized with a master clock so that all of the sensor pods in the Web have a synchronized clock. The synchronization is carried out by first using a coarse synchronization which takes less power, and subsequently carrying out a fine synchronization to make a fine sync of all the pods on the Web. After the synchronization, the pods ping their neighbors to determine which pods are listening and responded, and then only listen during time slots corresponding to those pods which respond.

Abstract: A method, implemented in a user equipment (UE), of maintaining base station synchronization, comprises receiving a measurement message from a radio network controller (RNC) directing the UE to measure a time difference of arrival (TDOA) between signals transmitted from a first and second base station. The UE receives a transmission from the first and second base stations and measures the TDOA of the transmission from the first and second base station. The UE transmits the measurement of the TDOA of the transmission from the first base station to the first base station, and the measurement of the TDOA of the transmission from the second base station to the second base station.

Abstract: Aspects of a method and system for low power IDLE signal transmission in Ethernet networks are provided. In this regard, during time periods between transmissions of actual data by a local Ethernet link partner, the local Ethernet Link partner may generate one or more signals, in place of a standard Ethernet IDLE signal, that enable synchronization between Ethernet link partners. In this manner, the generated signals may enable reducing power consumption as compared to standard Ethernet IDLE signals. Accordingly, link activity may be monitored to enable detecting periods when there may be no actual data for transmission and the generated signals may be transmitted. The generated signals may be transmitted at a reduced symbol rate as compared to standard Ethernet IDLE signals. The generated signals may be transmitted via fewer network links as compared to standard Ethernet IDLE signals.

Abstract: A system includes first and second wireless nodes having a clock with plural times, a wireless transceiver, and a processor cooperating with the transceiver to transmit and receive packets. The second node transceivers wirelessly communicate with the first or other second node transceivers. The second nodes include a Kalman filter with an output, plural filter gains, and an input representing the difference between: about the time of the clock when a received packet should have ideally been received, and a time when the received packet was actually received as measured by the clock. A circuit provides dynamic adjustment of the filter gains. The Kalman filter output estimates the difference between the time of the receiving node clock and a corresponding one of the times of the transmitting node clock. The second processor cooperates with the Kalman filter output to adjust the times of the receiving node clock.

Abstract: A device and method for time synchronization in a communication network, wherein a virtual clock is produced by a controller in each network node based on the PROFINET-Standard and/or the Precision Transparent Clock Protocol. In contrast to known methods for estimating the time, the time of the virtual clock does not undergo sudden changes. The virtual clock includes a controlled, continuous path. As a result, the virtual clock is particularly suitable for time-critical applications. Here, the estimation of the time of a reference clock is improved by 18-35%. Accordingly, a markedly greater number of network nodes may be synchronized with a predetermined level of accuracy for the time synchronization.

Abstract: A line current differential protection system that uses an external time reference continues providing protection to a power apparatus upon the loss of the external time reference. An external time reference synchronization mode and a channel based synchronization mode may be selectively applied on a per channel basis such that only those channels in the system that are not guaranteed to stay symmetrical use external time reference synchronization.

Abstract: A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

Abstract: A method and apparatus for switching, merging, and demerging data between data communication locations have been disclosed.

Abstract: A method, a related system, and recordable media adapted to store the method. The method controlling transmission frequency for first and second transmission signals exchanged between a host and an attached device using a serial advanced technology attachment (SATA) technology by detecting a first transmission frequency from a received first transmission signal, and controlling a second transmission frequency for a second transmission signal in relation to the detected first transmission frequency.

Abstract: A system for reducing electromagnetic interference and ground bounce in an information communication system includes a plurality of information communication devices. Each of the plurality of information communication devices is responsive to a respective information communication clock signal. Each information communication clock signal of each of the plurality of information communication devices is associated with a common reference clock signal. The system includes a phase controller. The phase controller is responsive to the common reference clock signal. The phase controller alters a phase of each information communication clock signal of each of the plurality of information communication devices by a predetermined amount.

Abstract: In the field of the broadcasting of digital services intended for terminals retrieving these services, the concern is with the problem of synchronisation in the context of a network transmitting on a single modulation frequency and the reliability of the broadcasting channel by redundancy of equipment. The present invention proposes a broadcasting system having a duplicated formatting module. This system enables a modulator to switch between the two streams generated by the two formatting modules without becoming desynchronised. These formatting modules are synchronised with each other in order to generate synchronised streams. Thus, when a modulator is caused to switch from a first stream generated by one of the formatting modules onto a second stream generated by a second formatting module, this switching can be effected without requiring a resynchronisation step.

Abstract: Provided is a method for measuring a neighbor cell signal in a portable terminal includes acquiring a minimum required quality level value and a threshold for an intra-frequency measurement from received system information; calculating a measured cell quality value after the acquiring step; and commencing a neighbor cell signal measurement for an intra-frequency cell reselection when a value acquired by subtracting the minimum required quality level value from the measured cell quality value is less than or equal to a value acquired by adding the threshold and a certain signal strength value over a certain time. In the neighbor cell signal measurement for the cell reselection, the unnecessary neighbor cell signal measurement can be avoided to reduce the power consumption and extend the battery lifetime.

Abstract: An apparatus including a transmit circuit, a receive circuit, and a control circuit. The control circuit may be configured to present a plurality of transmit data lanes in response to (i) a plurality of transmit data sources and (ii) a plurality of first skew control signals. The receive circuit may be configured to generate a plurality of receive data lanes in response to (i) the plurality of transmit data lanes and (ii) a plurality of second skew control signals. The control circuit may be configured to generate the first skew control signals and the second skew control signals in response to an alignment of the plurality of receive data lanes. The control circuit may adjust a timing of the receive data lanes and the transmit data lanes to achieve arrival of the receive data lanes across a transmission medium within a skew parameter.

Abstract: A baseband processing module includes TX processing components, a processor, memory, an RX interface, and a cell searcher module. The TX processing components receive outbound data, process the outbound data to produce a baseband TX signal, and output the baseband TX signal to a RF front end of the RF transceiver. The RX interface receives a baseband RX signal from the RF front end carrying a WCDMA signal. The cell searcher module receives the baseband RX signal, scans for WCDMA energy within the baseband RX signal, acquires slot synchronization to the WCDMA signal based upon correlation with a Primary Synchronization Channel (PSCH) of the WCDMA signal, acquires frame synchronization to, and identify a code group of, the WCDMA signal based upon correlation with a Secondary Synchronization Channel (SSCH) of the WCDMA signal, and identifies the scrambling code of the WCDMA signal based upon correlation with a Common Pilot Channel (CPICH) of the WCDMA signal.

Abstract: A method and apparatus for synchronizing timing of Access Points (APs) and/or Synchronization Units (SUs) includes (a) arranging a cable having at least four pairs of twisted wires connected between two or more fixed APs and/or SUs in a network; (b) assigning a first pair of the twisted wires to carry a positive D.C. voltage to at least one AP or SU; (C) assigning a second pair of the twisted wires to carry a negative D.C. voltage to at least one AP or SU; (d) providing to the first and second pairs of rails a series of synchronization pulses generated from a synchronization source and capacitively-coupled to the first and second pairs of twisted wires so as to supply a composite signal; and (e) reconstructing the generated synchronization pulses by detecting pulses on the positive and negative D.C. voltages at a receiving end by at least one AP or SU.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.

Abstract: A network device that arranges and transfers in an initial period of a cycle a synchronization frame that synchronizes network devices within a network includes: a cycle timer that measures a time within the cycle and a synchronization management unit that suspends frame transmission for a predetermined period till a start of the next cycle in each cycle, on the basis of information from a cycle timer.

Abstract: A communications system includes a wireless telephony network and a wireless Local Area Network (LAN), both accessible by a mobile communications device (16). To facilitate transitioning of the mobile communications device to the wireless LAN from the wireless telephony network, the wireless LAN includes a beacon transmitter, which generates a synchronization channel having a pattern unique to the wireless LAN. The Wireless LAN synchronization channel is received at a first receiver in the mobile communications device together with a synchronization channel from the wireless telephony. The wireless LAN synchronization channel enables the mobile communication device to synchronize with, for transitioning to, the wireless LAN.

Abstract: When the synchronization information, transmitted from a synchronization information output unit of a clock master side device, is detected by a synchronization information detection unit, the clock slave side device associates the synchronization information with the timestamp information at the time of detection of the synchronization information. Based on the timestamp information associated with the currently received synchronization information, the timestamp information associated with at least one synchronization information up to the synchronization information received last time and transmission period information of the synchronization information, a calculation/decision unit decides whether or not a predetermined condition is met. When the condition is met, the calculation/decision unit supplies the currently received synchronization information to a clock synchronization technique function unit.

Abstract: A parallel processing-based time synchronization apparatus is disclosed. The time synchronization apparatus employs a double-filter structure based on parallel processing, thereby providing more precise and reliable time synchronization between a master device and a slave device.

Abstract: A method and a communication modem for broadband communication over power transmission lines. The modem includes a coarse level synchronization mapping unit which maintains a regularly updated coarse level clock synchronization map of neighboring communication units with which it is likely to exchange communications; and a second level synchronization unit which utilizes session handshakes and session data capacity to increase the synchronization level with a neighboring communication unit to allow a communication session to be held at a higher modulation level than the coarse level synchronization is able to support.

Abstract: A wireless access terminal, system and method for the wireless access terminal to synchronize to system times in a wireless communication system. A first timing hierarchy in a first wireless communication network is used to operate the wireless access terminal. The first wireless communication network has a first radio access technology. Operating with the first timing hierarchy includes determining a frame cycle for the first wireless communication network. The frame cycle has a frame cycle boundary. Broadcast parameters for a second wireless communication network having a second radio access technology different from the first radio access technology are received. The broadcast parameters include the system time of the second wireless communication network. The system time of second wireless communication network is aligned, from the perspective of the wireless access terminal, with the frame cycle boundary.

Abstract: In certain aspects, the present disclosure is related to devices, methods, systems and/or computer-readable media for use in an isochronous media network in which media devices connected to a network employ one or more synchronization signal to regulate or facilitate the transmission of media signals through the network. In certain aspects, the present disclosure is also related to devices, methods, systems and/or computer-readable media for use in a larger unified, or substantially unified, isochronous network created from aggregating local isochronous media networks in which media devices connected to a network employ a one or more synchronisation signal distributed from a local master clock to regulate or facilitate the transmission of media signals.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: A system for synchronizing clock, which is used to realize the synchronization between a radio frequency module and a base band module in a base station, comprises: one or more time generators, located on the radio frequency module side, configured to generate a synchronous signal according to an external clock signal, and to send the synchronous signal to a time distributor; the time distributor, located on the base band module side, configured to generate a synchronous clock according to a synchronous signal from one of the one or more time generators, and to adjust the synchronous clock according to a communication delay between the time generator which outputs the synchronous signal and the time distributor, and to send the synchronous clock adjusted to the radio frequency module and the base band module to realize the synchronization between the radio frequency module and the base band module.

Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

Abstract: A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.

Abstract: A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

Abstract: Provided is a network synchronization method and apparatus for performing a time synchronization between nodes. When a system starts up and the time synchronization between the nodes is initiated, the network synchronization method and apparatus may enhance jitter, wander, and a time synchronization performance by gradually increasing a window size for a propagation time measurement. When a full window of propagation time measurements is collected, the network synchronization method and apparatus may enhance jitter, wander, and the time synchronization performance by applying an exponential to a computation of an average propagation time value.

Abstract: Disclosed embodiments include a method for establishing a wireless communication session between a base station unit and a mobile unit wherein a system controller determines which base station unit of multiple base station units is an optimal base station unit to establish the session. The method includes the system controller receiving commands from each of multiple BSUs that have received a request for wireless service from a mobile unit. The commands include information, such as a unique identifier for the sending BSU, signal strength information for the sending BSU, and channel availability for the sending BSU. The system controller directs the optimal BSU to respond to the request, and directs every other BSU to ignore the request. In at least one embodiment, Bluetooth commands are used.

Abstract: There is disclosed a clock regeneration circuit having a PCR buffer including a register which buffers a PCR extracted from a transmission signal, a counter which counts a reception side reference clock CKr, an STC buffer including a register which buffers a counted value of the counter, and a CPU which generates a signal indicating a difference between a transmission side reference clock and the reception side reference clock CKr based on values held in the PCR buffer and the STC buffer. If, at this point, a new PCR is input before the values held in the PCR buffer and the STC buffer are read by the CPU, the PCR buffer and the STC buffer are not updated.

Abstract: Described is circuitry for improving the acquisition/locking time of phase-locked loops (PLL). The circuitry includes a node for tapping voltage from a PLL, with an analog-to-digital converter (ADC) to convert the voltage to a digital signal. A memory module stores the digital signal. A digital-to-analog converter (DAC) converts the digital signal to an analog output. A comparator/threshold detector is included to compare the voltage from the node to the analog signal from the DAC. Based on the comparison, the comparator/threshold detector provides a signal to the memory module to cause the memory module to update its stored digital signal. Upon power-up, the saved voltage is forced into the PLL to force the PLL nodes to the saved values as an initial condition, thereby decreasing acquisition time in the phased locked loop.

Abstract: A system for synchronizing a spreading sequence transmitted during a plurality of time slots includes a plurality of communication stations. Each communication station includes: (a) a control unit; (b) a spreading sequence unit for originating the spreading sequence; (c) at least one of a transmitter and a receiver; (d) at least one delay unit responding to the control unit for imparting a first delay to the spreading sequence presented to the transmitter unit and responding to the receiver unit for imparting a second delay to the spreading sequence presented to the receiver unit; and (e) a synchronizing sequence generator coupled with the transmitter unit. The synchronizing sequence unit in a first station presents a synchronizing sequence for transmission accompanying spread information transmitted during selected time slots. A receiver unit in a second station employs the synchronizing sequence in cooperation with the spreading sequence for despreading received spread information.

Abstract: An audio network system that performs transport of audio signals among nodes by cascading a plurality of nodes each including two sets of transmission I/Fs and reception I/Fs, and circulating among the nodes in each fixed period an audio transport frame generated by a master node, the audio transport frame including a plurality of storage regions for audio signals, is configured such that the master node measures time periods Dfw and Dbw after the audio transport frame is transmitted until the audio transport frame returns to the master node after passing through the transmission route and writes them into the audio transport frame, and each of the other nodes generates a signal processing wordclock based on those time periods, two reception times Tr1 and Tr2 while the audio transport frame circulates once through the transmission route, and a predetermined target time Tt.

Abstract: A method and circuit for providing coherent phase noise including a clock receiver to receive a clock signal generated external to the circuit and a local clock source arranged on the circuit. The circuit further includes a selector to select an output of one of the clock receiver and the local clock source and a wireless transceiver responsive to an output of the selector.