Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: A communications system includes a first oscillator for producing a first clock signal; a second oscillator for producing a second clock signal; and a secondary circuit coupled to the first oscillator and the second oscillator for determining a second oscillation frequency corresponding to a frequency of the second clock signal; the second oscillation signal being determined according to the first clock signal, the second clock signal, and a first oscillation frequency corresponding to a frequency of the first clock signal.

Abstract: An apparatus for managing modem sample rates within a direct access arrangement (DAA) circuit is disclosed. The DAA circuit includes a serial audio interface for providing communications between the DAA circuit and a host computer system. The serial audio interface is capable of operating under multiple serial communication interface standards, such as the AC '97 standard and the HD Audio standard. The DAA circuit also includes means for configuring the serial audio interface to transmit and receive modem samples at an audio sample rate higher than a modem sample rate of modem samples and at a predetermined bit size that is wider than a bit size of the modem samples, such that one bit of each of the modem samples is utilized to indicate the validity of each associated modem samples.

Abstract: A method of synchronizing multi-carrier systems is provided, wherein the method comprises inserting a predefined frequency domain signal into a signal on a transmitter side of a multi-carrier system and multi-carrier modulating the signal. Furthermore, the method comprises transmitting the multi-carrier modulated signal via a carrier channel to a receiving side of the multi-carrier system, and synchronizing the multi-carrier modulated signal by using the predefined frequency domain signal portion of the multi-carrier modulated signal.

Abstract: Systems and methods are described for supporting synchronization status messages (SSM) on building integrated timing system synchronization supply unit (BITS-SSU) remote shelves. A method includes providing a composite clock reference to a remote synchronization supply unit from a master synchronization supply unit; providing a synchronization status message to the remote synchronization supply unit; relaying the composite clock reference from the remote synchronization supply unit; and relaying the synchronization status message from the remote synchronization supply unit.

Abstract: In one embodiment, an electronic system comprises a first backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the first backplane, wherein the first backplane comprises a first clock module for generating the timing signals, a second backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the second backplane, wherein the second backplane comprises a second clock module for generating the timing signals, and an electrical connector coupling the first clock module to the second clock module for communication of a timing signal, wherein the first clock module comprises a circuit for detecting the presence of the electrical connector, the first clock module providing the timing signal to an output port coupled to the electrical connector in response to the circuit, and the second clock module synchronizes to the timing signal communicated via the electrical connector.

Abstract: The present invention is a system and method for enabling multicast synchronization of initially unicasted content. Multiple unicast streams are synchronized in order to convert the unicast streams into a multicast stream. Each unicast stream may be accelerated or slowed down in relation to a reference stream to a common point within each stream upon which the unicast streams are replaced by a multicast stream of the same content.

Abstract: Methods of controlling activation of electrical appliances can include reducing overlapping activation time of different electrical appliances located at a single customer location of an electrical service provider during at least one time interval during a day. Related systems, circuits, and computer program products are disclosed.

Abstract: A method and circuit for precisely synchronizing clocks in separate nodes on a communication network is provided by adjusting timestamps and related data in network messages. The circuit will allow a daisy-chain connection of the nodes and will forward time synchronization frames while accounting for delays in a manner that does not use boundary clocks, but does not depart from the IEEE 1588 standard protocol. The delays will be added on the fly to synchronization packets and the IP checksum and frame CRC will be adjusted. Deterministic data delivery and redundant data paths are also provided in a full duplex Ethernet network.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: A rake receiver for DS-CDMA UWB system and a DS-CDMA receiver having the same are provided. The rake receiver includes: a channel estimator for estimating a channel having a predetermined chip duration by using a synchronization acquisition sequence; a tracking module for detecting a channel variation and adjusting a synchronization position value when the channel variation is detected; a first switch for selecting one of an output value of an analog-to-digital converter and an output value of a correlator and outputting the selected value; a second switch for selecting one of the output value of the analog-to-digital converter and the output value of the correlator; and a plurality of demodulators having a parallel processing structure to demodulate received signals by using the channel estimation value inputted from the channel estimator, the synchronization position value stored by the tracking module, and an output value of the second switch.

Abstract: A multistation communication apparatus in which each of a plurality of primary stations (21) is connected to a plurality of secondary stations (91) by a communication channel for each primary station and the transmission from the primary stations (21) to the secondary stations (91) is performed by 1:1. The apparatus can arbitrarily vary a control period for each of the secondary stations connected to the primary stations and also enables the synchronization between the primary stations. The primary stations (21) have means for writing a transmission start flag (721) for starting transmission for each of transmission buffers (31s) corresponding to the secondary stations (91) and means for using a transmission start control signal (7611) of another transmission buffer. Furthermore, the primary stations (21) have means for matching the transmission start timing based on their own transmission start flags with the transmission start timing when synchronized with the another transmission buffer.

Abstract: A clock signal generating section generates a clock signal of a predetermined frequency. A frequency spreading section spreads the frequency of the clock signal generated by the clock signal generating section based on a predetermined spread ratio. A controlling section sets the spread ratio of the frequency spreading section in accordance with a used state of a serial communication device and a parallel communication device. The clock signal controlling device having the above arrangement enables to suppress an electromagnetic wave emitted from an electronic device, and to keep a computation processing speed in the electronic device, and an operation speed of the electronic device from unduly lowering.

Abstract: Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

Abstract: A communication apparatus (400) capable of supporting two bidirectional communication protocols is connected to a single bidirectional signal line and a controller (414). Software processes of the controller (414) include only processes of requesting transmission, setting transmission data, and decoding reception data. All communication processes, such as generation of a waveform during transmission, sampling of data during reception, decoding of a reception address, and the like, are hardware processes of the communication apparatus (400). In accordance with a control of a state determining circuit (405), the generation of a waveform during transmission is controlled by a transmission control circuit (409) and a data output circuit (111), while the sampling of data during reception and the decoding of a reception address are controlled by a waveform timing check circuit (407) and a reception control circuit (410).

Abstract: The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Abstract: A first communication apparatus receives, from a second communication apparatus, information indicating the number of relays from a first supplying apparatus to the second communication apparatus. The first communication apparatus receives, from a third communication apparatus, information indicating the number of relays from a second supplying apparatus to the third communication apparatus. The first communication apparatus transmits, to the third communication apparatus, information indicating the number of relays from the first supplying apparatus to the first communication apparatus. The first communication apparatus transmits, to the second communication apparatus, information indicating the number of relays from the second supplying apparatus to the first communication apparatus. The first communication apparatus selects the second communication apparatus, which has a smaller number of relays among the second and the third communication apparatuses.

Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

Abstract: The invention relates to a network operating on a time triggered protocol using time slots, wherein at least two clusters are included in the network, each cluster includes at least a node. Further, it relates to a method for clock synchronization within a time triggered network.

Abstract: A communication control apparatus includes a signal receiver for receiving a state variable signal indicating a timing of data transmission from a neighboring node. The apparatus also includes a calculator for forming a communication timing, by varying plural phase signals different in oscillation period in response to the state variable signal, synchronizing respective states of the phase signals so that they interact with each other, and temporally multiplexing plural data transmission periods different in time slot width and representing a transmission time period between its own node and the neighboring node based on respective oscillation periods of the phase signals. The calculator includes a state manager for managing states of phase signals for the own node and the neighboring node different in oscillation period, and prescribing an order relationship of time-slot allocation.

Abstract: A communication timing control apparatus for use in the nodes of a communication system includes a signal communication unit that transmits a state variable signal to neighboring nodes and receives state variable signals from those nodes. An external control signal, such as a beacon signal transmitted by a control node, is also received. The state variable signals indicate internal operating states or timings of the nodes; the control signal indicates a basic transition rate. A timing decision unit causes internal state or timing transitions to occur at timings responsive to the basic transition rate and the received state variable signals, adjusting the transition timings so as to avoid signal collisions and to adapt to changing system conditions, Use of the control signal enables a steady timing state to be reached quickly.

Abstract: A packet switched communications system and method for transmitting synchronous data from a source module (4) to a terminating module (8) over a network comprising plurality of modules (4, 5, 7, 8) interconnected via transmission links (2, 6, 9). Each module operates with a clock of nominal frequency that is not synchronized with the clocks of the other module(s) and has a single input and one or more outputs. The method includes determining the phase difference between the input clock and the output clock of each module, and transmitting the phase difference to the terminating module (8) in the network. The received accumulated phase difference at the terminating module (8) is used to lock the output clock at the terminating module to the input clock at the source module.

Abstract: An embodiment is a receiver for a communications system that may substantially block unwanted signals in a frequency range to protect the receiver from overload. Simultaneously, the receiver of an embodiment substantially passes a desired signal so that its information may be processed by the, for example, communications system of which the receiver is part.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

Abstract: Systems and methods are described for carrier phase synchronization for improved AM and TV broadcast reception. A method includes synchronizing the phase of a carrier frequency of a broadcast signal with the phase of a remote reference frequency. An apparatus includes a receiver to detect the phase of a reference signal; a phase comparator coupled to the reference signal-phase receiver; a voltage controlled oscillator coupled to the phase comparator; and a phase-controlled radio frequency output coupled to the voltage controlled oscillator.

Abstract: An apparatus for maintaining synchronization with a plurality of asynchronous communication links includes a first counter that generates a first local network clock, and a second counter that generates a second local network clock. The apparatus also includes an offset controller coupled with the first counter and coupled with the second counter, the offset controller configured to load a current network clock value of a first network clock of a first communication link into the first counter, and to load a current network clock value of a second network clock of a second communication link into the second counter. The apparatus further includes a drift controller coupled with the first counter and with the second counter, the drift controller configured to correct a drift between the first local network clock and the first network clock and to correct a drift between the second local network clock and the second network clock.

Abstract: When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: An intermittent operative communication apparatus can send data, received from a source communication device, to any receiver communication device at a predetermined interval and wait for receiving data at the predetermined interval. The communication apparatus has a selector for selecting one or multiple receiver communication devices as a reference communication device that gives a reference timing at which the communication apparatus waits for receiving data, and a timing controller for setting a timing, at which the communication apparatus waits for receiving data, to a timing according to operation of any reference communication device.

Abstract: A system and method for determining a common time base among nodes in a network by iteratively propagating timing constraints among the nodes, and determining a time-shift to apply to the time base of each node that conforms to these constraints. “Trace” files record the time of transmission or reception of packets at each node, based on the time base at the node. A fundamental constraint in a common time-based system is that the time of reception of a packet at a destination node cannot be prior to the time of transmission of the packet from a source node. A further constraint in a common time-based system is that the time of reacting to an event cannot be prior to the time of the event.

Abstract: An information processing apparatus and method, a recording medium, and a program for removing jitter and reducing the delay of the information processing system. A substantial error is produced between accumulated value of intervals of reception time of the packets and accumulated value of time stamps of these packets. For each number of transport stream packets on which this substantial error provides one clock, a time equivalent to one clock is added to the subsequent time stamps of the transport stream packets or this time is subtracted therefrom to adjust time stamp, thereby correcting the deviation in time from reception time of the transport stream packets.

Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Disclosed is a time-synchronization algorithm for use among disparate systems, such as between a controller system and a system having one or more application workstations. In an embodiment of the invention, the workstation system acts as a master timekeeper, ensuring that the time stored in the controller system is in synchrony with the time kept by the workstation system. In a further embodiment of the invention, the time-synchronization system provides staggered time-synchronization signals from each of two or more workstations for receipt by the controller system. The controller system sets its local time by resetting the time for each such incoming synchronization signal. In a further embodiment of the invention, each of two or more workstations employs a technique for evaluating the error accumulated in the controller's time clock and transmits a time-synchronization message in response to finding that the accumulated error has exceeded a predetermined acceptable error threshold.

Abstract: A method includes determining a network counter value indicative of a network clock time of a system at a first time instant and a second time instant occurring later in time than the first time instant. The method further includes determining an audio counter value indicative of an audio clock time of the system at a third time instant occurring the first and second time instants and a fourth time instant occurring later in time than the second time instant. The method further includes determining an offset based upon the determined network counter values and the audio counter values. The method further includes adjusting the audio clock time based upon the determined offset to synchronize operation of at least one audio component operating according to the audio clock with at least one audio component operating according to the network clock. An associated system is also disclosed.

Abstract: A slave radio station establishes communization with a master radio station by transmitting a signal intermittently, listening for a response, and saving power by deactivating its transmitter and receiver at other times. When the master radio station responds, the slave station may synchronize periods of receiver activation with a beacon signal transmitted periodically by the master station and may cease transmission of the intermittent signal.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Abstract: A method for time synchronization of a number of measuring computers cooperating over a telecommunications network includes providing a number of time sources associated with one of the measuring computers. Each of the time sources has a different accuracy and can provide a time stamp. Using the first measuring computer, one of the time sources is selected as a function of the accuracy of the time source.

Abstract: A system and method for providing wireless synchronized operation of electronic article surveillance (EAS) systems are provided. The method may include communicating wirelessly between each of a plurality of controllers connected to a plurality of detectors of the plurality of EAS systems and receiving with a communications receiver of each of the controllers wireless communications from at least some of the other plurality of controllers. The communications receiver may be separate from a tag detection receiver.

Abstract: A method and system to synchronize a first device and a second device includes generating a first tone by the first device, the first tone one of including an identity of the second device and generated at a predefined time, receiving the first tone by the second device, setting a clock of the second device based on the received first time, and sending an acknowledgment by the second device to the first device.

Abstract: A mobile communication system having a radio controller for transmitting the same information to a mobile station via a plurality of radio links is disclosed. In the system, the mobile station includes an selecting unit for selecting at least one of receiving capability or receiving quality, and a transmitting unit for transmitting the selected information. The radio controller includes a receiving unit for receiving from the mobile station at least one of the receiving capability or reception quality, and a transmission timing controller for controlling transmission timing based on the received information from the mobile station.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: For signals to be transmitted through a signal transmission path constituted by a relay device group for relay for each set of a plurality of channels, a timing adjustment unit is provided in both or one of a receiver-side LSI and a transmitter-side LSI for each set of a plurality of channels transmitted through the relay device group for relay so that the signals can be transmitted with accurate timing. In addition, the timing adjustment unit can adjust the timing for signals transmitted through each relay device group, the timing in one receiver-side LSI in signal transmission through a plurality of relay device groups, and the timing in one-to-many signal transmission in which signals are transmitted from one transmitter-side LSI to a plurality of receiver-side LSIs.

Abstract: A method and a device are proposed for the synchronization of a radio transmitter and a radio receiver, notably for UMTS, while utilizing a Golay correlator, which synchronization should be performed reliably without imposing severe requirements as regards the frequency stability of the local oscillator. To this end, absolute value squaring B1, B2 is performed in the Golay correlator already prior to the last delay stages (D7, D8).

Abstract: A wireless clock system includes a master clock or other master time source, and a plurality of slave clocks or repeater devices. Each slave clock can both wirelessly receive and wirelessly transmit time signals including current time data. To avoid conflicts among the slave clocks, each slave clock transmits time signals in a frequency-hopping manner over pseudo-randomized frequencies and at pseudo-randomized transmission start times. In another embodiment, power consumption at the slave clocks is minimized by activating and deactivating receivers within the slave clocks at predetermined times and at predetermined intervals, each interval being longer than the previous interval, until valid time signals are received from either the master clock or another slave clock. Calibration of the slave clock's time base is also performed.

Abstract: Communicating nodes in a network exchange state variable signals indicating the timing of periodic operations performed at the nodes. Each node autonomously controls the timing of its periodic operation so as to distance the timing from the timing of the periodic operations performed at other nodes. If the periodic operations include data transmission, this arrangement enables the nodes to avoid data collisions. The nodes can also adapt autonomously to changing conditions such as changing priority levels and the addition and removal of nodes.

Abstract: Phase-error combination methods for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving phase error information with respect to each channel; combining the received phase error information and generating a combined phase error; and applying the combined phase error to at least one channel phase locked loop. Error signal combination comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combining the received error signal information and generating a combined error signal, weighting the received error signal information from each channel, for example with reliability information. The combined, weighted error signal is applied to at least one channel phase locked loop.

Abstract: A method and system of applying modulated carrier signals to tree networks and processing signals tapped from the tree networks to generate output signals with phase-synchronized carriers are disclosed.

Abstract: The present invention provides a robust global timing resynchronization architecture, a multi-link communications system including the same, and a method for minimizing the effects of resynchronization signal skew, reference clock skew, and PLL static phase error variations on resynchronization of multi-link communications systems.

Abstract: Methods and an arrangement for synchronizing communication of framed data via asynchronous base stations (BS1, BS2) in a cellular communication system are presented. The synchronization methods are performed continuously by sending out certain system frame counter states from a central node in the system to all its connected base stations (BS1, BS2). Each base station (BS1, BS2) includes a local frame counter (LFCBS1, LFCBS2), which generates local frame counter states (t1(1)-t1(4), t2(1)-t2(4)) correlated to the system frame counter states. Transmission of information via the base stations (BS1, BS2) is synchronized by assigning each data frame (DR(1)-DR(4)) a particular frame number, which is given by the local frame counter states (t1(1)-t1(4), t2(1)-t2(4)), so that data framed (DF(1)-DF (4)) having identical numbers contain copies of a certain data packet.