Abstract: A current-mode differential signal transmitting circuit is disclosed, including a transmitter having a first transmitting module and a second transmitting module. The first transmitting module includes a plurality of first outputting units to output first data and a clock outputting signal. The second transmitting module includes a plurality of second outputting units for outputting second data, and the first and second transmitting modules share this clock outputting unit.

Abstract: A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management system in the receiving device then uses this information to adjust event information once the event is received.

Abstract: Output clock adjustment for a digital I/O between physical layer devices and media access controller. A method is disclosed for transferring data received on the input of a physical layer device from a transmission medium to an output associated with the physical layer device and to a media independent layer, the transferred data associated with transferred timing information from the physical layer device to the media independent layer. A receive clock is generated and then the data transitions in the received data are synchronized to at least one edge of the receive clock to provide synchronized receive data. The synchronized received data is then transmitted to the media independent layer. The generated receive clock is delayed by a predetermined clock delay to provide a delayed receive clock, and wherein the data transitions in the synchronized receive data is positioned relative to the rising edge of the delayed receive clock at a predetermined position therein following the rising edge thereof.

Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Abstract: Method and apparatus for synchronizing base stations employing an independent synchronizing source or identifying a base station as a master source. An RNC (C-RNC) or a base station may designate one base station or a UE to acquire measurements derived from base stations to achieve synchronization. Synchronization activities may be regularly scheduled or may be undertaken when periodic measurements indicate that a drift value exceeds a given threshold.

Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.

Abstract: A transceiver apparatus and a method comprise detecting means for detecting messages, wherein the detecting means comprises a first detector arranged to operate over a first detection period and which output indicates the beginning of a message with a first detection probability, and a second detector arranged to operate over a second detection period and which output indicates the detection of the beginning of a message with a second detection probability. The second detection probability is higher than the first detection probability and the transceiver apparatus is arranged to receive the message if the second detector indicates detection of the beginning of a message.

Abstract: Network timing is derived from the PSTN and distributed through the network to gateways capable of deriving timing from the incoming UDP stream. The derived timing has the correct frequency for voice telephony without using external timing sources or extraneous hardware components. For example, a digital signal processor (DSP) can derive the timing from a timed TDM bus and distribute messages, such as IP messages, to other gateways or port networks. The other gateways and port networks use the incoming stream to extract the timing which is then used to time their TDM bus. The port networks and gateways can also distribute other streams to other gateways in a fan-out type of arrangement. This internally generated timing can be used, for example, for Circuit Emulated Services (CES).

Abstract: Data is synchronized between a mobile device and a computing device over a wireless link. Synchronization operations are scheduled according to a synchronization schedule that is based on a current time of day.

Abstract: Systems, device and methods are provided for determining a reference clock frequency for use by a multi-protocol analyzer in connection with a multi-protocol communications system. Initially, the clock frequencies for each of the links in the multi-protocol communications system are determined. The link clock frequencies are then used as a basis for determining the frequency of the reference clock. While the reference clock frequency is based upon the link clock frequencies, the reference clock frequency is different from each of the reference clock frequencies.

Abstract: A system and method for aligning a local timebase to a remote timebase given a timebase error value from a higher-level protocol, and using the aligned timebases to generate and distribute synchronized events and synchronized adjustable frequency periodic signals across a domain using the aligned timebases. Slightly speeding up or slowing down a periodic signal used to count time, a local timebase may be aligned to a remote timebase when given an error value from a higher-level protocol. A device may be configured to begin generating a periodic waveform at an agreed upon time in the future, once the timebases are aligned, where the time may be synchronized to remote devices via a synchronization protocol and an alignment mechanism. Remote periodic signals may remain synchronized to each other as long as the higher-level protocol and timebase alignment algorithm keep the timebases aligned.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: A system for bi-directional power distribution line communication. The system is configured for data communication with an endpoint transceiver located at a customer premise. The system comprises a time server in electrical communication with the transceiver, the time server configured to retrieve the time. A substation controller is in electrical communication with a power distribution line. The substation controller includes a transceiver and a programmable circuit. The programmable circuit includes a substation clock. The programmable circuit is programmed to periodically retrieve the time from the time server to calibrate the substation clock to the retrieved time, and to control the transceiver to transmit the time to the endpoint transceiver.

Abstract: Provided is a data delivery system including a transmitter which transmits data stream via a network, and a receiver which receives the data stream and stores it into a reception buffer thereof, and decodes the stored data stream. The network has predetermined therein a necessary amount of data stored in the reception buffer for decoding the received data stream continuously irrespectively of a variation of a time taken for data transfer from the transmitter to the receiver. The receiver starts, after reception of the latter and before the data has been stored up to the predetermined necessary stored amount, decoding of the data stream at a rate lower than assumed at the time of data encoding at the transmitter. When the data has been stored into the reception buffer up to the predetermined necessary stored amount, the receiver changes the decoding data to the assumed rate for decoding further data.

Abstract: Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The sync byte reference time is multiplied by the message data size to determine the data budget.

Abstract: A synchronization circuit includes a first flip-flop circuit to hold an input signal which is asynchronous to a clock signal by the clock signal, and output an output signal, a second flip-flop circuit to hold the input signal by a signal of an opposite phase to the clock signal and output a signal, a comparing unit to compare the input signal and the output signal of the first flip-flop circuit and output a signal with a high or low level depending on whether the input signal and the output signal of the first flip-flop circuit have the same level, a selection unit to select one of the output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit depending on the level of the signal outputted by the comparing unit, and a third flip-flop circuit to output the output signal selected by the selection unit.

Abstract: A supply voltage is provided in an integrated circuit by retrieving an indicator from a storage device and generating a supply voltage for use by the integrated circuit, the supply voltage being regulated responsive to the indicator being in a first state and unregulated responsive to the indicator being in a second state. Alternatively or additionally, an external voltage provided to the integrated circuit is compared with a threshold. The supply voltage is regulated responsive to the external voltage exceeding the threshold level and unregulated responsive to the external voltage falling below the threshold level.

Abstract: According to one embodiment, a high speed serializer for multiplexing 2N data inputs, N being a positive integer, comprises one less than 2N multiplexing cells arranged in N stages. The stages are numbered 1 through N, and the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs. Each stage comprises half as many multiplexing cells as the preceding stage. Additionally, each multiplexing cell comprises a multiplexer that comprises a pair of inputs and an output. 2N-2 of the multiplexing cells in the first stage further comprise a latch, and the output of the latch is coupled to an input of the multiplexer.

Abstract: A method and apparatus for recovery from discontinuous reception desynchronization, the method having the steps of: determining a most recent time that an explicit message indicating a change from an old discontinuous reception period to a new discontinuous reception period was sent; adding to the most recent time that the explicit message was sent the old discontinuous reception period multiplied by an integer, where the integer is selected to ensure the results of the adding step occur after a present time; and sending a continuous reception command at the time found in the adding step.

Abstract: A receiving device (50) is provided to allow appropriate clock regeneration even for a VBR TS when a stream including video and audio data, such as an MPEG2 TS, is transmitted or received in real time through a network having jitter. When the received packet data is stored in a memory (53) and the packet data is output in accordance with time information added to the received packet data, a clock frequency deviation between a sending device and a receiving device is calculated on the basis of the integration result of the amount of the received packets temporarily stored in the memory (53), the number of the received packets which have been processed, and the measurement result of the integration time used for integrating the amount of the received packets. A read timing offset of the received packet is obtained on the basis of the calculation result of the clock frequency deviation.

Abstract: An apparatus for and method of deciding symbols in a M-ary phase shift keying (MPSK) system are provided. The apparatus includes: a linear transform unit performing linear transform, to which a phase error is applied, of a received pair of symbols; and a symbol decision unit deciding a transmitted symbol corresponding to the received pair of symbols according to the sign value of the transformed symbol pair. According to the apparatus and method, degradation of a symbol error rate caused by a phase error when an MPSK signal is demodulated can be improved and a phase error can be estimated through a simple method.

Abstract: An efficient synchronization procedure applicable to mesh WLAN based on the 802.11s standard is proposed. A first and second stations initiate the process and establish a communication link between them. Next, the first station transmits to the second station a synchronization element that contains: a capability information element indicative of a capability of the first station to synchronize, and a status information element indicative of whether the first station has established a synchronized peer link with another station. One of the two stations may then initiate the actual handshake for synchronization. The initiator transmits a request for synchronization and receives a response from the other station representative of the acceptance by the other station of the synchronization, the request and the acceptance being restrained in that the stations may not entertain conflicting synchronization procedures with different links. The request may include a set of the synchronization profile.

Abstract: The present invention describes a method and a system for executing preamble detection, symbol timing recovery, and frequency offset estimation that are applied to a PHS system for executing the preamble symbol detection and timing recovery. The system includes a first absolute value circuit, an average circuit, a multiplier, a sample and accumulate circuit coupled to the multiplier, a second absolute value circuit, a first compare circuit, and a second compare circuit, such that the system with the foregoing structure can detect a preamble symbol by less symbols while performing a timing recovery. The invention also describes a frequency offset computation method and its circuit.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: A method employing an improved rate-matching algorithm used during transmission and reception of information packets involves performance of a complete process of puncturing or repetition in two steps. In the first step the action to be taken on each bit of the input register is calculated and is stored in the form of flag bits in flag register. In step 2, puncturing/repetition are performed on input bits and the output is stored in output register. Input bits can be processed in groups in step 2, reducing the number of steps required in the complete rate matching process.

Abstract: Two or more local-oscillator-equipped instruments connected to a network are disclosed. Among the instruments, one instrument is designated as the master instrument and the rest, slave instruments. A master clock signal generated by the local oscillator of the master instrument is used by the slave instruments, through the network, to discipline their own local oscillators to generate slave clock signals that are synchronized to the master clock signal. In one embodiment, in the slave instrument, the master clock signal from the master instrument is used as a reference to generate slave clock signals. In another embodiment, the phases of the slave clock signals are adjusted to compensate for the phase difference between the slave clock signals and the master clock signal.

Abstract: A semiconductor integrated circuit includes an oscillation circuit for generating multiple clocks of mutually different phases, and is also characterized in selecting a single clock FCLK_P from among multiple clocks FCLK_P [n-1:0] for use in transmitting IQ Serial transmission signals and, utilizing the FCLK_P to transmit an IQ Serial transmission signal.

Abstract: Systems and methods for converting a data stream from a first sample rate to a second sample rate, where the data is received in bursts. In one embodiment, a method includes receiving bursty audio data on a first input line and receiving synchronization data on a second input line that is separate from the first input line. An input sample rate is then estimated for the received audio data based on the received synchronization data and the audio data is converted to an output sample rate. The input sample rate is determined by counting samples received in a time interval and potentially low-pass filtering the result. The audio data may be in packetized, parallel, or other forms, and the synchronization data may include individual signals, such as pulses or bits received at regular or irregular intervals.

Abstract: A method of establishing and updating a master node in a computer network by scoring each node in the network as a function of its physical attributes, designating the highest scoring node as the master node, sending a periodic message by the master node with its score and a request for non-master node scores, sending a message by a non-master node to the master node requesting relinquishment of master node status if the non-master node has a higher score, relinquishing master node status to a non-master node with a higher score and returning to the third step, and declaring by a non-master node that it is a master node if it has not received a message from the previously designated master node in a user-definable period of time and returning to the third step.

Abstract: An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.

Abstract: A system and method that allows a user to concurrently connect to multiple wireless networks with a single network interface card is presented. The networks may be infrastructure (“IS”) networks and ad hoc (“AH”) networks. A driver is inserted into a device's networking stack and exposes a plurality of virtual wireless network adapters, one for each network. The adapters are enabled and disabled in accordance with which network is presently activated. Packets for a network are queued when the network is not enabled. The wireless driver controls the switching of the network card. In one embodiment where multiple wireless cards are switching in and out of AH networks, the method converges the switching times for the cards in an AH network to ensure concurrent connectivity in the AH network for at least a brief time period every switching cycle of the wireless cards.

Abstract: Described is a system and method for establishing a wireless connection between wireless devices. The method comprises obtaining data of a corresponding computing device. The device conducts wireless communications using a predetermined wireless protocol. The obtained data is processed to generate a wireless address of the device and a first message is transmitted to the device for establishing a wireless connection. The first message is addressed to the wireless address. When a first response message is received from the device, a second message is transmitted to the device. The first response message is generated in response to the first message and includes the wireless address. The second message includes synchronization data. When a second response message is received from the device, the wireless connection is established with the device. The second response message is generated in response to the second message.

Abstract: A communication device with digital and analog circuits mixedly mounted thereon, for which the influence of noise generated in its interface part on the analog circuit part can be reduced, which does not interfere with the downsizing of the communication device. The communication device has a communication part, such as semiconductor communication device, and a control part, such as a semiconductor control device operable to control the communication part. The communication part and control part are operated in asynchronization with each other. The communication part includes an analog circuit. The interface circuit of the communication part, which is interfaced with the control part, receives a clock signal supplied from the communication part and conducts a synchronous interface. The control part stops supplying the clock signal during the time when the communication part operates the analog circuit.

Abstract: Inter-carrier interference (ICI) in a kth sub-carrier of an orthogonal frequency division multiplexing (OFDM) signal received at time t is reduced, wherein the received OFDM signal comprises a plurality of sub-carriers. This is achieved by generating a self-interference term, ICIk?L,k?L, for a signal received on sub-carrier k?L, wherein L ? [ . . . , ?3,?2,?1,1,2,3, . . . ], and wherein the self-interference term is an estimate of the data received at time t on the sub-carrier k?L, weighted by a rate of change of the channel through which sub-carrier k?L passes at time t. An ICI cancellation coefficient, GL is obtained, and an estimated ICI term is generated by adjusting the self-interference term, ICIk?L,k?L, by an amount based on the ICI cancellation coefficient, GL. The estimated ICI term is then subtracted from a term representing a signal received on the kth sub-carrier at time t.

Abstract: A wireless communication system is described that generates FDFR transmissions with any number of transmit and receive antennas through flat-fading channels and frequency- or time-selective channels. In particular, the system utilizes layer-specific linear complex-field (LCF) coding with a circular form of layered space-time (ST) multiplexing to achieve FDFR wireless communications with any number of transmit and receive antennas through flat-fading and frequency- or time-selective channels. Additionally, the described techniques provide flexibility for desirable tradeoffs among performance, rate, and complexity.

Abstract: A method of synchronizing a base station of a wireless communication system and a subscriber communication equipment located in the coverage area of the base station by compensating a sampling frequency offset in the subscriber equipment by interpolating input and/or output signals of a radio frequency part of the communication equipment to generate samples corresponding to the original symbol timing of the base station, and compensating the carrier frequency offset from the estimate of the sampling clock error.

Abstract: In a communication network, a network connection apparatus accepts timing information of a grand master to achieve timing synchronization. Next, the network connection apparatus requests slave nodes to be in timing synchronization with itself to achieve the timing synchronization. Even when the grand master is removed or crashed, when a new slave node is added, or when a hack node tries to hack the communication network, the network connection apparatus still periodically requests the slave nodes to be in timing synchronization with itself so that the timing synchronization inside the communication network is not negatively affected.

Abstract: A method for transmitting audio data of a plurality of audio sources through a single SPDIF link, includes: sequencing and multiplexing the audio data of the plurality of audio sources to pack the audio data of the plurality of audio sources into a plurality of frames of a block; performing bi-phase mark encoding on the audio data in the frames; appending preambles Z, X, and Y of the AES3/SPDIF stream format to the frames according to the number of audio sources in a first mode, or appending preambles Z, X, and Y of the AES3/SPDIF stream format and a specific preamble differing from preambles Z, X, and Y to the frames according to the number of audio sources in a second mode; and outputting the frames carrying the audio data into the SPDIF link with a frame rate greater than an audio sampling frequency of one of the audio sources.

Abstract: A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a first dual-port synchronous memory in accordance with the first clock and the second trace stream is routed to a second dual-port synchronous memory in accordance with the second clock. The first trace stream and the second trace stream are delivered to a memory in accordance with a third clock.

Abstract: Techniques for allocating transmission gaps and making cell measurements in asynchronous communication networks are described. A terminal establishes communication with a first communication network (e.g., a W-CDMA network), receives an initial allocation of transmission gaps for making cell measurements, and makes measurements for cells in a second communication network (e.g., a GSM network) during the allocated transmission gaps. The terminal determines the timing of at least one cell in the second network, which is asynchronous with the first network, and sends the cell timing to the first network. The terminal then receives a new allocation of transmission gaps for making cell measurements. The locations of the transmission gaps in the new allocation are determined based on the cell timing reported by the terminal. The terminal makes measurements for the at least one cell in the second network during the transmission gaps in the new allocation.

Abstract: Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided to a terminal connected in a wired or wireless network, specifically a terminal connected in a heterogeneous network, that requires TOD information. The apparatus includes a time server that provides standard TOD information, a gateway or a host personal computer (PC) that provides the standard TOD information of the time server to the terminal in a 3rd layer or lower instead of an upper layer of the open system interconnection (OSI) 7 layer model, and the terminal that adjusts a local clock according to the provided standard TOD information. According to the method and apparatus, the terminal not only maintains a very precise TOD by obtaining TOD information of the time server periodically or when required, but also obtains the TOD information without using application software for processing the TOD information.

Abstract: A system for managing the simultaneous operation of a plurality of radio modems in a single wireless communication device (WCD). The multiradio control may be integrated into a WCD as a subsystem responsible for scheduling wireless communications by temporarily enabling or disabling a plurality of radio modems. The multiradio control system may include a plurality of distributed control components, some or all of which are coupled to a dedicated radio interface. The radio interface is dedicated to quickly conveying delay sensitive information to and from the distributed control components. This information may be requested by any or all of the distributed control components, or provided by any or all of the radio modems if a change occurs during operation.

Abstract: In a clock-synchronous communication system, a clock pulse as a communication clock is outputted from a master device to a slave device so as to synchronize the master device and slave device. The transmitting side transmits a data to a data line with a first edge timing of the clock pulse, and the receiving side receives the data from the data line with a second edge timing of the clock pulse. A microcomputer as the master device is configured to enable separate setting of high-level duration and low-level duration of a clock pulse to be outputted, using a program. High-level duration and low-level duration are each set to a minimum value that satisfies the requirements for constituting communication with a communication destination. Uprating not only the cycle of a clock pulse but also the communication baud rate, efficient clock-synchronous communication can be performed.

Abstract: Various embodiments are described to address the need for providing wireless backhaul that may reduce operator startup costs while avoiding some of the drawbacks present in the prior art approaches. Generally expressed, the wireless network equipment (WNE) (121) of a collector cell provides access to a backhaul network (151) to one or more neighboring cells (122) via in-band wireless signaling. Given the frequency bands used by the collector cell WNE for communication with remote units, one portion of each band used for user traffic while another portion of each band is used for backhaul traffic. Having backhaul and user traffic share the assigned frequency bands can eliminate the need to license additional bands for wireless backhaul. Moreover, utilizing a portion of the existing, in-band orthogonal channels may be more spectrally efficient than using a separate radio in the same band.

Abstract: A system for transmitting a clock signal through a packet-based network is disclosed. The system comprises a first node configured to measure a clock frequency of the clock signal and calculate an accuracy indicator of the measured clock frequency; a second node configured to receive the clock frequency measurement and the accuracy indicator of the clock frequency measurement, and synthesize the clock signal therefrom; and a packet-based network for transmitting the measured clock frequency and accuracy indicator from the first node to the second node. A method of deriving a clock frequency by identifying packets with the shortest total transmission time is also disclosed.

Abstract: A multi-rate clock signal extracting device includes a light modulator, a photoelectric converter, a band-pass filter unit, a phase comparison unit, a bit rate changeover switch and a modulating electric signal generating unit. The light modulator modulates a light signal according to a modulating electric signal as a mixing signal obtained by mixing an electric signal with frequency f/(2j?1) and an electric signal with frequency ?f so as to output it as a modulated light signal. The modulated light signal is converted into a first electric signal by the photoelectric converter. A second electric signal group with frequency (2n?1)×?f is generated from signal components with frequencies (2n?1)×?f included in the modulated light signal by the photoelectric converter and the band-pass filter unit so as to be input into the phase comparison unit.

Abstract: A method and apparatus for transmitting packets in a wireless communication system (100). The method and apparatus determining a delay period from among the various delay times at each of a plurality of access nodes (106-110) wherein the delay time is the time it takes for a node to receive a data packet from a source (102) through a network (104). During transmission of data from the source, the nodes receive data packets and from the data packets, the wall clock time is determined. The packets are transmitted from the nodes at a time equivalent to the wall clock time and the delay period so that the packets are synchronously transmitted from the multiple nodes.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.

Abstract: The transmission apparatus according to the present invention includes a switching device that switches the multiplexing destination of mask symbols and uses this switching device to switch the multiplexing destination of the mask symbols so that the mask symbols multiplexed with control channel signals transmitted in parallel from a plurality of antennas may be transmitted from only one antenna at each transmission timing.