Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A method and apparatus for connecting a plurality of digital video recorders to a plurality of video transmitters via first transmission lines and for connecting the plurality of digital video recorders to a playback receiver via second transmission lines. The playback receiver incorporates an external synchronizing generator for externally synchronizing the plurality of the digital video recorders and the video transmitters. The recorders receiving the video signals generate and inject into the output signals a signal corresponding to identification codes allotted to each video signals. The playback receiver has a selection control circuit receiving selectively and synchronously any individually coded playback or monitored signal, or multiple playback or monitored signals which are displayed individually or in a split screen, respectively.

Abstract: Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input cell with a second delay chain and a second register block is provided for receipt of a data signal by the second delay chain. The second input cell is configured such that output from the second delay chain is coupled to a data input of the second register block. The first input cell and the second input cell may be operated in either a first modality or a second modality. The first modality may be for interfacing to a synchronous integrated circuit interface. The second modality may be for interfacing to a synchronous network/telecommunications interface.

Abstract: This disclosure relates to a satellite receiver controller having a digital to analog circuit with an output having a dynamic range offset voltage, which is adjusted in synchronization with a signal pulse.

Abstract: An inter-base station synchronization system is constructed without using any receiver for detecting a frame period error at a zone boundary between leaky coaxial cables, and without using any exclusive line or dedicated radio waves for use in transmitting the frame period error information from this receiver to base stations. This system has a plurality of base stations provided in certain intervals, leaky coaxial cables laid down between the base stations, and one, or a plurality of, mobile station that measure a time delay difference of received signals from adjacent ones of the base stations while the mobile stations move along zone boundaries between leaky coaxial cables, and that transmit the delay time difference information through the leaky coaxial cables to at least either one of the two adjacent base stations.

Abstract: A clock transmission apparatus for network synchronization between systems wherein a communication system having a main unit and a remote unit, the main unit generates an even-second (PP2S) pulse and transmits it to the remote unit and the remote unit uses the received PP2S to generate a system clock and a 10 MHz clock, so that network synchronization is realized between two systems. Network synchronization can be maintained between two systems using a cheap UTP (Unshielded Twisted Pair) without using a GPS system and an expensive transmission line.

Abstract: A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchronizer operable to synchronize a signal processed by said first logic to produce a signal synchronized to said second clock domain; a synchronized signal output operable to export from said data processor said synchronized signal output from said synchronizer; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronized signals from each of said plurality of data processors and to combine said exported synchronized signals to prod

Abstract: To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.

Abstract: In addition to fast on-off timing, instructive information on an output wave such as an amplitude or a slope is transmitted through a small number of signal lines. Output wave modifier information such as the amplitude or slope is transferred through serial communication 1, and an on-off timing signal is transmitted as an individual signal 20.

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

Abstract: Ultra wide band communication systems and methods are provided. In one embodiment, an ultra wide band communication system includes a first and a second communication device. A lowest common ultra wide band pulse repetition frequency is determined, and data is transmitted between the communication devices using the lowest common ultra wide band pulse repetition frequency. In another embodiment, a first and second slave transceiver communicate with a master transceiver using a time division multiple access frame, with the master transceiver providing transmission synchronization. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: An embodiment of a method for switching to an operating mode a device comprising a counter counting the pulses number of a first clock and a date synchronized with an external reference date. The embodiment comprising at least: step A: at a first pulse edge of the first clock, storing corresponding first pulses number and first date synchronized with a first reference date; step B: at a second pulse edge of the first clock, storing corresponding second pulses number and second date synchronized with a second reference date; step C: computing a frequency error of the first clock by using at least the values stored; step D: according to the frequency error, computing a third pulses number; and step E: switching the device to the second operating mode at the occurrence of the third pulses number.

Abstract: One or more embodiments provide Common Industrial Protocol (CIP) based time synchronization systems and methods. The CIP Sync solution can be part of Ethernet/IP and can be based on standard UDP (User Datagram Protocol) and/or IEEE 1588 (Time Synchronization) Ethernet technology. According to an embodiment is a system that compensates for step changes in a master clock.

Abstract: Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.

Abstract: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

Abstract: A signal supply apparatus for a public and private mobile communication system. The apparatus has Internet protocol base transceiver subsystems, and a private base station controller that controls the Internet protocol base transceiver subsystems. Instead of having a global positioning system receiver (GPSR) in each of the Internet protocol base transceiver subsystems to receive time of day (TOD) signals, the TOD signals are relayed to each of the Internet protocol base transceiver subsystems via a LAN cable. It is only the base station controllers that have the GPSR that receives the TOD signals. Then, these TOD signals are relayed from the base station controller to respective collective base station transceivers and then from each collective base station transceiver to their respective Internet protocol base transceiver subsystems via a LAN cable.

Abstract: A method for clock tracing in a network and a method for clocking tracing, the method for clock tracing in a network includes: distributed network element or a centralized server in the network determining a shortest path to each of clock-source network elements according to stored network topology information and clock-tracing link weight information; determining, among clock sources provided by reachable clock-source network elements, one with an optimal quality, where a clock-source network element with that clock source being considered optimal; and taking a shortest path to the optimal clock-source network element as a clock-tracing path. Furthermore, the method for clocking tracing uses such a clock-tracing path for clock tracing.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A system and method for minimizing the frequency error of satellite modem signals at a satellite gateway. The gateway downstream baud (symbol) clock and the elements that control the upstream frequency (i.e., local oscillators in the conversion chain, A/D sample clocks) are locked to a common frequency reference. The gateway sends upstream satellite frequency offset information, such as satellite ephemeris data from which to calculate Doppler offset, to the satellite modem. The satellite modem locks the frequency of the satellite modems master oscillator to the recovered baud rate using a frequency locked loop. The satellite modem uses its master oscillator as the carrier reference for the upstream frequency up conversion. The satellite modem uses or calculates the upstream satellite frequency offset and compensates for this offset by shifting its center frequency.

Abstract: A Universal Mobile Telephone System (UMTS) receiver performs slot synchronization using a received primary synchronization channel (PSCH). Subsequent to completion of slot synchronization, the UMTS receiver performs frame synchronization using a received secondary synchronization channel (SSCH) in such a way that the UMTS receiver uses the received primary synchronization channel (PSCH) to detect a change in channel conditions.

Abstract: The invention relates to a method and arrangement for transferring synchronizing information in a data transmission system including modem connections. The arrangement according to the invention comprises a modulator (207) that is arranged to generate an analog signal (222) modulated by synchronizing information, the frequency spectrum of said signal being located in a frequency range that falls outside the data transmission bands of the modem line connected to the network element. The arrangement includes a switching circuit (208) that is arranged to connect said analog signal to a data transmission cable (206) that forms part of said modem line connected to a network element. The arrangement includes a second switching circuit (209) that is arranged to receive said analog signal from a data transmission cable that forms part of the modem line connected to the second network element.

Abstract: In a communication system including nodes laid out in a grid, each node operates on a repetitive internal timing cycle, at certain phases in which the node transmits data and state variable signals. The state variable signals transmitted by a node indicate its internal phase and its position in the grid. The advance of the phase at each node is governed by a phase response function, which drives neighboring nodes whose data transmissions could collide out of phase with each other, and a synchronization alliance function, which brings certain nodes having positional relationships that preclude data collisions into phase with each other. A highly efficient data transmission timing pattern can thereby be established autonomously.

Abstract: A method and system for representing a low-order connection and a high-order connection as a single circuit are disclosed. The method includes creating a low-order listener object and a low/high listener object at each end point of the low-order connection and creating a high-order listener object at each end point of the high-order connection. The low/high listener objects are matched with the high-order listener objects to create a link and represent the connections as a single circuit.

Abstract: A redundant synchronous clock distribution system is provided comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system. Each of the first and second clock modules are adapted to act as a master clock module or a slave clock module. A clock switchover module is adapted to switch each of the first and second clock modules to change between the master mode and the slave mode. The clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, wherein the first circuit part is located on the first clock module and the second circuit part is located on the second clock module.

Abstract: A time synchronization device (TSD) that produces a synchronization signal and couples it onto energized power conductors in a power monitoring system. Monitoring devices coupled to the TSD include frequency detection algorithms, such as a Goertzel filter, for detecting the synchronization signal and interpreting the information encoded in the signal. The frequency of the synchronization signal may correspond to the fourth or tenth harmonic component of the fundamental frequency of the voltage on the power conductors. The magnitude of the signal is selected to be above the expected or established noise floor of the power monitoring system plus a predetermined threshold. The duration of the signal can be varied, such as lasting a full cycle of the fundamental frequency. Multiple TSD signals received in a predetermined sequence may be converted into digital words that convey time, configuration, reset, control, or other information to the monitoring device.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.

Abstract: Methods and apparatus which allow a wireless terminal (302) to simultaneously maintain connections with multiple base stations (304, 306) are described. Each wireless terminal (302) is capable of supporting multiple separate timing and/or other control loops one, for each base station connection thereby allowing the connections to operate independently and in parallel. Different control signals and/or data are transmitted on each connection that is established with a base station (302, 306). In this manner base stations (302, 306) receive different data allowing for asynchronous data transmission. The data received by the base stations (302, 306) can be supplied to a wired asynchronous network (308) without the need to combine the received data prior to supplying it to the wired network (308). The communications techniques of the invention can be used to implement soft handoffs without the need to duplicate data transmissions to multiple base stations.

Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Abstract: Method and system by which a base station without a Global Positioning System (GPS) receiver acquires time synchronization in a Broadband Wireless Access (BWA) communication system. The method includes scanning neighbor base stations around a first base station and requesting time synchronization information from the scanned neighbor base stations by the first base station; receiving responses from predetermined neighbor base stations having already acquired time synchronization from among the neighbor base stations, the responses including time synchronization information of the predetermined neighbor base stations; and selecting a second base station from among the predetermined neighbor base stations and acquiring time synchronization based on the time synchronization information of the second base station.

Abstract: A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

Abstract: The present invention provides an improved clock correction scheme for multi-carrier transmission systems, based on synchronizing a local receiver with a remote transmitter using estimated phase and frequency drifts between the remote transmitter and local receiver clocks. Also, described are communication devices and methods.

Abstract: A configuration for time control of a transmitting/receiving device in a mobile station has a system clock generator for producing a standard system clock for different time patterns is supplied to a programmable clock divider which produces an output clock corresponding to a time pattern that can be selected. An event controller carries out the time control of events on the basis of the output clock and of event information.

Abstract: A communication controller mounted on a node includes a data communicator transmitting a data signal, a transmission cycle information decider deciding transmission cycle information of that node on the basis of occurrence frequency of traffic, and a timing control signal receiver receiving a timing control signal. The timing control signal is indicative of a communication timing of the node. The communication controller further includes a communication timing calculator calculating a communication timing of that node in response to reception of the timing control signal, a timing control signal transmitter transmitting a merged signal of a timing control signal and the transmission cycle information to neighboring nodes, and a transmission-reception interruption controller determining whether or not to interrupt transmission and/or reception of the data signal and/or the timing control signal in that node, on the basis of transmission cycle information of the neighboring nodes or the node itself.

Abstract: A system and method for aligning a local timebase to a remote timebase given a timebase error value from a higher-level protocol, and using the aligned timebases to generate and distribute synchronized events and synchronized adjustable frequency periodic signals across a domain using the aligned timebases. Slightly speeding up or slowing down a periodic signal used to count time, a local timebase may be aligned to a remote timebase when given an error value from a higher-level protocol. A device may be configured to begin generating a periodic waveform at an agreed upon time in the future, once the timebases are aligned, where the time may be synchronized to remote devices via a synchronization protocol and an alignment mechanism. Remote periodic signals may remain synchronized to each other as long as the higher-level protocol and timebase alignment algorithm keep the timebases aligned.

Abstract: Method and apparatuses for broadcasting and receiving a programme are presented. A programme is broadcast from a broadcasting system. Broadcast programme-associated data is transferred from a server to a cellular radio network. The broadcast programme-associated data is transmitted from a base station of the cellular radio network at a specific frequency defined for the cellular radio network in such a manner that the transmission of the broadcast programme-associated data is synchronized with the broadcasting of the programme. The programme and the broadcast programme-associated data is received with a subscriber terminal of the cellular radio network in such a manner that a programme receiver of the subscriber terminal receives from the broadcasting path of the broadcasting system the programme and a cellular radio network transceiver of the subscriber terminal receives the broadcast programme-associated data at a specific frequency.

Abstract: An audio network system that performs transport of audio signals among nodes by cascading a plurality of nodes each including two sets of transmission I/Fs and reception I/Fs, and circulating among the nodes in each fixed period an audio transport frame generated by a master node, the audio transport frame including a plurality of storage regions for audio signals, is configured such that the master node measures time periods Dfw and Dbw after the audio transport frame is transmitted until the audio transport frame returns to the master node after passing through the transmission route and writes them into the audio transport frame, and each of the other nodes generates a signal processing wordclock based on those time periods, two reception times Tr1 and Tr2 while the audio transport frame circulates once through the transmission route, and a predetermined target time Tt.

Abstract: One embodiment of the present invention includes a distributed clock system. The distributed clock system includes a clock transmitter configured to programmably amplify and transmit a sine-wave signal corresponding to a clock signal, and a clock receiver configured to receive the sine-wave signal and to convert the sine-wave signal into a square-wave clock signal.

Abstract: The invention provides a method and system for synchronizing a transmitter and a receiver wherein the transmitter generates phase difference information indicating a phase difference between an internal and an external clock, the phase difference information is transmitted to the receiver, and the receiver generates a clock signal dependent on the transmitted phase difference information.

Abstract: A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a transmission clock signal. When the counted value reaches a set value, a strobe signal is output. A reception unit loads the transfer data onto a second register according to a reception clock signal. An edge detection unit generates a valid signal with a pulse width corresponding to one cycle of the reception clock signal when the strobe signal is detected. A third register loads the data that is output from the second register, and outputs it as reception data according to the reception clock signal when the valid signal is supplied.

Abstract: Systems and methods for processing signals are disclosed. The method may include, in a communication system comprising a plurality of devices, controlling the supply of one or more clock signals from a first clock source to one or more of the plurality of devices based on a signal communicated from a particular one of the plurality of devices to a second clock source and a request for a clock signal from one of the plurality of devices. The communicated signal may control an accuracy of the second clock source. The particular one of the plurality of devices may have highest accuracy requirements among the plurality of devices. At least one main clock signal may be generated for at least one of the plurality of devices utilizing an input clock signal received from the second clock source.

Abstract: Radio communication devices receive timing reference pulses from a timing generation device and can acquire synchronism based on the received pulses, so that even on the ultra wide band (UWB) radio communication system, where there is no carrier as exists in the conventional radio communication systems, there is no need to add a redundant preamble signal ahead of transmitted information in order to acquire initial synchronism. In order to receive an asynchronous signal, there is no need to perform detection for a very long time to find whether the signal is present or absent. The application of an access control system according to the present invention to UWB radio communication implements high-speed asynchronous radio communication.

Abstract: A receiver (RCV) for receiving data from a transmitter, comprises a first clock domain operating at a data rate synchronous with a clock of the transmitter, and having an input (RI) for receiving data. The data includes primary data, secondary data and control data. The receiver further has a second clock domain operating at a clock rate independent from the transmitter, and a clock-domain crossing unit for transferring data from the first to the second clock domain. The receiver further includes a slot counter for counting a number of units of received data converted by the clock-domain crossing unit into the second clock domain, a first identification unit (PRIM) for identifying control data indicative for the presence of primary and secondary data and a second identification unit (PAUSE) for identifying control data indicative whether slot counter of the receiver will be updated or not. It has an output (RO) for communicating an indicator indicative for the value of the slot counter.

Abstract: The invention relates to a method and device for the time-synchronised relaying of signals, whereby various signals from at least one signal source are relayed over various signal paths to at least one signal receiver, with time markers overlaid on the various signals. The delays occurring in the various signal paths are determined, a minimum total delay is calculated from the determined delays and information as to the minimal total delay is inserted in the various signals in the form of time-markers. A time-synchronous relaying of the signals is guaranteed in each signal path by means of an individual signal delay, the delay value of which corresponds to the difference between the minimal total delay and the delay caused by signal processing imposed on the signal in each signal path.

Abstract: A radio correcting timepiece that can reduce the influence of a radio wave situation of the standard radio wave having time information according to an area, and can make a correction to the exact time in a shorter time is provided. The radio correcting timepiece comprises a signal receiving means (1) for receiving a standard radio wave and a timepiece means (2) for correcting and displaying time on the basis of the time information outputted from the signal receiving means. The signal receiving means (1) can receive plural standard radio waves and includes memory means (1I) which is able to store signal receiving order of the plural standard radio waves. Since the plural standard radio waves can be received, the influence of a radio wave situation according to an area can be reduced and a correction to the exact time can be made in a shorter time by using the standard radio wave transmitted every minute.

Abstract: A digital signal synchronizer integrated circuit includes an input port which receives digital signals, programmable delay modules which synchronize the digital signals, and an output port which outputs the synchronized digital signals. A method of synchronizing a plurality of digital signals includes arranging synchronizer chips in a cascade and interconnecting the chips so that timing and control data may be communicated between the chips, connecting digital buses to the chips, synchronizing the digital signals carried by the digitals buses and outputting the synchronized signals.

Abstract: An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of the signal traces to adjust the transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. In yet another embodiment, a transmitting device generates a set of serially delayed write clocks, which are used to control symbol transmission over signal traces so as to reduce simultaneous switching output noise and ground bound in the transmitting device.

Abstract: A method of synchronizing data in a communications system includes generating a composite signal comprising a serial stream of data partitioned in one or more frames, and transmitting the composite signal to a receiver. Multiphase clock signals are generated. The composite signal received at the receiver is compared with each of the multiphase clock signals until either sustained coincidence therebetween is achieved or sustained non-coincidence is achieved, thereby synchronizing the receiver to bit boundaries in the composite signal and to one or more of the clock phase signals. One or more bit templates at the receiver is correlated with one or more corresponding bit templates in the composite signal received at the receiver to determine where frames start in the composite signal, thereby synchronizing the receiver to the one or more frames in the composite signal.

Abstract: A system may include a buffer, a local clock, and a processor. The buffer may store and output received media information. The local clock may control a rate at which the buffer outputs stored media information. The processor may determine a number of mean time differences between the local clock and a remote clock at a corresponding number of different times. The processor may also detect whether the local clock has drifted relative to the remote clock based on the number of mean time differences, and the processor may adjust the local clock if the local clock has drifted.

Abstract: The present disclosure relates generally to systems and methods for frequency synchronization in a non-hierarchical network. In one example, the method includes receiving, by a node in a wireless non-hierarchical network, frequency synchronization messages from other nodes. The method calculates an average frequency based on the frequency synchronization messages, calculates a control frequency based on the average frequency, and sets an oscillator of the node to the control frequency.