Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) synchronization module includes a window generator module, a symbol timing estimator module, and a reliability metric calculator. The window generator module generates a sampling window that bounds a plurality of samples of OFDM symbols. The symbol timing estimator module generates an estimated symbol timing from the plurality of samples before a fast Fourier transform operation is performed on the plurality of samples. The reliability metric calculator calculates a reliability metric for the estimated symbol timing based on the estimated symbol timing. The window generator module changes at least one parameter of the sampling window based on the reliability metric.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: A communication system for determining a target calibration parameter for calibrating impairments in a transmission signal is disclosed. The communication system includes a carrier signal generator, a transmitting module, a testing signal generator, a power detection unit, and a calibration apparatus. The testing signal generator generates a first testing signal to the first transmitting path of the transmitting module or a second testing signal to the second transmitting path of the transmitting module according to a single tone signal having a specific frequency or according to combinations of a DC value and the single tone signal. The power detection unit detects power of components associated with the specific frequency in the transmission signal to generate a power indicating signal. The calibration apparatus applies a first candidate calibration parameter to reference a first power indicating signal corresponding to the first candidate calibration parameter to determine the target calibration parameter.

Abstract: A quadrature frequency division multiplexing (“OFDM”) wireless receiver, including methods and devices for adaptive quantization of OFDM signals according to modulation and coding schemes and sub-carrier frequency responses, is provided. Efficient quantization may be utilized to reduce the large dynamic range of signals to achieve circuit simplification and chip area reduction. In one embodiment, a quantization circuit includes a quantization selector to select quantization thresholds according to modulation and coding schemes and sub-carrier frequency responses, and a non-uniform quantizer to reduce input dynamic range so that an output is represented by fewer bits than an input.

Abstract: A signaling method reduces bandwidth requirements and signaling delays normally associated with sending text-based signaling messages over a wireless links. An application at a transmitting endpoint generates and sends a binary-encoded signaling message, along with a binary interpreter that enables the receiving endpoint or SIP server to construct a text-based message from the binary encoded message. The binary-encoded signaling message may include references to a saved state, or to a dictionary to enable compression of the message. The signaling method can be used with any text-based signaling protocol, such as the Session Initiation Protocol, the Session Description Protocol, and the Real Time Streaming Protocol.

Abstract: Wireless communications devices, methods of processing a wireless communication signal, wireless communication synchronization methods and a radio frequency identification device communication method are described.

Abstract: Method and apparatus to manage delay for multiple receivers for a wireless system are described.

Abstract: The invention relates to an orthogonal frequency division multiplexing system with PN-sequence. In the synchronization of the invention, both timing offset and frequency offset are estimated and compensated by utilizing a time and frequency synchronization device. In addition, the PN-sequence with the cyclic prefix is added to the OFDM symbol before transmitting. The time and frequency synchronization device of the invention comprises two synchronization circuits from the cyclic prefix and PN-sequence when calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system of the invention not only has better performance in fading channel, but also has the better bandwidth utilization without extra bandwidth for transmitting the PN-sequence.

Abstract: In a synchronous acquisition method of a spread spectrum code, a digital code sequence is generated based on a received radio communication signal. The digital code sequence defines a spread spectrum code which includes a preamble symbol. A plurality of correlation signals are generated based on the spread spectrum code of the digital code sequence. A detection signal is generated in accordance with the correlation signal which corresponds to the preamble symbol. A timing control signal is generated in accordance with the detection signal. A demodulation signal is generated based on the correlation signals and in accordance with the timing control signal. A correction signal is generated based on the demodulation signal. A corrected timing control signal is generated based on the timing control signal and the correction signal, such that the demodulation signal corresponds to the preamble symbol.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: A method of synchronizing a base station of a wireless communication system and a subscriber communication equipment located in the coverage area of the base station by compensating a sampling frequency offset in the subscriber equipment by interpolating input and/or output signals of a radio frequency part of the communication equipment to generate samples corresponding to the original symbol timing of the base station, and compensating the carrier frequency offset from the estimate of the sampling clock error.

Abstract: In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.

Abstract: A signal receiver and a method for separating a RDS signal component from a received signal is described. After the received signal has been downconverted to the baseband, the baseband signal is split up into a first baseband signal for a first signal path and a second baseband signal for a second signal path. The first baseband signal is highpass filtered and forwarded to a frequency synchronization unit that generates a frequency synchronization carrier. The second baseband signal is modified in accordance with the frequency synchronization carrier provided by the first signal path, and a synchronized baseband signal is obtained that still comprises the full range of the RDS signal's spectral components.

Abstract: In an asynchronous read channel system, a reference value interpolation-type maximum likelihood decoder ASML having a small circuit scale (e.g., seven taps) is employed. A nonlinear waveform the equalizer SEQ is provided before the maximum likelihood decoder ASML. The nonlinear waveform the equalizer SEQ includes an FIR filter having, for example, four taps, and performs nonlinear waveform equalization with respect to an input digital signal so that only signal components having small amplitudes and high frequencies are amplified. After the nonlinear waveform equalization, the signal is input to the reference value interpolation-type maximum likelihood decoder ASML, which performs maximum likelihood decoding with respect to the signal. Therefore, even when the reference value interpolation-type maximum likelihood decoder includes a smaller number of taps and thus has a small circuit scale, maximum likelihood decoding with a high error correction function can be performed.

Abstract: In addition to fast on-off timing, instructive information on an output wave such as an amplitude or a slope is transmitted through a small number of signal lines. Output wave modifier information such as the amplitude or slope is transferred through serial communication 1, and an on-off timing signal is transmitted as an individual signal 20.

Abstract: A system and method is provided for bit eye center retraining. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively compares the location of the transitions to the expected locations to produce difference values, and combines pairs of difference values to determine when the sample point of the data stream needs to be adjusted.

Abstract: A method of establishing a synchronization signal in a communication system is disclosed. A set of discrete Fourier frequency coefficients is defined and transformed into a discrete time representation, the discrete time representation being particularly useful as a synchronization signal. According to example embodiments of the invention, signal symmetry is exploited. Preferably, the center frequency, also referred to as DC subcarrier, is not used for transmission. The invention also concerns a transmitter and receiver of a communication system.

Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Abstract: Methods of controlling activation of electrical appliances can include reducing overlapping activation time of different electrical appliances located at a single customer location of an electrical service provider during at least one time interval during a day. Related systems, circuits, and computer program products are disclosed.

Abstract: A method and circuit for precisely synchronizing clocks in separate nodes on a communication network is provided by adjusting timestamps and related data in network messages. The circuit will allow a daisy-chain connection of the nodes and will forward time synchronization frames while accounting for delays in a manner that does not use boundary clocks, but does not depart from the IEEE 1588 standard protocol. The delays will be added on the fly to synchronization packets and the IP checksum and frame CRC will be adjusted. Deterministic data delivery and redundant data paths are also provided in a full duplex Ethernet network.

Abstract: Aspects of a method and system for 60 GHz wireless clock distribution may include configuring a microwave communication link established between a first chip and a second chip via a wireline communication bus. The configuration may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first chip, and of a second antenna array communicatively coupled to the second chip. The first chip and the second chip may communicate a clock signal via said microwave communication link. The microwave communication link may be routed via one or more relay chips, when the first chip and the second chip cannot directly communicate. Control data may be transferred between the first chip, the second chip, and/or the one or more relay chips, which may comprise one or more antennas. The relay chips may be dedicated relay ICs or multi-purpose transmitter/receivers.

Abstract: A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.

Abstract: A sync detector includes a correlation computing unit configured to receive signal values corresponding to respective sample points and to compute auto-correlation of the received signal values between sample points of interest and sample points that are situated at a distance equal to a constant number of sample points from the sample points of interest, a correlation value synthesizing unit configured to receive auto-correlation values corresponding to respective sample points obtained by the correlation computing unit and to synthesize the auto-correlation values with respect to at least two sample points among sample points that are spaced apart by the constant number of sample points thereby to compute a synthesized correlation value, and a peak-point detecting unit configured to detect a position of a sample point corresponding to a largest synthesized correlation value among synthesized correlation values corresponding to respective sample points obtained by the correlation value synthesizing unit.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit receives a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, while the reception-end clock signal has N clocks as generated. When the difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the synchronization processing unit controls media signal playing according to the reception-end clock signal and the procedure clock signal.

Abstract: An apparatus and method for frequency synchronization is proposed to obtain the pilot tones and evaluate the frequency offset and time offset for frequency synchronization. The frequency synchronization method has the following steps: filtering a baseband signal of a frequency correction burst by using multiple pre-filters; measuring the baseband signal and the signals output from the pre-filters to produce the first power value and the second power values respectively; normalizing the maximum second power value by using the first power value so as to produce the first detection value; using the samples of the baseband signal at different time points and a predetermined mathematical function to produce the second detection value; combining the first and second detection values to produce the third detection value; and using the third detection value to determine whether the frequency correction burst is received or not.

Abstract: A phase difference detection device able to detect a phase with a high precision is provided.

Abstract: An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase.

Abstract: In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted network synchronization clock signal, compares the value of one period of the network synchronization clock signal to the value of one period of the divided clock signal, and determines whether the network synchronization clock signal is normal or not. Thus, the reliability of an operation of checking the network synchronization clock signal is enhanced.

Abstract: A first node initiating communications with a second node already in a secure network sends a discovery burst having a preamble portion and a payload portion. The preamble portion is sent at a varying frequency between high and low thresholds that are reflective of Doppler uncertainty between the nodes. The second node continuously listens at a frequency, termed an acquisition frequency. A data sequence in the preamble portion, known to the second node, is received and used to determine the receive instant in the preamble portion, and thereby compare against the known frequency ramp to determine the frequency at which the payload portion will be received. Preferably, the first node varies the preamble portion between thresholds more than once within the time span of a single preamble portion, and the preamble and payload portions are spread with different spreading codes. The preamble portion may also be disguised with noise generated by the first node.

Abstract: Disclosed herein is a transmission apparatus, including: a control section configured to control the timing at which actual data from a data source is to be transmitted to a reception apparatus; and a transmission section configured to produce a control signal representative of the contents of the control of the control section, transmit the control signal to the reception apparatus through a first signal line, receive the actual data from the data source under the control of the control section and transmit the received actual data to the reception apparatus through a second signal line.

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract: A phase interpolator according to an embodiment of the present invention includes a first mixer group including two mixers which are provided with a clock “D0” having a delay equivalent to a phase difference of 0 degree with respect to a reference clock, and generate and output a clock “D0+2Dc” having a delay equivalent to a phase difference of 0 degree with respect to the reference clock and a delay produced by two mixers, a second mixer group including two mixers which are provided with the clock “D0” and a clock “D90” having a delay equivalent to a phase difference of 90 degrees with respect to the reference clock, and generate and output a clock “D45+2Dc” having a delay equivalent to a phase difference of 45 degrees with respect to the reference clock and a delay produced by two mixers, and at least one mixer which generates and outputs, by using any two of the clocks “D0”, “D90”, and “D45+2Dc”, a clock having a delay equivalent to a phase difference of a predetermined angle with respect to the reference

Abstract: A method is provided for compensating for clock drift error and movement error of an access terminal. A forward link error is obtained that is attributable to at least a first error (e.g., clock drift error) component and a second error (e.g., movement error) component. The first error component and the second error component are estimated based on the obtained forward link error. A receive clock of the access terminal is compensated based on a combination of the first error component and the second error component. A transmit clock of the access terminal is compensated based on a difference between the first error component and the second error component. The forward link error may include a timing synchronization error between the access terminal and an access point as well as a frequency synchronization error between a forward link frequency and a baseband reference frequency.

Abstract: The present invention provides asynchronous digital capture by first, capturing the digital output of the device under test (DUT) clock on an automated test equipment (ATE) digital channel. Next, the NRZ output data of the DUT is captured while the clock signal is captured on adjacent ATE channels. Next, the digital clock data is analyzed such that a frequency spectrum is generated. From the spectrum, the frequency and phase of the clock is calculated. From the clock frequency, the number of device cycles captured is determined. From the phase of the clock, the captured data is aligned with the clock data to determine which device cycles have been oversampled.

Abstract: A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.

Abstract: A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets according to a spreading sequence of the time frequency code, a comparison unit for comparing correlation values provided by division units of the plurality of packet detection units, and a packet decision module for determining a time frequency code and size of a fast Fourier transform sampling window according to output signals of the comparison unit, allowing a frequency band to be selected and synchronization to be executed.

Abstract: A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the reception data buffer unit, a variable clock generation unit generating a clock having a variable frequency, a time information output unit outputting second time information counted in accordance with the frequency of the clock generated by the variable clock generation unit, and a first time information comparison unit comparing the first time information added to the packets with the second time information outputted from the time information output unit and controlling the timing of outputting the packet stored in the reception data buffer unit. The reception data amount measuring unit controlling the frequency of the clock generated by the variable clock generation unit in accordance with measured values obtained by the reception data amount measuring unit.

Abstract: A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred.

Abstract: Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

Abstract: The present invention relates, in general, to a joint channel and frequency offset estimation apparatus and method based on a multi-band-orthogonal frequency division multiplexing system, and, more particularly, to a joint channel and frequency offset estimation apparatus and method based on an MB-OFDM system, which uses low-rank LMMSE channel estimation, in which a low-rank is applied to the MB-OFDM system, thus decreasing complexity, and adds a simple structure using the autocorrelation characteristics of an estimated channel, thus joining channel estimation to frequency offset estimation at low complexity. The apparatus includes a channel estimator for receiving a Fourier-transformed OFDM signal, and calculating results of channel estimation using a Linear Minimum Mean Square Error (LMMSE) channel estimation, which minimizes a Mean Square Error (MSE) between an actual channel value and an estimated channel value.

Abstract: In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Abstract: A frequency compensation circuit for compensating for a frequency offset in a received signal, the received signal including a periodically repeated pilot sequence for phase locking. The circuit comprises a phase estimator for estimating a phase of the received signal; a phase compensator, associated with the phase estimator, for compensating for the phase; a frequency estimator, comprising a maximum likelihood estimator comprising a first modification for estimating a frequency offset which is small relative to a symbol time, from the pilot sequence, the frequency estimator being connected downstream of the phase compensator; and a frequency compensator for applying a compensation to the signal, thereby to compensate for the frequency offset. The compensator is suitable for the exacting conditions of the DVB-S2 standard.

Abstract: Circuitry is provided in a programmable logic device incorporating clock-data recovery circuitry on I/O channels to allow the use of otherwise unused noise-reduction circuits in the I/O channels, such as decision-feedback equalization (DFE) circuits, to cancel or minimize cross-talk with other channels or other sources of cross-talk. Selectable connections are provided to allow various potential sources of cross-talk to be programmably connected to the DFE circuits instead of unused CDR output taps. When a user finalizes a user logic design, the user can determine the sources of cross-talk and the unused taps relative to a particular channel, and programmably connect the sources to the DFE circuits corresponding to those unused taps. DFE coefficients may then be adjusted to cancel or at least minimize the cross-talk. Programmable time delays can be provided to adjust for clock differentials between the cross-talk source and the particular channel under consideration.

Abstract: A detector for detecting a received signal according to a Gaussian shift keying (“GFSK/GMSK”) modulation scheme. The detector may enhance a detection performance of the receiver while limiting one or more implementation impacts. An implementation impact may include an implementation complexity impact, an implementation cost impact, or other impacts. The detection performance of the detector may be enhanced in relation to one or more performance aspects, such as, an ISI aspect, an AWGN aspect, a co-channel interference aspect, a sensitivity aspect, an error propagation aspect, or other aspects. The detector may be configured or reconfigured to enhance one or more particular performance aspects. The enhancement of the particular performance aspects may affect, adversely or otherwise, one or more related performance aspects that may be related to the particular performance aspects. The detector may be configured or reconfigured according to a current application of the detector.

Abstract: A high speed transmission system transfers data streams over a set of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and please is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.

Abstract: A clock data recovery circuit which reproduces clock contained in data sequence from data sequence which is serially input includes a digital control oscillator outputting reproduced clock whose frequency is controlled according to a control signal. A phase comparator compares a phase of the data sequence and a phase of the reproduced clock. A digital control circuit produces the control signal in accordance with an output of the phase comparator, first control information indicating a first period for which the frequency of the reproduced clock is changed, and a second control information indicating a number of steps by which the frequency of the reproduced clock is changed.

Abstract: A server apparatus receives packetized data and transmits the packetized data over a network. The apparatus includes an input for receiving the packetized data from a signal source. An AC clock counter receives an AC power signal and generates a count value in dependence upon a frequency of the AC power signal. An output is coupled to the network and transmits the packetized data and the count value to a client device. A clock associated with the client device is controlled in dependence upon the count value.