Abstract: A signal transition detection circuit is provided. The signal transition detection circuit comprises a counter module, a DAC, a comparator and a digital sampling module. The counter module generates a digital step signal. The DAC converts the digital step signal into an analog input signal and transmits it to an under-test circuit such that the under-test circuit generates an output signal transiting from a first stable level to a second stable level, wherein a transition section is located between the first and the second stable level. The comparator receives and compares the output signal with a default value to generate a normalized output signal. The digital sampling module samples the normalized output signal to retrieve impulses such that when the number of the impulses is accumulated to be larger than a reference value, a corresponding step of the digital step signal is determined to be a transition point.

Abstract: A method for providing timing recovery from a received digital data stream where the digital data stream is a series of consecutive data samples. The method separates the data stream into a series of consecutive observation periods where each observation period includes the same number of consecutive data samples. The method also includes identifying a series of consecutive timing recovery data samples in each observation period where the timing recovery data samples are used for timing recovery and other data samples in the observation period are not used for timing recovery, and where the number of data samples used for timing recovery in each observation period is less than the number of data samples that are not used for timing recovery in the observation period. The method then uses the timing recovery data samples for timing recovery in each observation period.

Abstract: The present invention relates to a communication method, system and signal, and in particular to a method and system for communicating information in a digital signal. It has particular application to satellite or terrestrial packet-based multi-user radio communication systems. A method for communicating information in a digital signal comprising data symbols is disclosed, wherein the information is encoded in a sequence characteristic of pilot symbols distributed amongst the data symbols, such that a receiver is able to determine the sequence characteristic and retrieve the transmitted information. The invention allows information to be encoded into a sequence characteristic of pilot symbols, rather than relying on modulating such information onto the pilot symbols themselves. This allows a significantly larger number of pieces of information to be transmitted than hitherto possible, and the technique is more resistant to large frequency errors than prior techniques.

Abstract: A method of and apparatus for synchronous data transfer are described. The method may include encoding a clock period and data into an encoded signal, transmitting the encoded signal from a master device to a slave device, and recovering the data at the slave device without using a local oscillator. The apparatus may comprise a first integrated circuit including a master device configured to transmit an encoded signal of a clock period and data on a first port, and a second integrated circuit including a slave device where the slave device is configured to receive the encoded signal on a second port coupled to the first port and to recover the data without using a local oscillator.

Abstract: A method for detecting a pattern in a signal according to one embodiment includes determining a time between symbol transitions in a signal derived from a radio frequency signal; determining ratios of relational times between consecutive symbol transitions; and comparing a sequence of the ratios to a target pattern for determining whether the sequence corresponds to the target pattern. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: Provided is a symbol synchronization apparatus and method of a passive RFID reader. The symbol synchronization apparatus includes: an edge clock detector generating edge clocks by detecting phase inversion positions of a received signal; a preamble detector detecting a preamble section by analyzing the generation times of the edge clocks; a symbol decision time extractor extracting a symbol decision time by averaging distances between the edge clocks consecutively generated in the preamble section, when the preamble section is detected; and a symbol decider deciding a symbol by analyzing the magnitude of the received signal, when the time reaches the symbol decision time.

Abstract: Techniques for transmitting pilot and for processing received pilot to obtain channel and interference estimates are described. A terminal may generate pilot symbols for a first cluster in a time frequency block based on a first sequence and may generate pilot symbols for a second cluster in the time frequency block based on a second sequence. The first and second sequences may include common elements arranged in different orders and may be considered as different versions of a single sequence. The terminal may transmit the pilot symbols in their respective clusters. A base station may obtain received pilot symbols from multiple clusters in the time frequency block. The base station may form each of multiple basis vectors with multiple versions of the sequence assigned to the terminal and may process the received pilot symbols with the multiple basis vectors to obtain a channel estimate for the terminal.

Abstract: A method of syncing a serial data stream includes the step of providing a data stream having frames and sub-frames. Each sub-frame is provided with an expected SYNC Word, and there is an expected offset between the SYNC Words in each sub-frame. The data is sent to a plurality of sync modules. Each sync module searches for an expected and different one of the SYNC Words. The sync modules identify an expected SYNC Word, then look for a different one of the SYNC Words at said expected offset from its expected SYNC Word to verify that it has properly identified a SYNC Word.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: Systems, methods, and circuits provide phase inversion of a clock signal. A first clock signal is received. A phase inversion signal indicates the existence of a 180 degree phase difference between the first clock signal and a second clock signal. As a result of the phase inversion signal indicating the 180 degree phase difference, the system, methods and circuits adapt the first clock signal by extending the first clock signal by a phase such that the first clock signal's rising edges and falling edges align with the second clock signal's rising edges and falling edges. As a result, the 180 degree phase difference between the clock signals is eliminated.

Abstract: A radio communication system has a transmitter and a receiver that transmits and receives, respectively, synchronization signals. The transmitter has a multiple-synchronization-signal generation section configured to generate the synchronization signals, a radio circuit configured to transmit the synchronization signals in a predetermined transmission cycle from a start time of the predetermined transmission cycle and with an interval shorter than the predetermined transmission cycle, and a synchronization signal sequence number generation section configured to assign a sequence number to each of the synchronization signals.

Abstract: There is provided a high resolution circuit for converting a capacitance-to-time deviation including a capacitance deviation detecting unit generating two detection signals having a phase difference corresponding to variations of capacitance of an micro electro mechanical system (MEMS) sensor; a capacitance deviation amplifying unit dividing frequencies of the two detection signals to amplify the phase difference corresponding to the capacitance deviation; and a time signal generating unit generating a time signal having a pulse width corresponding to the amplified phase difference.

Abstract: An object of the present invention is to provide a data communication technique which can reduce a size of a system by enabling bidirectional data communication, and enables a cheap system configuration.

Abstract: Provided is an equalization device which receives a signal transmitted from a transmission side of the signal as an input signal, and equalizes the deterioration of a wave shape of the received input signal, wherein a bit value indicated by the input signal is judged in accordance with a clock on the basis of the wave shape of the input signal. From judged signals which result from the judgment and which are composed of a plurality of bits, a two-bit transition signal is detected so that the two-bit transition signal has two adjacent bit values having the same value, and bit values located before and after the two adjacent bit values are different from the bit value of the two adjacent bit values, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal.

Abstract: A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: An apparatus detects, from symbol data of a predetermined communication scheme that is input via a common public radio interface (CPRI) at a first rate indicating a chip rate for the CPRI, a timing at which a clock phase matches between the first rate and a second rate indicating a symbol rate for the predetermined communication scheme, where the CPRI is an internal interface for a radio communication apparatus. The apparatus changes, at the timing, a clock rate for transmitting the symbol data, from the first rate to the second rate.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: Disclosed is a method for modulating and demodulating data. The method composes symbols by grouping a plurality of symbols for pulse position modulation to newly add symbol compositions to fixed symbols used for the pulse position modulation of the related art. Further, the method uses grouped symbols to improve data transmission rate as the average amount of information increases.

Abstract: A medical sensor system comprises a gateway comprising a wideband receiver and a narrow band transmitter, the each gateway configured to receive a wideband positioning frame using the wideband receiver from one or more wearable sensors and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the sensors to establish timing for transmission of the positioning frame; and at least one wearable sensor comprising a wideband transmitter and a narrow band receiver, the sensor configured to transmit a sensor data frame to the gateway using the wideband transmitter and to receive an acknowledgement frame from the gateway using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract: A packet trace is received. The packet trace is transformed into a sequence of pulse signals in a temporal domain. The sequence of pulse signals in the temporal domain is transformed into a sequence of pulse signals in a frequency domain. Peaks are detected within relevant frequency bands in the sequence of pulse signals in the frequency domain. A fundamental frequency is identified within the peaks. The fundamental frequency, which represents the TCP flow clock, is returned.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: The present application discloses a method in which a base station transmits a reference signal sequence in a wireless communication system. In detail, the method comprises the steps of: generating a pseudo-random sequence using a first m-sequence and a second m-sequence; generating the reference signal sequence using the pseudo-random sequence; and transmitting the reference signal to a mobile station via antenna ports different from one another. The second m-sequence has an initial value containing parameters for discriminating reference signal sequences among users.

Abstract: Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.

Abstract: The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.

Abstract: Receiving a modulated carrier signal that is modulated using a reference signal, wherein an acquisition by a digitizer is synced to the reference signal such that the modulated carrier signal has known timing with respect to a start of an acquisition within the digitizer. Further including routing the modulated carrier signal through a receiver system to generate a processed signal, receiving the processed signal at the digitizer, digitizing the processed signal at the digitizer, and determining a delay of the modulated carrier signal routed through the receiver system based on the timing of the processed signal.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

Abstract: An apparatus for synchronizing audio data and visual data and a method therefor are provided. The apparatus includes a splitter, a synchronization unit coupled to the splitter, an audio control unit coupled to the splitter and the synchronization unit, and a visual data processing unit coupled to the splitter and the synchronization unit. The splitter receives an application layer data frame including audio data and visual data and splits the visual data from the audio data. The synchronization unit receives audio timing information of the audio data and acquires synchronization information according to the audio timing information and external timing information. The audio control unit receives and temporarily stores the audio data and outputs the audio data according to the synchronization information. The visual data processing unit analyzes and temporarily stores the visual data and outputs the visual data together with the audio data according to the synchronization information.

Abstract: In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: There is provided a communication system that includes master and slave communication ECUs. The master communication ECU sends a clock signal to a clock communication line, with which the communication ECUs synchronize with each other when sending and receiving data. The master and slave communication ECUs then receive the clock signal through the clock line. The ECUs use the received clock signal as a reference timing, which is designated as a transmission/reception reference, and send or receive data to/from data communication lines.

Abstract: A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.

Abstract: A positioning system comprises a plurality of controllers, each controller comprising a wideband receiver and a narrow band transmitter, the each controller configured to receive a wideband positioning frame using the wideband receiver from one or more devices and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the devices to establish timing for transmission of the positioning frame; and at least one device comprising a wideband transmitter and a narrow band receiver, the device configured to transmit a positioning frame to the plurality of controllers using the wideband transmitter and to receive an acknowledgement frame from one or more controllers using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract: Embodiments of the present invention set forth a method and system for reducing uncertainty in receive and transmit timestamps created by an NTP server. The uncertainty in the receive timestamps is removed by recording the time-of-arrival in the hardware clock of the NTP server before the incoming packets may be delayed by traversing the various layers of software in a timestamping system. The uncertainty in the transmit timestamps is removed by giving the outgoing packets a timestamp in the future using an estimate of the transmission latency calculated by the latency estimator filter. Subsequently, the actual time-of-departure is used to re-calculate and update the estimate of the transmission latency. In this fashion, superior control of the timestamping function may be implemented in existing NTP servers in a manner that retains interworking compatibility with the current NTP standards.

Abstract: Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.

Abstract: A signal processing apparatus, which executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10” to any one of binary digital signals “0 and “1”, and assigning two bits of “01” to the other binary digital signal, is provide with a decoding unit which executes the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of the first bit and the second bit of the Manchester-encoded digital signal.

Abstract: The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.

Abstract: A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.

Abstract: In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(?1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

Abstract: A signal processing apparatus, which executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10” to any one of binary digital signals “0 and “1”, and assigning two bits of “01” to the other binary digital signal, is provide with a decoding unit which executes the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of the first bit and the second bit of the Manchester-encoded digital signal.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: A data receiver circuit includes: a clock/data recovery circuit to recover a clock and data from a received signal; a fixed pattern generation circuit to generate fixed pattern data; a first selection circuit to select and output one of the fixed pattern data generated by the fixed pattern generation circuit and recovered data recovered by the clock/data recovery circuit; a second selection circuit to select and output one of a reference clock and recovered clock recovered by the clock/data recovery circuit; and a switching circuit to make the first selection circuit output the fixed pattern data and to make the second selection circuit output the reference clock, when an input signal is lost or the clock/data recovery circuit is in a loss-of-lock state.

Abstract: A frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths. A differential correlation detector calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. Frame period confirmation counters perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 1 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Abstract: For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.