Abstract: A method for digital timing recovery from oversampled analog signals includes computing filter coefficients for digitized samples of the oversampled analog signals based on an oversampling factor of the oversampled analog signals, using the filter coefficients in a rotation filter to compensate for the oversampling factor in the digitized samples of the oversampled analog signals, deriving a starting phase and magnitude from the compensated digitized samples of the oversampled analog signals, and using the starting phase and magnitude in a timing recovery loop to recover a clock from the compensated digitized samples of the oversampled analog signals. The rotation filter may include a plurality of taps, and the circuitry may be configured to compute respective sets of coefficients for respective taps. Each set of coefficients may be dependent on another set of coefficients, or the coefficients may be approximate with each set of approximate coefficients being independent.

Abstract: A first component of a network device determines that the first component is to provide packet data to a second component of the network device for processing by the second component. In connection with determining that the first component is to provide packet data to the second component of the network device, the first component prompts the second component to activate a clock network of the second component. In connection with prompting the second component to activate the clock network, the first component sends the packet data to the second component to be processed by the second component. The first component determines when the second component has completed processing of the packet data, and prompts the second component to deactivate the clock network in response to determining that the second component has completed processing of the packet data.

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Abstract: Embodiments of the present invention provide duplication schemes for control frames to extend the range of LPI in the 6 GHz wireless band for EHT WLAN. Duplicate 20 MHz legacy preambles containing L-STF, L-LTF, L-SIG and RL-SIG, U-SIG and EHT-SIG fields may be used to transmit beacon and other control frames using duplicate PPDUs to extend transmission range thereof. Non-HT duplication can be performed to maintain backwards compatibility with legacy devices. HE duplication can include duplication of a 20 MHz HE SU PPDUs over 40 MHz, 80 MHz, 160 MHz or 320 MHz portions, for example. DCM+MCS0 or duplication over DCM+MCS0 may be applied to the payload, and a duplication indication is inserted in the U-SIG field or EHT-SIG field to indicate if the duplication is applied to the payload over DCM+MCS0.

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

Abstract: The present disclosure provides a signal generation device, comprising at least two signal generators, a clock source that is coupled to the at least two signal generators and that is configured to generate a clock signal and provide the clock signal to the at least two signal generators, wherein the signal paths between the clock source and each one of the at least two signal generators are matched at least regarding the signal runtime, and wherein the at least two signal generators are each configured to generate an output signal based on the clock signal. Further, the present disclosure provides a respective measurement device and a respective method.

Abstract: In a general aspect, a set of observed frequency-domain channel responses is filtered to remove noise or distortions that are not related to changes in the physical environment. In some aspects, for each frequency-domain channel response, a time-domain channel response is generated based on the frequency-domain channel response; and a filtered time-domain channel response is generated based on a constraint applied to the time-domain channel response. Additionally, a reconstructed frequency-domain channel response is generated based on the filtered time-domain channel response. An error signal is also generated, and a determination is made as to whether the error signal satisfies a criterion. The error signal can be indicative of a difference between the frequency-domain channel response and the reconstructed frequency-domain channel response. In response to each of the error signals satisfying the criterion, motion of an object in a space is detected based on the set of frequency-domain channel responses.

Abstract: Certain aspects of the present disclosure provide techniques for dynamic configuration of demodulation reference signals (DMRSs). A method that may be performed by a base station (BS) includes receiving one or more uplink signals from at least one user equipment (UE); estimating a Doppler shift associated with the one or more uplink signals; determining a density of reference signals (RSs) within a slot for the at least one UE based, at least in part, on the estimated Doppler shift associated with the one or more uplink signals; and transmitting information to the at least one UE indicating an allocation of RS resources for the UE, wherein the allocation of the RS resources is based on the density of the RSs for the at least one UE.

Abstract: A system for monitoring the state of a cable, includes a plurality of transferometry devices capable of injecting a test signal into the cable and measuring a signal being propagated in the cable, the transferometry devices being positioned along the cable so as to break down the cable into successive sections, the system comprising a control member capable of communicating with the transferometry devices and configured so as to perform at least one transferometry test consisting in injecting a test signal into the cable by means of a first transferometry device and measuring the test signal after its propagation in the cable by means of a second transferometry device different from the first device, the system comprising a post-processing member capable of communicating with the transferometry devices and configured to compare the measured signal to a reference signal to deduce therefrom an indicator of degradation of the section of cable disposed between the first transferometry device and the second transf

Abstract: A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a ?3-dB corner frequency of 40 MHz.

Abstract: Disclosed are techniques for using firmware and hardware blocks of a device to decode signals encoded by signal edge positioning within a data bit width, such as bi-phase mark space coding (BMC) used for encoding in-band communication of wireless charging systems. The first device may use general purpose I/O (GPIO) interrupts to detect the start of a packet. The firmware may synchronize and configure the clock of a serial peripheral interface (SPI) to oversample the signals. The SPI may store the sampled data into a buffer, freeing the firmware from having to expend processing cycles to detect the transitions of the data in real-time. The firmware may read the buffered samples to decode the packet data in a post-processing stage. The firmware may detect the end of the packet by polling and GPIO interrupts or based on the samples read from the buffer to stop the clock of the SPI.

Abstract: The present disclosure provides a clock and data recovery processor for recovering timing information from a measured signal with a data input interface configured to receive samples representing the measured signal, a level comparator coupled to the data input interface and configured to determine the signal level for each of the received samples in a group comprising a predetermined number of samples, a transition comparator coupled to the level comparator and configured to compare the number of signal transitions for the samples in the group with a predetermined transition number, and a bit value determiner coupled to the transition comparator and configured to determine bit values for data symbols in the measured signal based on the detected transitions, if the transition comparator determined the number of signal transitions being equal to or larger than the predetermined transition number. Further, the present disclosure provides a measurement device and a respective method.

Abstract: A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

Abstract: A vehicle control apparatus is mounted on a vehicle to perform wireless communication with a portable terminal. The vehicle control apparatus includes a first processor configured to execute a first process including a determination process that determines whether or not a received signal, which is a wireless signal received by an antenna mounted on the vehicle and encoded, is a regular wireless signal transmitted from the portable terminal by determining whether or not a counted number of short bits sandwiched by two long bits adjacent to each other in the received signal is an even number.

Abstract: A signal equalizer comprising: a feedback system, configured to acquire at least one signal value of an edge region of an input signal, and configured to adjust the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region.

Abstract: A system for simulating a wireless communication network over a wired network may comprise a plurality of physical UEs, one or more RANs, and a channel condition emulator. The plurality of UEs may be coupled to one another through the wired network. The one or more RANs may be simulated in software to simulate data transmissions between the plurality of UEs. The channel condition emulator may be simulated in software to derive channel conditions for each of the plurality of UEs based on their current location. The channel condition emulator may further provide the channel conditions to the plurality of UEs and the one or more RANs.

Abstract: A delay locked loop circuit includes: a variable delay line configured to delay an initial clock signal to generate a delayed clock signal; and a control circuit connected to the variable delay line, configured to control the variable delay line to perform delay adjustment of a first mode and further configured to perform delay adjustment of a second mode on the variable delay line when the delayed clock signal satisfies a preset condition. A step value of each delay adjustment of the first mode is a first step value, a step value of each delay adjustment of the second mode is a second step value, and the second step value is greater than the first step value.

Abstract: Disclosed are a data processing method and apparatus. The method includes: a first receiving end determines a range of a data demodulation reference signal (DMRS) ports occupied by one or more second receiving ends by using at least one of the following information: a usage state of a joint encoding table corresponding to a DMRS port group, the number of layers corresponding to a physical downlink shared channel (PDSCH) of the first receiving end, and the number of codewords corresponding to the PDSCH of the first receiving end; and the first receiving end processes data according to the range of the DMRS ports occupied by one or more second receiving ends.

Abstract: A three-phase transmitter that sets voltages of first, second, and third output terminals based on first, second, and third signals. The transmitter includes a first transmitting section configured to set the voltage of the first output terminal based on the first and third signals; a second transmitting section configured to set the voltage of the second output terminal based on the first and second signals; and a third transmitting section configured to set the voltage of the third output terminal based on the second and third signals.

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

Abstract: Aspects of the embodiments are directed to a data transmission receiver that includes a neural network circuit for resolving a received bit value. The data transmission receiver can be coupled to a data transmitter by a high speed data link. The neural network circuit can sample a bit value at multiple locations across the bit's unit interval. The neural network circuit can also sample bit values for neighboring bits to the interested bit at multiple sampling locations across unit intervals for the neighboring bits. The neural network circuit can determine the value of the interested bit from the samples of the waveform.

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

Abstract: Embodiments of various methods, devices and systems are described herein that correspond to an encoding scheme that can be used with various communication protocols for increased bandwidth over a single wire bus or a wireless single transmission channel. For example, a method of encoding a series of data bits to increase bandwidth may comprise selecting a data bit in the series of data bits, generating an inverted version of the selected data bit, positioning the inverted version of the selected data bit in a consecutive fashion with respect to the selected data bit to signify an edge of a clock signal, and transmitting the inverted version of the selected data bit and the series of data bits with each bit being transmitted in a single unique time slot.

Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

Abstract: Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines. For a quadrature encoded signal, the input signal is separated into intermediary signals representing a real portion of and an imaginary portion. The processing circuit can then determine timing information from the real portion of and the imaginary portion. The intermediary signals can then be decimated according to a variable rate of decimation that is responsive to the determined timing information. The decimated intermediary signals are also filtered.

Abstract: A method for synchronizing an output clock signal with an input clock signal in a delay locked loop. A first count values decreasing the number of bypassed elements in a differential delay line until an edge of the output clock signal is delayed relative to an edge of the input clock signal or the first count value reaches a first count final value if the first count value reaches the first count final value, a second count value is adjusting to decrease the number of bypassed elements in a single-ended delay line until the edge of the output clock signal is delayed relative to the edge of the input clock signal. A third count value is adjusted to decrease the delay of an interpolator until the edge of the output clock signal is no longer delayed with respect to the edge of the input clock signal.

Abstract: A sensor may include a clock generator configured to generate a clock. A receiver may be configured to receive signals from a control unit, and a transmitter they be configured to send signals to the control unit. In one implementation, the transmitter is configured to send a synchronization signal based on the clock. A period between a first edge and a second edge of the synchronization signal may be dependent on the clock and both edges are either rising or falling.

Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Abstract: A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: A channel estimation method, comprising when it is determined that in-band SRSs are required to be transmitted, acquiring the number of transmitting antenna ports and the number of layers of the currently transmitted DMRSs; calculating the difference of the number of the transmitting antenna ports and the number of layers of the currently transmitted DMRSs, and using the difference as the number of in-band SRSs that are required to be transmitted; transmitting in-band SRSs to a receiving-end device according to the number of in-band SRSs that are required to be transmitted, to enable the receiving-end device to perform channel estimation according to the currently transmitted DMRSs and the received in-band SRSs.

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract: The carrier phase of a carrier wave modulated with information symbols is recovered with a multi-stage, feed-forward carrier phase recovery method. A series of digital signals corresponding to the information signals is received. For each digital signal, a coarse phase recovery is performed to determine a first phase angle which provides a first best estimate of the information symbol corresponding to the digital signal. Using the first best estimate as input, a second stage of estimation is then performed to determine a second phase angle which provides an improved (second) best estimate of the information symbol. Additional stages of estimation can be performed. The multi-stage, feed-forward carrier phase recovery method retains the same linewidth tolerance as a single-stage full blind phase search method; however, the required computational power is substantially reduced. The multi-stage, feed-forward carrier phase recovery method is highly efficient for M-QAM optical signals.

Abstract: An adaptive filtering arrangement for providing bit-synchronous, time-dependent filtering of a time-varying analog input signal taking the form of a time-dependent low pass filter including at least one adaptive resistive element that exhibits a varying resistance value as a function of a time. The time-dependent low pass filter uses as a “control” input a modifying element responsive to a clock signal associated with the received signal for creating a time-varying control signal applied as an input to the adaptive resistive element. The time-varying control signal is created to be synchronous with a baud interval of a created output signal such that the instantaneous bandwidth of the time-dependent low pass filter is synchronous with the baud interval, exhibiting a relatively small bandwidth during a central portion of the baud interval and exhibiting a relatively large bandwidth during a transition from one baud interval to the next.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the synchronization signal, wherein both edges are either rising or falling, and the control unit taking the period as a basis for determining a clock for sampling data in the sensor signal.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.

Abstract: Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.

Abstract: A circuit can include an input section configured to store a data signal in response to phase shifted clocks to generate a plurality of sample values; an output section configured to store one of the sample values; and a logic section configured to selectively output one of the sample values to the output section in response to the sample values and a previous sampled value stored in the output section.

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract: A receiver device for receiving a signal that comprises one or more periodic features, the receiver device comprising: a detector configured to listen to the signal during at least a first reception phase, and to be triggered when a feature of the signal is received so as to determine the time of reception of that feature; and a receiver configured to process time-limited segments of the signal so as to derive information from features of the signal received during those segments, the receiver being configured to be dependent on the detector such that after the first reception phase the timings of the time-limited segments processed by the receiver are dependent on the time of reception determined by the detector.

Abstract: There is provided a signal transmission device including a first communication module including a first signal transmission unit for transmitting a first transmission signal having first amplitude to a second communication module through a predetermined transmission path, and the second communication module including a second signal transmission unit for transmitting a second transmission signal having second amplitude different from the first amplitude to the first communication module through the predetermined transmission path, and a transmission timing adjustment unit for adjusting a transmission timing of the second transmission signal by the second signal transmission unit so that a transition timing of the first transmission signal transmitted from the first communication module and a transition timing of the second transmission signal coincide with each other at a receiving end of the first communication module.