With Transition Detector Patents (Class 375/360)
  • Patent number: 10255964
    Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjun Shin, Su Yeon Doo, Taeyoung Oh
  • Patent number: 10084620
    Abstract: Aspects of the embodiments are directed to a data transmission receiver that includes a neural network circuit for resolving a received bit value. The data transmission receiver can be coupled to a data transmitter by a high speed data link. The neural network circuit can sample a bit value at multiple locations across the bit's unit interval. The neural network circuit can also sample bit values for neighboring bits to the interested bit at multiple sampling locations across unit intervals for the neighboring bits. The neural network circuit can determine the value of the interested bit from the samples of the waveform.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Yunhui Chu, Fan Chen, John Lang, Charles Phares
  • Patent number: 9998124
    Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 12, 2018
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Benton H. Calhoun, Aatmesh Shrivastava
  • Patent number: 9705665
    Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: July 11, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
  • Patent number: 9490965
    Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 8, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Inyeol Lee, Baegin Sung, Hanwoong Sohn, Shinje Tahk, Sun Woo Baek, Chandlee B. Harrell
  • Patent number: 9461812
    Abstract: Embodiments of various methods, devices and systems are described herein that correspond to an encoding scheme that can be used with various communication protocols for increased bandwidth over a single wire bus or a wireless single transmission channel. For example, a method of encoding a series of data bits to increase bandwidth may comprise selecting a data bit in the series of data bits, generating an inverted version of the selected data bit, positioning the inverted version of the selected data bit in a consecutive fashion with respect to the selected data bit to signify an edge of a clock signal, and transmitting the inverted version of the selected data bit and the series of data bits with each bit being transmitted in a single unique time slot.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 4, 2016
    Assignee: Blackberry Limited
    Inventor: Jens Kristian Poulsen
  • Patent number: 9281934
    Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 8, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Yu Song, Jan Christian Diffenderfer, Nan Chen, David Ian West, Paul Lawrence Viani
  • Patent number: 9088404
    Abstract: Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines. For a quadrature encoded signal, the input signal is separated into intermediary signals representing a real portion of and an imaginary portion. The processing circuit can then determine timing information from the real portion of and the imaginary portion. The intermediary signals can then be decimated according to a variable rate of decimation that is responsive to the determined timing information. The decimated intermediary signals are also filtered.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: July 21, 2015
    Assignee: Landis+Gyr Technologies, LLC
    Inventor: James Hilmer Glende, Jr.
  • Patent number: 9059718
    Abstract: A method for synchronizing an output clock signal with an input clock signal in a delay locked loop. A first count values decreasing the number of bypassed elements in a differential delay line until an edge of the output clock signal is delayed relative to an edge of the input clock signal or the first count value reaches a first count final value if the first count value reaches the first count final value, a second count value is adjusting to decrease the number of bypassed elements in a single-ended delay line until the edge of the output clock signal is delayed relative to the edge of the input clock signal. A third count value is adjusted to decrease the delay of an interpolator until the edge of the output clock signal is no longer delayed with respect to the edge of the input clock signal.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 16, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Toru Ishikawa
  • Publication number: 20150146831
    Abstract: A sensor may include a clock generator configured to generate a clock. A receiver may be configured to receive signals from a control unit, and a transmitter they be configured to send signals to the control unit. In one implementation, the transmitter is configured to send a synchronization signal based on the clock. A period between a first edge and a second edge of the synchronization signal may be dependent on the clock and both edges are either rising or falling.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Dirk Hammerschmidt, Friedrich Rasbornig, Bernhard Schaffer, Michael Strasser
  • Publication number: 20150117580
    Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 30, 2015
    Inventors: Inyeol Lee, Baegin Sung, Hanwoong Sohn, Shinje Tahk, Sun Woo Baek, Chandlee B. Harrell
  • Patent number: 9001869
    Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
  • Patent number: 8983012
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Publication number: 20150071393
    Abstract: A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Synopsys, Inc.
    Inventors: Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8963750
    Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: David Canard, Julien Delorme
  • Patent number: 8948320
    Abstract: A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 3, 2015
    Assignee: National Instruments Corporation
    Inventors: Baijayanta Ray, Nikhil A. Deshmukh
  • Publication number: 20150030112
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 29, 2015
    Inventors: George Alan Wiley, Chulkyu Lee
  • Patent number: 8917800
    Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Matsumoto, Naoki Mori, Takashi Yagi
  • Patent number: 8908818
    Abstract: A channel estimation method, comprising when it is determined that in-band SRSs are required to be transmitted, acquiring the number of transmitting antenna ports and the number of layers of the currently transmitted DMRSs; calculating the difference of the number of the transmitting antenna ports and the number of layers of the currently transmitted DMRSs, and using the difference as the number of in-band SRSs that are required to be transmitted; transmitting in-band SRSs to a receiving-end device according to the number of in-band SRSs that are required to be transmitted, to enable the receiving-end device to perform channel estimation according to the currently transmitted DMRSs and the received in-band SRSs.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lei Wan, Qiang Li, Mingyu Zhou, Yuan Xia
  • Patent number: 8890580
    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: November 18, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Teva Stone, Jihong Ren
  • Patent number: 8861647
    Abstract: The carrier phase of a carrier wave modulated with information symbols is recovered with a multi-stage, feed-forward carrier phase recovery method. A series of digital signals corresponding to the information signals is received. For each digital signal, a coarse phase recovery is performed to determine a first phase angle which provides a first best estimate of the information symbol corresponding to the digital signal. Using the first best estimate as input, a second stage of estimation is then performed to determine a second phase angle which provides an improved (second) best estimate of the information symbol. Additional stages of estimation can be performed. The multi-stage, feed-forward carrier phase recovery method retains the same linewidth tolerance as a single-stage full blind phase search method; however, the required computational power is substantially reduced. The multi-stage, feed-forward carrier phase recovery method is highly efficient for M-QAM optical signals.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: October 14, 2014
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Xiang Zhou
  • Patent number: 8854550
    Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Pyeong Kim, Han-Kyul Lim, Cheon-Oh Lee
  • Patent number: 8855256
    Abstract: An adaptive filtering arrangement for providing bit-synchronous, time-dependent filtering of a time-varying analog input signal taking the form of a time-dependent low pass filter including at least one adaptive resistive element that exhibits a varying resistance value as a function of a time. The time-dependent low pass filter uses as a “control” input a modifying element responsive to a clock signal associated with the received signal for creating a time-varying control signal applied as an input to the adaptive resistive element. The time-varying control signal is created to be synchronous with a baud interval of a created output signal such that the instantaneous bandwidth of the time-dependent low pass filter is synchronous with the baud interval, exhibiting a relatively small bandwidth during a central portion of the baud interval and exhibiting a relatively large bandwidth during a transition from one baud interval to the next.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: October 7, 2014
    Assignee: Receivers Unlimited LLC
    Inventors: John Sargent French, Ernest Eisenhardt Bergmann
  • Publication number: 20140294131
    Abstract: A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the synchronization signal, wherein both edges are either rising or falling, and the control unit taking the period as a basis for determining a clock for sampling data in the sensor signal.
    Type: Application
    Filed: October 1, 2008
    Publication date: October 2, 2014
    Inventors: Dirk HAMMERSCHMIDT, Friedrich RASBORNIG, Bernhard SCHAFFER, Michael STRASSER, WOLFGANG SCHERR
  • Patent number: 8848835
    Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Takayuki Shibasaki
  • Patent number: 8848851
    Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 30, 2014
    Assignee: IPGoal Microelectronics (SIChuan) Co., Ltd.
    Inventors: Zhaolei Wu, Guosheng Wu
  • Patent number: 8848850
    Abstract: Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventor: Wei-Lien Yang
  • Patent number: 8837657
    Abstract: A circuit can include an input section configured to store a data signal in response to phase shifted clocks to generate a plurality of sample values; an output section configured to store one of the sample values; and a logic section configured to selectively output one of the sample values to the output section in response to the sample values and a previous sampled value stored in the output section.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 16, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Mezyad Amourah
  • Publication number: 20140254732
    Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Shoichiro Sengoku, George Alan Wiley, Chulkyu Lee, Joseph Cheung
  • Patent number: 8831132
    Abstract: A receiver device for receiving a signal that comprises one or more periodic features, the receiver device comprising: a detector configured to listen to the signal during at least a first reception phase, and to be triggered when a feature of the signal is received so as to determine the time of reception of that feature; and a receiver configured to process time-limited segments of the signal so as to derive information from features of the signal received during those segments, the receiver being configured to be dependent on the detector such that after the first reception phase the timings of the time-limited segments processed by the receiver are dependent on the time of reception determined by the detector.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: September 9, 2014
    Assignee: Ubisense Limited
    Inventor: Andrew Martin Robert Ward
  • Patent number: 8824613
    Abstract: There is provided a signal transmission device including a first communication module including a first signal transmission unit for transmitting a first transmission signal having first amplitude to a second communication module through a predetermined transmission path, and the second communication module including a second signal transmission unit for transmitting a second transmission signal having second amplitude different from the first amplitude to the first communication module through the predetermined transmission path, and a transmission timing adjustment unit for adjusting a transmission timing of the second transmission signal by the second signal transmission unit so that a transition timing of the first transmission signal transmitted from the first communication module and a transition timing of the second transmission signal coincide with each other at a receiving end of the first communication module.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Tatsuo Shimizu, Takeshi Maeda, Uichiro Omae
  • Patent number: 8817195
    Abstract: An embodiment of the present invention provides a method for digital television demodulation, comprising using adjacent-channel power dependent automatic gain control (AGC) for the digital television demodulation, wherein an AGC technique takes into account a total power as well as power of adjacent channels to control gain of a gain control amplifier.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Parveen K. Shukla, Bernard Arambepola, Thushara Hewavithana, Sahan Gamage
  • Patent number: 8817933
    Abstract: Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: August 26, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Darshini H. Mehta, Alan Campbell
  • Patent number: 8811557
    Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 19, 2014
    Assignee: NXP B.V.
    Inventors: Gerrit Willem den Besten, Arnoud Pieter van der Wel
  • Patent number: 8812063
    Abstract: In a signal-based gain control scheme, one or more gain levels used for processing signals are selected based on characteristics of previously received signals. For example, different gain levels may be used to receive sets of signals whereupon certain characteristics of the received sets of signals are determined. One or more gain levels are then selected based on these characteristics whereby another signal is processed based on the selected gain level(s). In some aspects, the signal-based gain control scheme may be employed to facilitate two-way ranging operations between two devices. For example, leading edge detection may involve determining a characteristic of a received signal, determining a threshold based on the characteristic, and identifying a leading edge associated with the received signal based on the threshold. In some aspects, the signal-based gain control scheme may be employed in an ultra-low power pulse-based communication system (e.g., in ultra-wideband communication devices).
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 19, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Petru Cristian Budianu, David Jonathan Julian, Amal Ekbal
  • Patent number: 8811515
    Abstract: To realize quick adaptation to a communication link between a transmitter and a receiver by using two different frequency carriers. A receiver detects a preamble from a transmission bit string. When determining that a total sum of the number of modified bits exceeds a certain threshold in a range of a payload following the preamble (when detecting that a reception state of a communication link has been degraded), the receiver issues, to a transmitter, a request for changing a transmission parameter (four parameters may be used for enhancement/lowering) for the transmission bit string by using a communication link, which is a relatively-low-frequency carrier. On the other hand, the transmitter receives the request for change, and executes the request for changing the transmission parameter for the transmission bit string while maintaining transmission of a payload in the transmission bit string.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yasuteru Kohda, Daiju Nakano, Kohji Takano
  • Patent number: 8804888
    Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 12, 2014
    Assignee: Ensphere Solutions, Inc.
    Inventors: Hessam Mohajeri, Bruno Tourette, Emad Afifi
  • Patent number: 8781051
    Abstract: A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 15, 2014
    Assignee: NXP, B.V.
    Inventors: Massimo Ciacci, Remco Cornelis Herman van de Beek, Ghiath Al-kadi
  • Patent number: 8774337
    Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
  • Patent number: 8767900
    Abstract: A signal transition detection circuit is provided. The signal transition detection circuit comprises a counter module, a DAC, a comparator and a digital sampling module. The counter module generates a digital step signal. The DAC converts the digital step signal into an analog input signal and transmits it to an under-test circuit such that the under-test circuit generates an output signal transiting from a first stable level to a second stable level, wherein a transition section is located between the first and the second stable level. The comparator receives and compares the output signal with a default value to generate a normalized output signal. The digital sampling module samples the normalized output signal to retrieve impulses such that when the number of the impulses is accumulated to be larger than a reference value, a corresponding step of the digital step signal is determined to be a transition point.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Test Research, Inc.
    Inventors: Yu-Chen Shen, Kuei-Chang Yang
  • Patent number: 8755450
    Abstract: To realize quick adaptation to a communication link between a transmitter and a receiver by using two different frequency carriers. A receiver detects a preamble from a transmission bit string. When determining that a total sum of the number of modified bits exceeds a certain threshold in a range of a payload following the preamble (when detecting that a reception state of a communication link has been degraded), the receiver issues, to a transmitter, a request for changing a transmission parameter (four parameters may be used for enhancement/lowering) for the transmission bit string by using a communication link, which is a relatively-low-frequency carrier. On the other hand, the transmitter receives the request for change, and executes the request for changing the transmission parameter for the transmission bit string while maintaining transmission of a payload in the transmission bit string.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yasuteru Kohda, Daiju Nakano, Kohji Takano
  • Patent number: 8723651
    Abstract: A method for detecting a pattern in a signal according to one embodiment includes determining a time between symbol transitions in a signal derived from a radio frequency signal; determining ratios of relational times between consecutive symbol transitions; and comparing a sequence of the ratios to a target pattern for determining whether the sequence corresponds to the target pattern. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 13, 2014
    Assignee: Intelleflex Corporation
    Inventor: Dean Kawaguchi
  • Patent number: 8711995
    Abstract: Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines. For a quadrature encoded signal, the input signal is separated into intermediary signals representing a real portion of and an imaginary portion. The processing circuit can then determine timing information from the real portion of and the imaginary portion. The intermediary signals can then be decimated according to a variable rate of decimation that is responsive to the determined timing information. The decimated intermediary signals are also filtered.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 29, 2014
    Assignee: Landis+ Gyr Technologies, LLC
    Inventor: James Hilmer Glende
  • Patent number: 8705669
    Abstract: In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: April 22, 2014
    Assignee: BlackBerry Limited
    Inventor: Martin Kosakowski
  • Patent number: 8675776
    Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Dragos Dimitriu
  • Patent number: 8666007
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 4, 2014
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 8667320
    Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Daniel J. Sisolak, Kenneth H. Cooper
  • Patent number: 8660172
    Abstract: A pulse signal receiving apparatus may include a reception unit that receives a pulse signal modulated by a double-edge modulation scheme, a measurement unit that measures an edge interval of the pulse signal, which has been received by the reception unit, a detection unit that detects a deviation of the edge interval, which has been measured by the measurement unit, for a pulse-width reference value indicating a reference value of a width of the pulse signal, a correction unit that corrects the edge interval, which is to be measured next by the measurement unit, by using the deviation, which has been detected by the detection unit, and a decoding unit that decodes the pulse signal, of which the edge interval has been corrected by the correction unit, so as to output a digital signal.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 25, 2014
    Assignee: Yokogawa Electric Corporation
    Inventors: Yoshio Yoshida, Noriaki Kihara
  • Patent number: 8638895
    Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmad Chini, Mehmet Tazebay, Scott Powell
  • Patent number: 8638842
    Abstract: Provided is an equalization device which receives a signal transmitted from a transmission side of the signal as an input signal, and equalizes the deterioration of a wave shape of the received input signal, wherein a bit value indicated by the input signal is judged in accordance with a clock on the basis of the wave shape of the input signal. From judged signals which result from the judgment and which are composed of a plurality of bits, a two-bit transition signal is detected so that the two-bit transition signal has two adjacent bit values having the same value, and bit values located before and after the two adjacent bit values are different from the bit value of the two adjacent bit values, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: January 28, 2014
    Assignee: NEC Corporation
    Inventor: Hideyuki Hasegawa