Abstract: The present technology relates to protocols relative to utility meters associated with an open operational framework. More particularly, the present subject matter relates to protocol subject matter for advanced metering infrastructure, adaptable to various international standards, while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field. The present subject matter supports meters within an ANSI standard C12.22/C12.19 system while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field, all to permit cell-based adaptive insertion of C12.22 meters within an open framework. Cell isolation is provided through quasi-orthogonal sequences in a frequency hopping network. Additional features relate to apparatus (both network and device related) and methodology subject matters relating to uplink routing without requiring a routing table.

Abstract: A system for synchronizing data after they are collected and stored locally in sensor units in a distributed sensor system, so that wired or wireless communication is not required during a data-collection session. Each sensor unit has a local clock providing local-clock times before and after a data-collection session, and a data processor uses its local clock or a sensor unit's local clock as the reference to compute each sensor unit's time-scaling factor, which is the ratio of the elapsed reference local-clock time and the elapsed local-clock time. The data processor uses the time-scaling factor to convert each sensor unit's local-clock data-sampling times to the reference local-clock data-sampling times, and the data processor subsequently interpolates sensor data to approximate simultaneous sensor-data values at desired reference local-clock times. A physical-activity monitoring system can use this synchronization method to reduce the size, power consumption, and cost of the sensor units.

Abstract: A system for self-correcting the multiphase clock includes a transmitter, a receiver, a random code generator and a controller. The random code generator generates a random code stream, the random code stream is transformed to the high-speed serial data by the transmitter, the high-speed serial data are sent into the receiver and transformed to the parallel data by the receiver, the parallel data are sent into the controller, the controller stores the random code stream and detects the probability of the bit error of the parallel data output by the receiver. According to the test result of the bit error, the controller generates a phase adjustment control signal for adjusting the phase uniformity of the multiphase clock. Also, a method for self-correcting the phase uniformity of the multiphase clock of the present invention effectively makes up the sampling bit errors caused by the phase nonuniformity of the multiphase clock.

Abstract: The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the associated receiving part to its clock.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: Methods having corresponding apparatus and computer-readable media comprise: receiving an estimated frame index, and an estimated symbol index, for a time-sliced OFDM signal; identifying a plurality of possible frame indexes, and a plurality of possible symbol indexes, based on the estimated frame index and the estimated symbol index; selecting a plurality of possible forward error correction code offsets based on the possible frame indexes and the possible symbol indexes; and selecting one of the possible frame indexes, and one of the possible symbol indexes, based on the possible forward error correction code offsets and a SYNC byte of the time-sliced OFDM signal.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of analog values stored in at least one of a plurality of periodic signal generators. The frequency switching local oscillator signal is generated by selecting an output of a one of the plurality of periodic signal generators.

Abstract: A high speed transmission system transfers data streams over a plurality of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and phase is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.

Abstract: A time stamp adding device includes: PCR_PID detecting means for detecting a PCR_PID included in a PMT by searching TS packets included in a TS from the head of the TS including TS packets having no time stamp, input from the outside and transmitted in a MPEG2-TS format and analyzing the resulting PMT; PCR detecting means for detecting values of PCRs included between the head of the TS and the PMT and position information of the PCRs and detecting values of all PCRs in the TS packets between the PMT and the tail of the TS and position information of the PCRs in the TS; time interval calculating means for calculating a time interval for adding a time stamp and a value of the time stamp based on the PCR values; and time stamp adding means for adding the time stamps to the TS packets having no time stamp based on the time interval.

Abstract: Apparatus for serial communication using embedded clock signals includes a data divider for dividing a data stream into odd-numbered and even-numbered data streams; a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signals by pulse amplitude modulating the odd-numbered and even-numbered data streams and, when an external clock is input, inverting polarities of the pulse amplitude modulated odd-numbered and even-numbered data streams; a clock-embedded signal recovery unit for recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively, and recovering synchronization information of the clock by detecting when amplitude polarities of the odd-numbered and even-numbered embedded clock signals are inverted; and a data integrator for integrating the odd-numbered and even-numbered data streams and supplying the result as the data stream.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: A method for the synchronization of a radio receiver, comprising an estimation of the moment when a pulse (11, 17) is received (11, 17), performed from the moment when a previous pulse was received. The estimated moment is compared with the real moment when the pulse (21, 27) is received in order to validate an association of pulses with values of a code recorded in the receiver (31, 37). A moment for the beginning of transmission of a symbol is thus deduced, enabling the receiver to be synchronized in relation to the transmitted radio pulse sequence.

Abstract: Provided are a method and system for determining system time in a satellite based cable data communication system. The system includes a satellite modem termination system configured to transmit data frames to a receiver in a predetermined symbol rate. Each frame includes a corresponding number of symbols and has a time stamp (i) indicative of the frame's time of transmission and (ii) positioned within the frame at a location common to all of the frames. The method includes receiving at least two consecutively transmitted data frames within the receiver and registering the time stamp of the first received data frame within the receiver to produce a first time stamp. Also, the time stamp of the second received data frame is registered within the receiver to produce a second time stamp. The time of transmission of the second transmitted data frame is updated, wherein the updating is a function of the first time stamp, the second time stamp, the corresponding number of symbols, and the symbol rate.

Abstract: In a transmitter of an orthogonal frequency division multiple access (OFDMA) system, a subchannelization module generates an OFDMA symbol with data on multiple subcarriers, from received incoming data packets. An input controller applies a first formula to determine a first index of each received data packet, and stores each received data packet at an address in memory according to its first index. An output controller applies a second formula to determine the nature of the data to be carried by each subcarrier in the OFDMA symbol and, if said second formula indicates that a data subcarrier should be output, reads the data from said memory, wherein said data packets are stored in said memory at addresses such that the data can be read out at least piecewise sequentially when generating the OFDMA symbol.

Abstract: A method is provided for offsetting a reference frequency of a quadrature reference clock signal. A quadrature reference clock (110) generates the quadrature reference clock signal at the reference frequency, while a quadrature variable offset clock (130) generates a quadrature clock signal at a base offset frequency based on a base offset value it receives from a control circuit (560). The base offset value can be determined in many ways, including reading it from a local memory (910) or receiving it from a remote device (1010). A polyphase mixer (140) performs a polyphase mixing operation between the quadrature reference clock signal and the offset clock signal to generate an agile clock signal having an agile clock frequency equal to the reference frequency plus the base offset frequency. If desired, the method can revise the offset frequency based on actual conditions and determine a corresponding revised offset value (920, 1020).

Abstract: A translation circuit for mediating between a fiber-optic controller chip and a host device. The translation circuit may be on a fiber-optic transponder. The controller chip includes a phase locked loop that outputs a short synchronization signal when a hunting frequency passes through a target data signal frequency while hunting for a data signal and outputs a synchronization signal when the phase locked loop is locked onto a data signal. The translation circuit distinguishes between the synchronization signals and generates a lock signal when the phase locked loop is locked onto a data signal, but does not when the hunting frequency passes through the target data signal frequency. The lock signal may be used by a host device into which the fiber-optic transponder has been in installed. Errors from misinterpreted signals can thus be mitigated.

Abstract: A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the timing information, or conversely, propagated by request via a training sequence. All system components other than the master system component do not require a separate clock input, since frequency coherency is maintained by internal time bases that have been calibrated to the frequency of the propagated timing information.

Abstract: A system and method for bit eye center determination is provided. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively offsets the selected samples based on state criteria and the number of transitions in each set of samples, accumulates the offset samples and averages the result to determine the center of the bit eye. The system and method also provides the ability to locate the eye center even in the case of noise in the system, whether the noise is random or deterministic, including odd/even noise.

Abstract: Systems, devices, processors, and methods are described for joint detection of frequency and unique word (UW) location(s) for burst transmissions. Embodiments receive a wireless signal. Frequency detection is performed, resulting in multiple possible frequency correlation peaks. A subset of the correlation peaks are each used to perform trial frequency corrections, thereby generating a set of trial sequences. A UW correlation is performed on each of the trial sequences to generate a maximum UW correlation value for each trial sequence. The UW correlation value and the frequency correlation peak value are weighted and combined to generate a joint detection correlation value. The trial sequence having largest joint detection correlation value may indicate the correct transmission frequency and UW location. The jointly detected information may then be used to identify the frequency and start time of the burst transmission, which may then be demodulated, decoded, etc. to recover its payload data.

Abstract: A system and method for training a data path for parallel data transfer are presented. A first part of the method includes determining a delay setting for each coupling of a plurality of parallel couplings between a first device and a second device. The delay setting for each coupling may substantially align reception of signals transmitted from the first device to the second device on each coupling with a system clock. A second part of the method includes determining the alignment of the plurality of parallel couplings relative to each other. A timing adjustment for one or more of the plurality of parallel couplings may then be determined, whereby after the timing adjustment, signals transmitted from the first device to the second device on the plurality of couplings are received by the second device in alignment with each other.

Abstract: Provided is a symbol synchronization apparatus and method of a passive REID reader. The symbol synchronization apparatus includes: an edge clock detector generating edge clocks by detecting phase inversion positions of a received signal; a preamble detector detecting a preamble section by analyzing the generation times of the edge clocks; a symbol decision time extractor extracting a symbol decision time by averaging distances between the edge clocks consecutively generated in the preamble section, when the preamble section is detected; and a symbol decider deciding a symbol by analyzing the magnitude of the received signal, when the time reaches the symbol decision time.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: A packet trace is received. The packet trace is transformed into a sequence of pulse signals in a temporal domain. The sequence of pulse signals in the temporal domain is transformed into a sequence of pulse signals in a frequency domain. Peaks are detected within relevant frequency bands in the sequence of pulse signals in the frequency domain. A fundamental frequency is identified within the peaks. The fundamental frequency, which represents the TCP flow clock, is returned.

Abstract: Clock synchronization resistance is improved against selectivity fading without degrading the stability of clock phase synchronization control. Clock phase detector 7, which forms part of a clock reproduction PLL, is preceded by orthogonal component equalizer 6 for removing only orthogonal component interference wave not affecting the clock regeneration, thereby assuring an opening of an eye pattern and maintaining the gain of clock phase detector 7 without erasing the clock phase information. Accordingly, even when inter-symbol interference is caused in a received signal by selectivity fading or the like, part of the interference component can be erased to keep the opening of the eye pattern wide. Thus, the clock synchronization resistance can be improved against the selectivity fading without degrading the stability of the clock phase synchronization control.

Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

Abstract: A clock synchronization circuit includes a clock generation circuit generating a sampling clock for sampling a received signal from an output of a local oscillator, a phase error detection circuit finding a phase error between sampling timing of the sampling clock and ideal sampling timing, and a timing correction circuit finding a correction quantity to correct a frequency error between a frequency of the sampling clock and a frequency of the ideal sampling timing and the phase error every sampling timing of the sampling clock, and outputting a sampling value interpolated according to the found correction quantity.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: A system includes first and second wireless nodes having a clock with plural times, a wireless transceiver, and a processor cooperating with the transceiver to transmit and receive packets. The second node transceivers wirelessly communicate with the first or other second node transceivers. The second nodes include a Kalman filter with an output, plural filter gains, and an input representing the difference between: about the time of the clock when a received packet should have ideally been received, and a time when the received packet was actually received as measured by the clock. A circuit provides dynamic adjustment of the filter gains. The Kalman filter output estimates the difference between the time of the receiving node clock and a corresponding one of the times of the transmitting node clock. The second processor cooperates with the Kalman filter output to adjust the times of the receiving node clock.

Abstract: A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 1OG-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.

Abstract: The A/D converter changes sampling timing of a received signal in a synchronization acquisition mode and a synchronization tracking mode. The A/D converter generates an internal clock of a sampling frequency eight times a symbol rate under the control of the clock control unit in the synchronization acquisition mode. On the other hand, in the synchronization tracking mode, the A/D converter generates an internal clock with a symbol point and one each point before and after the symbol point as sampling timing under the control of the clock control unit. The A/D converter further corrects the sampling timing of the symbol point based on the squares of the maximum value of a correlation value between the received signal and a reference signal and the absolute values of correlation values before and after the maximum value.

Abstract: For time synchronization of a data stream with multi-channel additional data and a data stream with data on at least one base channel, a fingerprint information calculation is performed on the encoder side for the at least one base channel to insert the fingerprint information into a data stream in time connection to the multi-channel additional data. On the decoder side, fingerprint information are calculated from the at least one base channel and used together with the fingerprint information extracted from the data stream to calculate and compensate a time offset between the data stream with the multi-channel additional information and the data stream with the at least one base channel, for example by means of a correlation, to obtain a synchronized multi-channel representation.

Abstract: According to a method for generating a system time clock in a receiving device for digital packetized elementary data streams (E), the packetized elementary data streams (E) being generated in a transmitting device by sampling at a sampling frequency (fsample) synchronized by a system time clock of the transmitting device, the sampling frequency (fsample) of one data stream is determined in the receiving device, and the program clock reference counter is synchronized with the data stream's sampling frequency.

Abstract: In an electronic system, a frequency modulator manages clock signals for electromagnetic interference (EMI) reduction. The illustrative frequency modulator comprises a core oscillator, and a clock divider coupled to the core oscillator that modulates frequency of the core oscillator and deterministically spreads clock spectral components of a digital clock signal whereby electromagnetic interference (EMI) is reduced. The frequency modulator further comprises a circuit coupled to the clock divider that receives the digital clock signal, combines the digital clock signal with a data bitstream for transmission across an isolation barrier, and resynchronizes to the digital clock signal.

Abstract: A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communication signal having a signal frame for synchronization by using a pair of correlation processing windows of a variable size; a correlation unit for performing self correlation processing to the self correlation processing signals extracted; a matching unit for performing pattern matching processing between the correlation-processed signal, obtained through the self correlation processing, and a reference signal; and a computation unit for estimating the base point of the signal frame and an offset of the digital communication signal with respect to the base point, based on distance information of the pattern matching processing.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: There is provided a transmission system in which a data sequence is transmitted. The transmission system includes a transmitter that generates a transmission signal by converting pieces of data included in the data sequence into data waveforms each of which has (i) a level signal whose signal level is determined by a value of a corresponding one of the pieces of data and (ii) a timing edge indicating a timing to obtain the level signal, and transmits the generated transmission signal, and a receiver that detects the signal level of each of the data waveforms of the received transmission signal at the timing designated by the timing edge of the each data waveform, and outputs a data value corresponding to the detected signal level.

Abstract: The present invention relates to a method for measuring radio channel quality in a radio communication system. In the method a modulated signal is received over a communication channel. The modulated signal has been modulated by using modulation parameters. A decoder decodes (305) the modulated signal and forms decoded data. The decoder creates (306) a decoder performance indicator (PS) that depends on the decoded data. Then a radio channel quality indicator (RCQI) is created, the radio channel quality indicator being essentially independent of the modulation parameters.

Abstract: A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract: A phase synchronization method uses a removal path for removing an error component contained in an input signal and a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path. The removal path includes an averaging section. The averaging section includes a shift register and an obtaining unit. The shift register stores as many data as the maximum number of data to be averaged and successively receives processing data from which the error component has been extracted in the removal path. The obtaining unit obtains, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.

Abstract: A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received

Abstract: A quantized channel rate and corresponding rate multiplier is determined on a transmitter-side of a communication system based on a measured minimum required bandwidth. In certain embodiments, the quantized data rate may be an integer multiple of the system's reference clock. The determined rate multiplier is then transmitted to the receiver-side at a default data rate prior to or near the beginning of a data transmission session, such as upon initialization. Prior to transmission, the data stream may be padded with some determined amount of null data such that the actual transmitted data rate is approximately equal to the quantized channel rate, and the receiver-side can readily recover the data clock using its known reference clock and the previously-provided rate multiplier.

Abstract: A frame number detecting device includes: a symbol counter that receives a received signal including frames each of which is formed of a predetermined number of symbols, and outputs a count value as a symbol number for each of the symbols by incrementing the count value by one every time one symbol is inputted, each of the frames including a frame synchronization signal including a part obtained by shifting a frame synchronization signal of a different frame on a symbol-by-symbol basis according to a predetermined rule; a sequence storage that stores a synchronization sequence based on at least one of the frame synchronization signals included in the received signal, and a pattern matching unit that performs pattern matching between the synchronization sequence stored in the sequence storage and the received signal.

Abstract: In a packet receiving method and device which convert a voice packet received into a voice, a receiving packet buffer temporarily stores a voice packet received; a plurality of parameter information monitors respectively determine different buffer adjustment values for determining a buffering amount of the receiving packet buffer based on one or more pieces of parameter information obtained from the voice packet temporarily stored; a buffer adjustment value determiner determines a receiving buffer adjustment value from the plural buffer adjustment values; and a buffer controller controls the buffering amount based on the receiving buffer adjustment value.

Abstract: A time synchronized measurement system has a master device and a slave device. The master device and the slave device each have a time measurement device for assigning a corresponding time of sending and/or receiving a piece of measurement information. The master device also has a reference clock pulse-generating device for transmitting a reference clock signal to the slave device. The reference clock signal is modulated by a piece of information on a common time basis for the master device and the slave device.

Abstract: A clock recovery circuit includes a frequency detection module and a correction module. The frequency detection module detects frequency offset information between a received signal and a reference clock according to a phase difference between the received signal on which timing information for reproducing the received signal is superimposed and a recovery clock. The correction module corrects a phase difference between the received signal and the recovery clock according to the frequency offset information detected by the frequency detection module.

Abstract: A system and method for synthesizing a frequency using a multi-phase oscillator. A state machine operating on one of the phases of the oscillator computes, based on a pair of input integers, a phase select vector that indicates when a particular phase of the multi-phase oscillator should be selected when a transition of the waveform of the output frequency is needed. The phase select vector is then re-timed to form a retimed phase vector so that each phase select signal is in phase with signal it is designed to select. The signals in the retimed phase vector then can be combined to create the output frequency directly or can be used to select the corresponding phase of the multi-phase oscillator, if more accuracy is desired. In one embodiment, the multi-phase oscillator is a rotary traveling wave oscillator which provides highly accurate multiple phases.

Abstract: A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.