Abstract: A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. Each center which is not within an associated correction window is discarded. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the centers between each pair of consecutive edges which are not discarded. In one embodiment, a current correction window size is varied based on whether an immediate previous center was within an immediate previous correction window. When the immediate previous center is discarded because it is not within the immediate previous correction window, the current correction window size is enlarged.

Abstract: The present invention relates to a clock recovery system which allows for stable clock information to be extracted from a serial data stream with defined jitter characteristics. The clock recover circuit is comprised of a flip flop which is used for receiving the serial data stream and for outputting stable clock information. A sampling clock circuit is coupled to the flip flop for sending a signal which reflects a center area of each bit period in the serial data stream when a transition occurs in the serial data stream.

Abstract: A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.

Abstract: The invention provides a parallel to serial data converter wherein the frequency of a basic clock pulse signal to be applied for driving can be reduced to one half with respect to a same data rate and consequently the operation speed required for a circuit in a preceding stage can be reduced, and a bad influence of noise such as, for example, jitters of serial data is eliminated. In the parallel to serial data converter, a clock pulse signal having a frequency f/2 Hz equal to one half the data rate of parallel data which is f bps is used as a basic clock pulse signal, and an inverted pulse signal is produced from the basic clock pulse signal. Then, a rising or falling edge of each pulse of the basic clock pulse signal and a rising or falling edge of each pulse of the inverted pulse signal are detected, and a byte clock pulse signal having a frequency equal to that of the parallel data is produced by logical ORing of such two edge detection outputs and is supplied to a multiplexer.

Abstract: A clock recovery circuit employing a phase-locked loop design includes an N-to-1 multiplexer (MUX) coupled to a series of N latches which allows data to sampled at a frequency N times that of the clock. Incoming data is latched by each of the N latches, where each latch is clocked at a different phase of the clock signal such that the phase of the clock provided to the nth latch is shifted nT/N, where T is the period of the clock and n is an integer from 1 to N. The output terminals of the series of N latches are coupled to associated ones of input terminals of the N-to-1 MUX. The selection of MUX input terminals is controlled by the clock signal such that the incoming data signal is reconstructed at the output terminal of the MUX. In this manner, the incoming data signal is effectively sampled at N times the clock speed.

Abstract: A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.

Abstract: It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).

Abstract: A clock extraction circuit for retiming a ternary data stream derives first and second binary streams corresponding respectively to the positive and negative going portions of the ternary data stream These binary streams are combined to provide a further binary stream which is retimed to a local clock whereby to generate a reference stream for retiming the first and second binary data streams to said reference stream. The retimed binary data streams are combined to generate a retimed ternary data stream.

Abstract: The present invention relates to a circuit for restoring bits transmitted by an asynchronous signal, including a comparator of the signal level with a reference level; a sampling circuit supplying several samples of the comparator output for each time interval corresponding to a bit; a circuit for determining a succession of windows, each of which corresponds to a bit; an acquisition circuit receiving the samples and supplying, for each window, the number of samples having a first logic value, the number of sample transitions, and the value of a border sample of an adjacent window; and an estimation circuit for correcting the reference level and the alignment of the windows on the bits according to the outputs of the acquisition circuit.

Abstract: A clock recovery unit for recovering a clock embedded in a data communication is disclosed. The clock recovery unit includes an oscillator (50) operating at a frequency close to that of the clock embedded in the data communication. The clock recovery unit also includes an edge detector (30) that produces a synchronization pulse with each transition in the data communication. The edge detector is coupled to the oscillator to force a transition in the oscillator in synchronization with the synchronization pulse produced by the edge detector. A start-up latch (10) that starts and stops the oscillator also forms part of the clock recovery unit. The start-up latch starts the oscillator at the beginning of the data communication, with no preamble bits required. For low-power consumption in stand-by mode, a counter (40) coupled to the start-up latch stops the oscillator after data has been determined not to be present for a preset period of time.

Abstract: A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Abstract: In a data bus with m data bits, electromagnetic interference is produced by polarity switching the data on that data bus. When two consecutive data items result in a change of over half of the data bits, the polarity of the second data item is switched, and a polarity signal is correspondingly switched on the data bus. When the data is received, it is restored to its original polarity by adjusting the polarity of the received data according to the signal on the polarity line. In this way, the total number of bit transitions between any two data items is reduced to a maximum of m/2.

Abstract: A digital data recovering apparatus which includes an edge detector, a threshold comparator, a position address generator, a position memory, a maximum position detector, a new position generator and a recovered data detector. The digital data recovering apparatus ensures that the desired data and clock reference can be recovered by exactly synchronizing the input data on a communication path, including a noise and/or jitter component.

Abstract: A method and apparatus for recovering clock and data signals from a Manchester code is provided. The present invention uses a phase lock loop with a digital delay line wherein an adjustable delay is introduced into the Manchester coded signal for synchronizing the coded signal with the local clock of the decoding apparatus. This delaying technique enables the present invention to successfully receive Manchester coded signals having substantial jitter. The present invention also conserves energy by reducing power consumption when no signals are present.

Abstract: In a burst signal detecting apparatus, a first circuit is provided to detect a falling edge in a burst signal to generate a first pulse signal when a low level of the burst signal continues for a time period after the falling edge is detected in the burst signal. Also, a second circuit is provided to detect a rising edge in a burst signal to generate a second pulse signal when a high level of the burst signal continues for the time period after the rising edge is detected in the burst signal. The first pulse signal is logically combined with the second pulse signal to generate a burst signal detection signal. Each of the time periods is smaller than a minimum time period of one bit of the burst signal. The pulse width of each of the first and second pulse signals is longer than a time period of a predetermined number of bits of the burst signal.

Abstract: A dual clock tracking decoder for use in a local station of a token ring local area network extracts the mostly repetitive bit-cell transitions corresponding to the imbedded clock of a received phase encoded message from which a short term and a long term moving average estimate is made of the clock transitions relative to a local stable clock. The short term moving average adjusts rapidly to short term jitter and is used to sample the received phase encoded message twice each bit-cell and generate an intermediate phase encoded message that is resynohronized with a clock derived from the long term moving average of the estimated imbedded clock transition and having a rate that is twice the bit-cell rate of the received phase encoded message. This provides a mechanism for sampling the states of the incoming message with a clock that is adaptive to fast short term jitter while restoring an imbedded clock that is only responsive to slow longer term jitter.

Abstract: Briefly, in accordance with one embodiment of the invention, a refined timing recovery circuit for retiming a recovered data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: A receiver for NRZ data does not require a separate transmission media for the clock. Rather, a clock recovery circuit is included in the receiver capable of recovering the clock based on transitions detected in the NRZ data alone. The clock recovery circuit comprises an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream. Reference clock generation circuity generates a plurality of reference clock signals shifted in phase with respect to one another. Phase quantizing circuitry is responsive to the edge detection signals and the plurality of reference clock signals. The phase quantizing circuitry generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals.

Abstract: An optical parallel receiving module receives optical signals transmitted in parallel in a plurality of channels by using optical fibers. The optical parallel receiving module includes photo-electric conversion elements for converting received signals which are electric signals as received signals, limiter amplifiers for comparing the received signals and a threshold level, and data decision circuits for recognizing data at a timing in every period of received data using a reference clock.

Abstract: A synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium includes a binary-valued signal detector for translating RF signals into binary-valued signals, an edge detection circuit for extracting edge portions of the binary-valued signals, a counter for counting the number of clocks generated by an external source between the edge portions, a number of latch circuits for holding successive clock count values between the edge portions and for successively shifting the clock values held by them, value coincidence circuits for comparing the numbers of clocks between transitions of the synchronization patterns and the clock count values held by the counter and the latch circuits and for outputting a signal indicating a coincidence in case of complete coincidence between the numbers of clocks and the clock count values and an AND circuit for taking a logical sum of the outputs of the value coincidence circuits and the edge detector for pr

Abstract: A multi-valued signal decoding circuit is disclosed which has a circuit for detecting a bit synchronization signal included in the multi-valued data signal transmitted in the form of a packet signal, a circuit for detecting by this detected output a timing of a transition of the bit synchronization signal, a circuit for sampling and holding the bit synchronization signal by using sampling pulses generated on the bases of said timing, and a circuit for decoding the multi-valued data signal by using decoding reference voltages formed on the basis of the sampled and held level.

Abstract: A data sampling circuit and method is provided for a burst mode communication system. The circuit is an entirely digital circuit for reliably sampling an incoming stream of data for automatically adjusting to variations in data stream clock rates and phase variations in the incoming data. The circuit includes a delay line, with a plurality of serially coupled taps, each tap having a variable delay. A first aspect of the invention includes increasing the delay time until the delay line captures at least one full data cell, but preferably two, of the incoming data stream (i.e., signal levels over at least one full clock period, defined by two transitions of the data stream), thereby aligning the receiving circuit with the frequency of the data stream clock. A second aspect of the invention includes outputting data from a tap that is selected to be midway between two regions of transitions of the incoming data stream, thereby aligning the receiving circuit with the phase of the data stream clock.

Abstract: A phase detector detects a transition edge on a received data signal and generates a pump-down reference pulse and a pump-up, variable width pulse indicative of phase to synchronize a local clock with the received data signal. The variable width pulse overlaps in time with the reference pulse. The reference pulse is subtracted from the variable width pulse, and the resulting difference signal is supplied in an integrated format to a voltage controlled oscillator (VCO) that controls the frequency of the local clock. When the phase detector is balanced, the variable width pulse and the reference pulse substantially cancel out one another, providing for relatively reduced jitter for the local clock.

Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the chock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 2 -nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.

Abstract: A system and method for the transmission and recovery of asynchronous data. For instantaneous synchronization, the receiver is equipped with a high frequency timing base which has a far higher frequency than either the data-generating or transmitting rate. The receiver clock is instantly synchronized upon detection of the first transition of the incoming data packet. Data packet verification can be conducted and data processed with minimal loss of data.

Abstract: A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the center between each pair of consecutive edges. For example, the center between each pair of consecutive edges is determined by counting a number of cycles of an over sampling signal which occurs between each pair of consecutive edges to obtain a bit width. The bit width is divided in half and the result added to an edge phase value to obtain a value for the center. Also, the phase of the extracted clock signal may be varied based on the center between each pair of consecutive edges as follows. An amount a plurality of centers varies from a center of the extracted clock signal is averaged to produce a phase error.

Abstract: The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted.

Abstract: A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.

Abstract: A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data.

Abstract: The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted.

Abstract: According to the present invention, synchronization between two or more asynchronous devices or systems is accomplished according to the clock edges of the asynchronous devices or systems rather synchronization through sampling of the clock frequencies of the asynchronous devices or systems. Because synchronization is dependent on the clock edges rather than frequencies, there are two readily apparent advantages. First, it is no longer necessary to sample data in order to determine frequencies of the asynchronous devices or systems. Second, the data transmitted from a transmitter device, such as a microprocessor, to a receiver device, such as a printer, can be assured of being stable data before being received by the receiver device. Because the data received by the receiver device is not in transition or otherwise meta-stable, it is valid, uncorrupted data.

Abstract: Briefly, in accordance with the embodiment of the invention, a refined timing recovery circuit for retiming a colored data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: A carrier sensing circuit coupled to a receiving amplifier, measures the frequency of a phase shift modulated carrier signal by counting a predetermined number of the pulses for a measured interval whose duration is determined by counting a first clock count value. A demodulator coupled to the amplifier, detects when the spacing between the edges of the square wave pulses changes in response to the phase shift modulation. The demodulator measures first intervals between consecutive rising edges of the received signal, by counting clock pulses for a second selected interval whose duration is determined by a second selected count value. The demodulator further measures second intervals between consecutive falling edges of the received signal by counting clock pulses for a third selected interval whose duration is determined by a third selected count value.

Abstract: A method and apparatus for extracting digital information (111) from an asynchronous data stream (101) is achieved by providing a data stream (101) that is clocked at a data stream clock rate (210). A sampled data stream (103) is produced by sampling the asynchronous data stream at a first clock rate (105), which is independent of the data stream clock rate (210). Using the sampled data stream (103), a recovered clock (107) is generated. The recovered clock (107) is then used to extract the digital information (111) from the sampled data stream (103).

Abstract: A DQPSK delay detection circuit is provided that can securely reproduce stable clock signal. An absolute value circuit ABS(14) calculates an absolute value of I signal. An absolute value circuit ABS(15) calculates an absolute value of Q signal. Subtraction circuit(16) generates a P signal according to the difference between the absolute values of I signal and Q signal. Zero-cross detection circuit(11) detects zero-cross timing of the P signal to input it as a timing signal to the DPLL(64). The zero-cross timing of the P signal can be detected even when the data pattern of I or Q signal makes it impossible to detect the zero-cross timing from I and Q signal. Because the zero-cross timing of the P signal has a variation less than that of the zero-cross timing determined from I or Q signal, it is becomes possible to reproduce stable clock signals and in turn reliability of data demodulation can be improved.

Abstract: Phase of first and second signals is compared by producing an output signal in the event of a predetermined phase relationship between the first and second signals and clearing the output signal at a predetermined phase during the cycle of the second signal regardless of the state of the first signal.

Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.